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-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini57
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini57
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini14
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats28
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr4
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout6
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini67
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt206
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini14
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats24
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr4
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout4
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini67
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt206
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini38
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout10
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini49
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout8
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini34
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt8
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini87
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt222
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini57
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini16
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini1
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr4
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout4
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini69
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt206
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/power/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini14
-rwxr-xr-xtests/quick/se/00.hello/ref/power/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini61
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt289
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats20
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini29
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt206
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats22
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout4
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt206
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini66
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt243
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini61
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt439
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt27
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini29
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt214
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini142
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt78
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini84
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt10
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini84
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout8
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt10
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini2
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats32
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout4
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini162
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr146
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simout6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt6
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats20
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr4
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout6
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt4
130 files changed, 2653 insertions, 2586 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index ab195624f..a18c9a2f4 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index 05dfd62f0..fa2cf12dd 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:12
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:17:23
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 6769b3cad..b21e4d084 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18737000 # Number of ticks simulated
final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 37767 # Simulator instruction rate (inst/s)
-host_op_rate 37763 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 110721753 # Simulator tick rate (ticks/s)
-host_mem_usage 213516 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 42684 # Simulator instruction rate (inst/s)
+host_op_rate 42679 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 125129111 # Simulator tick rate (ticks/s)
+host_mem_usage 269636 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 39920.04 # Average gap between requests
+system.cpu.branchPred.lookups 1632 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1266 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 352 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 27.804107 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 126 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 37475 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1632 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 8465ac1d0..beec6d00f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 9cdc62046..acb604328 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:12
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:07:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 56f807ea0..a295cf48e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu
sim_ticks 15802500 # Number of ticks simulated
final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 38730 # Simulator instruction rate (inst/s)
-host_op_rate 38726 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96032767 # Simulator tick rate (ticks/s)
-host_mem_usage 214332 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 36566 # Simulator instruction rate (inst/s)
+host_op_rate 36562 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 90663114 # Simulator tick rate (ticks/s)
+host_mem_usage 270656 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 32145.79 # Average gap between requests
+system.cpu.branchPred.lookups 2927 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 757 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 31606 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2927 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 8484e6949..38823b11f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -106,7 +112,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index 5f9ceb0b2..dc9014a9b 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:12
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:33:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index e13838fa4..4cd56283e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57981 # Simulator instruction rate (inst/s)
-host_op_rate 57971 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29099028 # Simulator tick rate (ticks/s)
-host_mem_usage 214184 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 84722 # Simulator instruction rate (inst/s)
+host_op_rate 84702 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42507676 # Simulator tick rate (ticks/s)
+host_mem_usage 261184 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 9c198f1c4..52003673d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index 6e22a3518..f494b4cd3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Jan/14/2013 08:12:30
+Real time: Jan/23/2013 13:45:24
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours: 0.000141667
-Virtual_time_in_days: 5.90278e-06
+Virtual_time_in_seconds: 0.52
+Virtual_time_in_minutes: 0.00866667
+Virtual_time_in_hours: 0.000144444
+Virtual_time_in_days: 6.01852e-06
Ruby_current_time: 143853
Ruby_start_time: 0
Ruby_cycles: 143853
-mbytes_resident: 54.9062
-mbytes_total: 274.051
-resident_ratio: 0.200393
+mbytes_resident: 55.0117
+mbytes_total: 274.062
+resident_ratio: 0.20077
ruby_cycles_executed: [ 143854 ]
@@ -86,10 +86,10 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11208
+page_reclaims: 11797
page_faults: 0
swaps: 0
-block_inputs: 0
+block_inputs: 8
block_outputs: 88
Network Stats
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index e45cd058f..5da3f0737 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -1,2 +1,6 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index c7e4dff49..070ea92d3 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 1 2012 13:41:29
-gem5 started Sep 1 2012 13:43:15
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:23
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 2a07a4255..b67c90410 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu
sim_ticks 143853 # Number of ticks simulated
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 34510 # Simulator instruction rate (inst/s)
-host_op_rate 34507 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 776735 # Simulator tick rate (ticks/s)
-host_mem_usage 280632 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 28953 # Simulator instruction rate (inst/s)
+host_op_rate 28951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 651686 # Simulator tick rate (ticks/s)
+host_mem_usage 280644 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 92dcab639..c41a1c22b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -92,23 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -124,25 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -151,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -193,7 +184,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index 891277ac4..fc43aac0c 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:12
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:47
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 34409000 because target called exit()
+Exiting @ tick 32544000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index aa2f4f81d..afd21634e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
sim_ticks 32544000 # Number of ticks simulated
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68117 # Simulator instruction rate (inst/s)
-host_op_rate 68101 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 346770993 # Simulator tick rate (ticks/s)
-host_mem_usage 218620 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 97330 # Simulator instruction rate (inst/s)
+host_op_rate 97300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 495402774 # Simulator tick rate (ticks/s)
+host_mem_usage 269640 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
@@ -160,104 +160,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
-system.cpu.dcache.overall_hits::total 1880 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
-system.cpu.dcache.overall_misses::total 168 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
@@ -383,5 +285,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
+system.cpu.dcache.overall_hits::total 1880 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
+system.cpu.dcache.overall_misses::total 168 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 4d782f4dd..1e20bfae8 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 8f40149c5..cb5c70de3 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:24
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:48:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index f9cbb8511..0c67bfe34 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu
sim_ticks 9059000 # Number of ticks simulated
final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28083 # Simulator instruction rate (inst/s)
-host_op_rate 28078 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 106544733 # Simulator tick rate (ticks/s)
-host_mem_usage 213348 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 18337 # Simulator instruction rate (inst/s)
+host_op_rate 18335 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69572663 # Simulator tick rate (ticks/s)
+host_mem_usage 270376 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33053.31 # Average gap between requests
+system.cpu.branchPred.lookups 1180 # Number of BP lookups
+system.cpu.branchPred.condPredicted 594 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 261 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 235 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 29.156328 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 4 # Nu
system.cpu.numCycles 18119 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 1180 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 325eb7b2e..81a4de4d4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -106,7 +112,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index 4dbe62d94..d9d6fa90d 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:15:42
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:35
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index cc1232526..70ee5a4ad 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 760610 # Simulator instruction rate (inst/s)
-host_op_rate 756680 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 379104629 # Simulator tick rate (ticks/s)
-host_mem_usage 204432 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
+host_inst_rate 34130 # Simulator instruction rate (inst/s)
+host_op_rate 34121 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17175609 # Simulator tick rate (ticks/s)
+host_mem_usage 260900 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index f9f9df412..45aed384d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 1f1d21982..86d41ea33 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jan/14/2013 08:12:30
+Real time: Jan/23/2013 13:29:25
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.42
-Virtual_time_in_minutes: 0.007
-Virtual_time_in_hours: 0.000116667
-Virtual_time_in_days: 4.86111e-06
+Virtual_time_in_seconds: 0.59
+Virtual_time_in_minutes: 0.00983333
+Virtual_time_in_hours: 0.000163889
+Virtual_time_in_days: 6.8287e-06
Ruby_current_time: 52498
Ruby_start_time: 0
Ruby_cycles: 52498
-mbytes_resident: 52.5664
-mbytes_total: 272.77
-resident_ratio: 0.192757
+mbytes_resident: 52.6836
+mbytes_total: 272.781
+resident_ratio: 0.193178
ruby_cycles_executed: [ 52499 ]
@@ -86,11 +86,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10106
-page_faults: 0
+page_reclaims: 11189
+page_faults: 18
swaps: 0
-block_inputs: 0
-block_outputs: 88
+block_inputs: 1600
+block_outputs: 128
Network Stats
-------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 31ae36f2e..3bd6641db 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -1,3 +1,7 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 71b6a1fe1..8e744dee3 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:25:55
-gem5 started Sep 9 2012 13:26:05
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 520abecf4..eab06dfe2 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu
sim_ticks 52498 # Number of ticks simulated
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 26806 # Simulator instruction rate (inst/s)
-host_op_rate 26801 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 545876 # Simulator tick rate (ticks/s)
-host_mem_usage 279320 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 10060 # Simulator instruction rate (inst/s)
+host_op_rate 10059 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 204912 # Simulator tick rate (ticks/s)
+host_mem_usage 279332 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 03e65dd55..adb7f583e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -92,23 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -124,25 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -151,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -193,7 +184,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index 95893429b..d3b147605 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:08:33
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:30
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 17541000 because target called exit()
+Exiting @ tick 16524000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 83ebc2ad9..005a80d9b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 16524000 # Number of ticks simulated
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93431 # Simulator instruction rate (inst/s)
-host_op_rate 93371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 598358642 # Simulator tick rate (ticks/s)
-host_mem_usage 217312 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 14244 # Simulator instruction rate (inst/s)
+host_op_rate 14243 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91318433 # Simulator tick rate (ticks/s)
+host_mem_usage 268332 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
@@ -160,104 +160,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
-system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
-system.cpu.dcache.overall_hits::total 627 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
-system.cpu.dcache.overall_misses::total 82 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
@@ -377,5 +279,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
+system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
+system.cpu.dcache.overall_hits::total 627 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
+system.cpu.dcache.overall_misses::total 82 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 773d3c5ec..49c4436f0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=system.cpu.checker
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,9 +113,28 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.checker]
type=O3Checker
children=dtb isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
@@ -598,7 +604,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index dbd9474aa..df6ac8e30 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:26:41
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13372000 because target called exit()
+Exiting @ tick 13354000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 3f637a122..cbe7a8e01 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000013 # Nu
sim_ticks 13354000 # Number of ticks simulated
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46154 # Simulator instruction rate (inst/s)
-host_op_rate 57584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 134203003 # Simulator tick rate (ticks/s)
-host_mem_usage 242404 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 22763 # Simulator instruction rate (inst/s)
+host_op_rate 28403 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66199618 # Simulator tick rate (ticks/s)
+host_mem_usage 285296 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33747.46 # Average gap between requests
+system.cpu.branchPred.lookups 2501 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
@@ -276,14 +285,6 @@ system.cpu.itb.accesses 0 # DT
system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 38f0d4bce..3da71cc39 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,7 +527,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index b1b5545bf..e90c24cf4 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:26:30
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13372000 because target called exit()
+Exiting @ tick 13354000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 730bbb524..a9f3432ad 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000013 # Nu
sim_ticks 13354000 # Number of ticks simulated
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53438 # Simulator instruction rate (inst/s)
-host_op_rate 66670 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 155374810 # Simulator tick rate (ticks/s)
-host_mem_usage 242400 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 20035 # Simulator instruction rate (inst/s)
+host_op_rate 24999 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58267208 # Simulator tick rate (ticks/s)
+host_mem_usage 285296 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33747.46 # Average gap between requests
+system.cpu.branchPred.lookups 2501 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -231,14 +240,6 @@ system.cpu.workload.num_syscalls 13 # Nu
system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index bda1e98df..8b4c27750 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=checker dtb interrupts itb tracer workload
+children=checker dtb interrupts isa itb tracer workload
+branchPred=Null
checker=system.cpu.checker
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -62,11 +65,11 @@ icache_port=system.membus.slave[1]
[system.cpu.checker]
type=DummyChecker
-children=dtb itb tracer
+children=dtb isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=-1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -74,6 +77,7 @@ dtb=system.cpu.checker.dtb
function_trace=false
function_trace_start=0
interrupts=Null
+isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -82,6 +86,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.checker.tracer
workload=system.cpu.workload
@@ -98,6 +103,23 @@ clock=500
num_squash_per_cycle=2
sys=system
+[system.cpu.checker.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.checker.itb]
type=ArmTLB
children=walker
@@ -129,6 +151,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -153,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 57c2a5d84..891f01e6f 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 15:18:10
-gem5 started Nov 1 2012 22:41:17
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:07
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 147a664f0..9c0909975 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135088 # Simulator instruction rate (inst/s)
-host_op_rate 168502 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 84394877 # Simulator tick rate (ticks/s)
-host_mem_usage 218472 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 1926 # Simulator instruction rate (inst/s)
+host_op_rate 2404 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1204405 # Simulator tick rate (ticks/s)
+host_mem_usage 275696 # Number of bytes of host memory used
+host_seconds 2.38 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index 1c831ee09..b76b7c5a6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,7 +120,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 3072fae00..38a423124 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:53
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:56
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index c3735e13f..1d0558bdb 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 116328 # Simulator instruction rate (inst/s)
-host_op_rate 145112 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72682624 # Simulator tick rate (ticks/s)
-host_mem_usage 217124 # Number of bytes of host memory used
+host_inst_rate 122854 # Simulator instruction rate (inst/s)
+host_op_rate 153228 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76735417 # Simulator tick rate (ticks/s)
+host_mem_usage 275692 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index bf0c1dcee..276d0c57a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index 92bf5cdb0..58b706eaf 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 27316000 because target called exit()
+Exiting @ tick 25969000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 059498d9f..2bce78814 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu
sim_ticks 25969000 # Number of ticks simulated
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 147661 # Simulator instruction rate (inst/s)
-host_op_rate 183366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 839095918 # Simulator tick rate (ticks/s)
-host_mem_usage 231680 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 66941 # Simulator instruction rate (inst/s)
+host_op_rate 83151 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 380602116 # Simulator tick rate (ticks/s)
+host_mem_usage 284140 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated
sim_ops 5672 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
@@ -170,112 +170,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
-system.cpu.dcache.overall_hits::total 1918 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
-system.cpu.dcache.overall_misses::total 141 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
@@ -404,5 +298,111 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
+system.cpu.dcache.overall_hits::total 1918 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
+system.cpu.dcache.overall_misses::total 141 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index df7d00601..0b4834ee5 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -165,21 +161,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -206,7 +197,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 75053b5ab..25f28ceed 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:08:52
-gem5 started Oct 30 2012 13:57:29
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:16:55
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 5bb87ba63..7f0e6e36f 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18578000 # Number of ticks simulated
final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59954 # Simulator instruction rate (inst/s)
-host_op_rate 59945 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 191522194 # Simulator tick rate (ticks/s)
-host_mem_usage 214528 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 49489 # Simulator instruction rate (inst/s)
+host_op_rate 49481 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 158085302 # Simulator tick rate (ticks/s)
+host_mem_usage 270352 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 40665.93 # Average gap between requests
+system.cpu.branchPred.lookups 1154 # Number of BP lookups
+system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 336 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -207,14 +216,6 @@ system.cpu.workload.num_syscalls 8 # Nu
system.cpu.numCycles 37157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1154 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 858 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 603 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 877 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 336 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 38.312429 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 3748def17..9962046c6 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -492,7 +497,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index f2fe39e9e..3edf11a35 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:13:46
-gem5 started Jan 4 2013 21:58:53
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:06
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index f897666a8..8a152a960 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 16532500 # Number of ticks simulated
final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25568 # Simulator instruction rate (inst/s)
-host_op_rate 25564 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 81956278 # Simulator tick rate (ticks/s)
-host_mem_usage 217336 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 36398 # Simulator instruction rate (inst/s)
+host_op_rate 36393 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 116675957 # Simulator tick rate (ticks/s)
+host_mem_usage 271376 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34566.18 # Average gap between requests
+system.cpu.branchPred.lookups 2120 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1453 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 517 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 31.314355 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -207,14 +216,6 @@ system.cpu.workload.num_syscalls 8 # Nu
system.cpu.numCycles 33066 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2120 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 517 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index f3b5a12e3..781c5e460 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,11 @@ size=64
[system.cpu.interrupts]
type=MipsInterrupts
+[system.cpu.isa]
+type=MipsISA
+num_threads=1
+num_vpes=1
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -106,7 +114,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 9e8404456..2d983a191 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:00:38
-gem5 started Aug 13 2012 18:11:50
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:17
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 2c73dba58..773dc4053 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 264545 # Simulator instruction rate (inst/s)
-host_op_rate 264338 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 132069950 # Simulator tick rate (ticks/s)
-host_mem_usage 214924 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 85249 # Simulator instruction rate (inst/s)
+host_op_rate 85225 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42601271 # Simulator tick rate (ticks/s)
+host_mem_usage 261900 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 59f6aa1fe..548d89a25 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index e45cd058f..5da3f0737 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -1,2 +1,6 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index df094012d..bc8425f96 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:41:09
-gem5 started Sep 9 2012 13:41:16
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:40
gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 6c61d4a4f..1047d276e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu
sim_ticks 125334 # Number of ticks simulated
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 23120 # Simulator instruction rate (inst/s)
-host_op_rate 23118 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 498325 # Simulator tick rate (ticks/s)
-host_mem_usage 282364 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 34119 # Simulator instruction rate (inst/s)
+host_op_rate 34115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 735344 # Simulator tick rate (ticks/s)
+host_mem_usage 282376 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 5e0921373..050099df0 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -92,23 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,11 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=MipsInterrupts
+[system.cpu.isa]
+type=MipsISA
+num_threads=1
+num_vpes=1
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -124,25 +122,20 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -151,10 +144,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -193,7 +186,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 15c5cb118..3cdc50c15 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:00:38
-gem5 started Aug 13 2012 18:12:01
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:28
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 33399000 because target called exit()
+Exiting @ tick 31633000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index b337ea793..45395bf9c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 284864 # Simulator instruction rate (inst/s)
-host_op_rate 284628 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1547353604 # Simulator tick rate (ticks/s)
-host_mem_usage 219460 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 3112 # Simulator instruction rate (inst/s)
+host_op_rate 3112 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16931146 # Simulator tick rate (ticks/s)
+host_mem_usage 270356 # Number of bytes of host memory used
+host_seconds 1.87 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
@@ -146,104 +146,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
-system.cpu.dcache.overall_hits::total 1950 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
-system.cpu.dcache.overall_misses::total 138 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
@@ -369,5 +271,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
+system.cpu.dcache.overall_hits::total 1950 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.dcache.overall_misses::total 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index ed3b8ffac..073ffb5b4 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -31,23 +31,19 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
UnifiedTLB=true
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -70,23 +66,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -98,7 +86,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -127,6 +114,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -491,7 +496,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
+executable=tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 302c5d913..09e115be1 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:14:12
-gem5 started Jan 4 2013 21:59:04
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:33:02
+gem5 started Jan 23 2013 15:33:08
+gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 32c8057b9..2fa72cd37 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
sim_ticks 14065500 # Number of ticks simulated
final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28037 # Simulator instruction rate (inst/s)
-host_op_rate 28032 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 68062430 # Simulator tick rate (ticks/s)
-host_mem_usage 213288 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 44313 # Simulator instruction rate (inst/s)
+host_op_rate 44306 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 107578636 # Simulator tick rate (ticks/s)
+host_mem_usage 267272 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 31295.96 # Average gap between requests
+system.cpu.branchPred.lookups 2247 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 602 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -207,14 +216,6 @@ system.cpu.workload.num_syscalls 9 # Nu
system.cpu.numCycles 28132 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2247 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1810 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1863 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 602 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 85e19f079..de2e34e4d 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,12 +31,12 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
UnifiedTLB=true
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -44,6 +45,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -54,6 +56,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,6 +71,9 @@ size=64
[system.cpu.interrupts]
type=PowerInterrupts
+[system.cpu.isa]
+type=PowerISA
+
[system.cpu.itb]
type=PowerTLB
size=64
@@ -107,7 +113,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 0d5c52051..82ad348ff 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:02:09
-gem5 started Aug 13 2012 18:12:35
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:33:02
+gem5 started Jan 23 2013 15:33:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 626b229db..94ea423b8 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332855 # Simulator instruction rate (inst/s)
-host_op_rate 332536 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 166086520 # Simulator tick rate (ticks/s)
-host_mem_usage 209936 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 57024 # Simulator instruction rate (inst/s)
+host_op_rate 57013 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28496468 # Simulator tick rate (ticks/s)
+host_mem_usage 257792 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 505121624..a9336e1ed 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,16 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -75,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -87,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -94,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -125,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -148,6 +145,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -159,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -200,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index ff91b8c31..7978eda39 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:02
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index f975c5003..0a19f6727 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000016 # Nu
sim_ticks 16286500 # Number of ticks simulated
final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32524 # Simulator instruction rate (inst/s)
-host_op_rate 32520 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 99417983 # Simulator tick rate (ticks/s)
-host_mem_usage 221588 # Number of bytes of host memory used
+host_inst_rate 32843 # Simulator instruction rate (inst/s)
+host_op_rate 32839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100387600 # Simulator tick rate (ticks/s)
+host_mem_usage 278524 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 38380.61 # Average gap between requests
+system.cpu.branchPred.lookups 1636 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 584 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 32574 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1636 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
@@ -256,19 +257,19 @@ system.cpu.stage4.runCycles 3157 # Nu
system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use
-system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits
-system.cpu.icache.overall_hits::total 896 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits
+system.cpu.icache.overall_hits::total 895 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
@@ -281,18 +282,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18347500
system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency
@@ -325,12 +326,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
@@ -338,112 +339,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
-system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
-system.cpu.dcache.overall_hits::total 914 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
-system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
@@ -572,5 +467,111 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
+system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
+system.cpu.dcache.overall_hits::total 914 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
+system.cpu.dcache.overall_misses::total 474 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 5620e85e4..d5e3e4b20 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 3359de27e..805340a73 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:14
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index a4c6ca2b7..bd3dfe2fe 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63026 # Simulator instruction rate (inst/s)
-host_op_rate 63015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31868954 # Simulator tick rate (ticks/s)
-host_mem_usage 212680 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 73566 # Simulator instruction rate (inst/s)
+host_op_rate 73547 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37192728 # Simulator tick rate (ticks/s)
+host_mem_usage 269044 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index f73262840..d14b371f2 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index c5c22fe69..1fd961fd8 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jan/14/2013 08:36:36
+Real time: Jan/23/2013 16:01:36
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.57
-Virtual_time_in_minutes: 0.0095
-Virtual_time_in_hours: 0.000158333
-Virtual_time_in_days: 6.59722e-06
+Virtual_time_in_seconds: 0.47
+Virtual_time_in_minutes: 0.00783333
+Virtual_time_in_hours: 0.000130556
+Virtual_time_in_days: 5.43981e-06
Ruby_current_time: 107952
Ruby_start_time: 0
Ruby_cycles: 107952
-mbytes_resident: 55.6602
-mbytes_total: 282.727
-resident_ratio: 0.196911
+mbytes_resident: 57.3125
+mbytes_total: 282.734
+resident_ratio: 0.202749
ruby_cycles_executed: [ 107953 ]
@@ -86,11 +86,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11405
+page_reclaims: 10848
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 88
+block_outputs: 96
Network Stats
-------------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index 18fb5a397..34599be55 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 78e09ef17..ce6a7813a 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 20687 # Simulator instruction rate (inst/s)
-host_op_rate 20685 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 419155 # Simulator tick rate (ticks/s)
-host_mem_usage 289516 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
+host_inst_rate 30407 # Simulator instruction rate (inst/s)
+host_op_rate 30404 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 616066 # Simulator tick rate (ticks/s)
+host_mem_usage 289524 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index bf88dfd5e..3ba498627 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -94,21 +92,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -128,21 +124,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index ff092cd6d..411439c6e 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index df9fd5f9b..4cc5c5030 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85623 # Simulator instruction rate (inst/s)
-host_op_rate 85602 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 446634768 # Simulator tick rate (ticks/s)
-host_mem_usage 221096 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 116604 # Simulator instruction rate (inst/s)
+host_op_rate 116555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 608021957 # Simulator tick rate (ticks/s)
+host_mem_usage 277492 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
@@ -128,104 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
-system.cpu.dcache.overall_hits::total 1253 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
-system.cpu.dcache.overall_misses::total 135 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
@@ -354,5 +256,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
+system.cpu.dcache.overall_hits::total 1253 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
+system.cpu.dcache.overall_misses::total 135 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 2a2790447..f7966bf07 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,7 +519,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 8a267af68..7ce584d65 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:09:04
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:48:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 59d569d41..44632e460 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu
sim_ticks 15014000 # Number of ticks simulated
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15963 # Simulator instruction rate (inst/s)
-host_op_rate 28915 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44538984 # Simulator tick rate (ticks/s)
-host_mem_usage 232848 # Number of bytes of host memory used
-host_seconds 0.34 # Real time elapsed on the host
+host_inst_rate 24822 # Simulator instruction rate (inst/s)
+host_op_rate 44962 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69258779 # Simulator tick rate (ticks/s)
+host_mem_usage 286624 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33318.89 # Average gap between requests
+system.cpu.branchPred.lookups 3018 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3018 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2500 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 796 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 31.840000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 30029 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3018 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index dd6c42ca1..f7b3c0261 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index acc9eb28e..463bf7a2c 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:20:22
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:30:54
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index da7f09764..bc4bb0d66 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
sim_ticks 5614500 # Number of ticks simulated
final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95396 # Simulator instruction rate (inst/s)
-host_op_rate 172737 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 99466308 # Simulator tick rate (ticks/s)
-host_mem_usage 263448 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 59484 # Simulator instruction rate (inst/s)
+host_op_rate 107725 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62039506 # Simulator tick rate (ticks/s)
+host_mem_usage 277020 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index f8bb08914..1d6c5844f 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 48dddeab7..5e5659352 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jan/14/2013 08:41:48
+Real time: Jan/23/2013 16:34:52
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours: 0.000169444
-Virtual_time_in_days: 7.06019e-06
+Virtual_time_in_seconds: 0.54
+Virtual_time_in_minutes: 0.009
+Virtual_time_in_hours: 0.00015
+Virtual_time_in_days: 6.25e-06
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
-mbytes_resident: 66.375
-mbytes_total: 290.48
-resident_ratio: 0.228541
+mbytes_resident: 66.3984
+mbytes_total: 290.648
+resident_ratio: 0.22849
ruby_cycles_executed: [ 121760 ]
@@ -89,11 +89,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13678
+page_reclaims: 13733
page_faults: 0
swaps: 0
-block_inputs: 240
-block_outputs: 152
+block_inputs: 0
+block_outputs: 88
Network Stats
-------------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 55cf80cf6..931a144eb 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:12:43
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:34:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 538b5b79e..ab8211afd 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 22533 # Simulator instruction rate (inst/s)
-host_op_rate 40812 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 509771 # Simulator tick rate (ticks/s)
-host_mem_usage 297456 # Number of bytes of host memory used
-host_seconds 0.24 # Real time elapsed on the host
+host_inst_rate 27688 # Simulator instruction rate (inst/s)
+host_op_rate 50147 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 626365 # Simulator tick rate (ticks/s)
+host_mem_usage 297628 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index f8e4933ef..46354ed27 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index dd8505ccc..9b198f409 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:20:12
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:18:31
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index ce11ecf17..30a2c344a 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
sim_ticks 28357000 # Number of ticks simulated
final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86866 # Simulator instruction rate (inst/s)
-host_op_rate 157296 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 457476490 # Simulator tick rate (ticks/s)
-host_mem_usage 271900 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 55225 # Simulator instruction rate (inst/s)
+host_op_rate 100013 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 290910277 # Simulator tick rate (ticks/s)
+host_mem_usage 285604 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
@@ -128,104 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
-system.cpu.dcache.overall_hits::total 1853 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
-system.cpu.dcache.overall_misses::total 134 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
@@ -351,5 +253,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
+system.cpu.dcache.overall_hits::total 1853 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
+system.cpu.dcache.overall_misses::total 134 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 431cc37fd..4cb5e1d1b 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,22 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa0 system.cpu.isa1
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -96,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=2
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -115,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -124,6 +113,24 @@ workload=system.cpu.workload0 system.cpu.workload1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=2
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -131,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -425,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -448,6 +445,12 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa0]
+type=AlphaISA
+
+[system.cpu.isa1]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -459,21 +462,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -500,7 +498,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +517,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index d895f3126..d90ba5e01 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 14:46:44
-gem5 started Nov 1 2012 15:18:34
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:39:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index b523abef7..18c747e94 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
sim_ticks 19857000 # Number of ticks simulated
final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 50642 # Simulator instruction rate (inst/s)
-host_op_rate 50640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 78893380 # Simulator tick rate (ticks/s)
-host_mem_usage 214784 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 38427 # Simulator instruction rate (inst/s)
+host_op_rate 38425 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59863252 # Simulator tick rate (ticks/s)
+host_mem_usage 271256 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 20387.35 # Average gap between requests
+system.cpu.branchPred.lookups 6348 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 874 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -222,14 +231,6 @@ system.cpu.workload1.num_syscalls 17 # Nu
system.cpu.numCycles 39715 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6348 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered
@@ -712,114 +713,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 60835.195200
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements::0 0 # number of replacements
-system.cpu.dcache.replacements::1 0 # number of replacements
-system.cpu.dcache.replacements::total 0 # number of replacements
-system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits
-system.cpu.dcache.overall_hits::total 4387 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses
-system.cpu.dcache.overall_misses::total 1035 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements::0 0 # number of replacements
system.cpu.l2cache.replacements::1 0 # number of replacements
system.cpu.l2cache.replacements::total 0 # number of replacements
@@ -947,5 +840,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47651.405145
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements::0 0 # number of replacements
+system.cpu.dcache.replacements::1 0 # number of replacements
+system.cpu.dcache.replacements::total 0 # number of replacements
+system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits
+system.cpu.dcache.overall_hits::total 4387 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses
+system.cpu.dcache.overall_misses::total 1035 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index b0053eeff..18f84cb91 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,16 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -75,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -87,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -94,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -125,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -148,6 +145,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -159,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -200,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
index 3730e9192..637eeae2b 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:09:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 87550aab2..3353b4aad 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
sim_ticks 22838500 # Number of ticks simulated
final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15645 # Simulator instruction rate (inst/s)
-host_op_rate 15645 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23565036 # Simulator tick rate (ticks/s)
-host_mem_usage 221420 # Number of bytes of host memory used
-host_seconds 0.97 # Real time elapsed on the host
+host_inst_rate 21741 # Simulator instruction rate (inst/s)
+host_op_rate 21740 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32746771 # Simulator tick rate (ticks/s)
+host_mem_usage 278448 # Number of bytes of host memory used
+host_seconds 0.70 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2327934 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11337934 # Sum of mem lat for all requests
+system.physmem.totQLat 2325934 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
system.physmem.totBankLat 7266000 # Total cycles spent in bank access
-system.physmem.avgQLat 5339.30 # Average queueing delay per request
+system.physmem.avgQLat 5334.71 # Average queueing delay per request
system.physmem.avgBankLat 16665.14 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26004.44 # Average memory access latency
+system.physmem.avgMemAccLat 25999.85 # Average memory access latency
system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s
@@ -185,19 +185,20 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 52305.05 # Average gap between requests
+system.cpu.branchPred.lookups 5147 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2720 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 45678 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 5149 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 3529 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 2365 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 4104 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 2723 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 173 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 66.349903 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 2896 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
@@ -207,21 +208,21 @@ system.cpu.regfile_manager.floatRegFileWrites 0
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3844 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 1540 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedTakenIncorrect 1541 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 2302 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 1056 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 68.552710 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted 2303 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 1055 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 68.582490 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 11045 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21901 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28111 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 17567 # Number of cycles cpu stages are processed.
-system.cpu.activity 38.458339 # Percentage of cycles cpu is active
+system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 17569 # Number of cycles cpu stages are processed.
+system.cpu.activity 38.462717 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
@@ -239,66 +240,66 @@ system.cpu.cpi_total 3.012663 # CP
system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 32253 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 13425 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 29.390516 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 36325 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 20.475940 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 36875 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 19.271860 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 36370 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 9308 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 20.377425 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 172.580385 # Cycle average of tags in use
-system.cpu.icache.total_refs 2999 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use
+system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.030100 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 172.580385 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.084268 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.084268 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 2999 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 2999 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 2999 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 2999 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 2999 # number of overall hits
-system.cpu.icache.overall_hits::total 2999 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 3004 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 3004 # number of overall hits
+system.cpu.icache.overall_hits::total 3004 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
system.cpu.icache.overall_misses::total 381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18870500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18870500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18870500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18870500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18870500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18870500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 3380 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 3380 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 3380 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 3380 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 3380 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 3380 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112722 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.112722 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.112722 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.112722 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.112722 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.112722 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49528.871391 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49528.871391 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49528.871391 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49528.871391 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 3385 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 3385 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 3385 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112555 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency
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-system.cpu.l2cache.ReadReq_avg_miss_latency::total 50348.011364 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 50683.066362 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 50683.066362 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11107481 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13289049 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11107481 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16671113 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11107481 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16671113 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37148.765886 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37752.980114 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 37d5abdb3..5411a2821 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -490,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index c7e6fdca4..757e1f2b0 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 21:59:36
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:08:16
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index a62497bbb..368690106 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
sim_ticks 23180500 # Number of ticks simulated
final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 21899 # Simulator instruction rate (inst/s)
-host_op_rate 21897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35159544 # Simulator tick rate (ticks/s)
-host_mem_usage 223288 # Number of bytes of host memory used
-host_seconds 0.66 # Real time elapsed on the host
+host_inst_rate 20805 # Simulator instruction rate (inst/s)
+host_op_rate 20805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33406458 # Simulator tick rate (ticks/s)
+host_mem_usage 278444 # Number of bytes of host memory used
+host_seconds 0.69 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 47868.53 # Average gap between requests
+system.cpu.branchPred.lookups 6759 # Number of BP lookups
+system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2448 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 46362 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6759 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index eec9abdb9..a6e90c248 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index a099312ec..b525c9dd9 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:06
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index fb1046e47..9a48953c1 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19584 # Simulator instruction rate (inst/s)
-host_op_rate 19584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9831731 # Simulator tick rate (ticks/s)
-host_mem_usage 212388 # Number of bytes of host memory used
-host_seconds 0.77 # Real time elapsed on the host
+host_inst_rate 30969 # Simulator instruction rate (inst/s)
+host_op_rate 30968 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15546804 # Simulator tick rate (ticks/s)
+host_mem_usage 268968 # Number of bytes of host memory used
+host_seconds 0.49 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 0cf9ff042..fd5e57b82 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -94,21 +92,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -128,21 +124,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index 8494e13f4..2651935f3 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 54610aef7..d366271d4 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 17560 # Simulator instruction rate (inst/s)
-host_op_rate 17560 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47909450 # Simulator tick rate (ticks/s)
-host_mem_usage 220988 # Number of bytes of host memory used
-host_seconds 0.86 # Real time elapsed on the host
+host_inst_rate 26295 # Simulator instruction rate (inst/s)
+host_op_rate 26295 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71739884 # Simulator tick rate (ticks/s)
+host_mem_usage 277420 # Number of bytes of host memory used
+host_seconds 0.58 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
@@ -128,108 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
-system.cpu.dcache.overall_hits::total 3529 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
-system.cpu.dcache.overall_misses::total 138 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
@@ -355,5 +253,107 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
+system.cpu.dcache.overall_hits::total 3529 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.dcache.overall_misses::total 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 74f1370ce..dd37fedf9 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[1]
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu0.workload
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -458,7 +463,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
@@ -471,22 +476,18 @@ uid=100
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -509,23 +510,15 @@ forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -537,7 +530,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -566,6 +558,24 @@ workload=system.cpu0.workload
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -892,22 +902,18 @@ type=ExeTracer
[system.cpu2]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -930,23 +936,15 @@ forwardComSize=5
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -958,7 +956,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -987,6 +984,24 @@ workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
icache_port=system.cpu2.icache.cpu_side
+[system.cpu2.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu2.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -1313,22 +1328,18 @@ type=ExeTracer
[system.cpu3]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu3.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -1351,23 +1362,15 @@ forwardComSize=5
fuPool=system.cpu3.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu3.interrupts
isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -1379,7 +1382,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -1408,6 +1410,24 @@ workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
icache_port=system.cpu3.icache.cpu_side
+[system.cpu3.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu3.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 4d35b5bd4..9fd6655b7 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 21:59:48
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index a08676b4f..3f4fe5ffb 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000105 # Nu
sim_ticks 104832500 # Number of ticks simulated
final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49068 # Simulator instruction rate (inst/s)
-host_op_rate 49068 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4970400 # Simulator tick rate (ticks/s)
-host_mem_usage 237836 # Number of bytes of host memory used
-host_seconds 21.09 # Real time elapsed on the host
+host_inst_rate 81452 # Simulator instruction rate (inst/s)
+host_op_rate 81452 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8250764 # Simulator tick rate (ticks/s)
+host_mem_usage 293492 # Number of bytes of host memory used
+host_seconds 12.71 # Real time elapsed on the host
sim_insts 1034907 # Number of instructions simulated
sim_ops 1034907 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
@@ -215,18 +215,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 159035.66 # Average gap between requests
+system.cpu0.branchPred.lookups 82004 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 209666 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered
@@ -690,17 +691,18 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 52905 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.numCycles 174086 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered
@@ -1163,17 +1165,18 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.branchPred.lookups 43658 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.numCycles 173761 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits
-system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered
@@ -1637,17 +1640,18 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.branchPred.lookups 53689 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits
+system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.numCycles 173451 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits
-system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target.
-system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 6cfde7057..606c05841 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[1]
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer workload
+children=dcache dtb icache interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
@@ -67,21 +70,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -98,21 +96,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -121,6 +114,9 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=SparcInterrupts
+[system.cpu0.isa]
+type=SparcISA
+
[system.cpu0.itb]
type=SparcTLB
size=64
@@ -136,7 +132,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
@@ -149,11 +145,11 @@ uid=100
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -162,6 +158,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -172,6 +169,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
@@ -186,21 +184,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -217,21 +210,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -240,6 +228,9 @@ mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=SparcInterrupts
+[system.cpu1.isa]
+type=SparcISA
+
[system.cpu1.itb]
type=SparcTLB
size=64
@@ -249,11 +240,11 @@ type=ExeTracer
[system.cpu2]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=2
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -262,6 +253,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -272,6 +264,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu2.tracer
width=1
@@ -286,21 +279,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
@@ -317,21 +305,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
@@ -340,6 +323,9 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu2.interrupts]
type=SparcInterrupts
+[system.cpu2.isa]
+type=SparcISA
+
[system.cpu2.itb]
type=SparcTLB
size=64
@@ -349,11 +335,11 @@ type=ExeTracer
[system.cpu3]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=3
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -362,6 +348,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
+isa=system.cpu3.isa
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -372,6 +359,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu3.tracer
width=1
@@ -386,21 +374,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
@@ -417,21 +400,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
@@ -440,6 +418,9 @@ mem_side=system.toL2Bus.slave[6]
[system.cpu3.interrupts]
type=SparcInterrupts
+[system.cpu3.isa]
+type=SparcISA
+
[system.cpu3.itb]
type=SparcTLB
size=64
@@ -454,21 +435,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index c63257902..e013c98f2 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:09:53
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index bb7e4e4f9..45b73a0af 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 174734 # Simulator instruction rate (inst/s)
-host_op_rate 174733 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 22625965 # Simulator tick rate (ticks/s)
-host_mem_usage 1150028 # Number of bytes of host memory used
-host_seconds 3.88 # Real time elapsed on the host
+host_inst_rate 205117 # Simulator instruction rate (inst/s)
+host_op_rate 205116 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26560282 # Simulator tick rate (ticks/s)
+host_mem_usage 1206900 # Number of bytes of host memory used
+host_seconds 3.30 # Real time elapsed on the host
sim_insts 677327 # Number of instructions simulated
sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 244af9704..c755fbf49 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[1]
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer workload
+children=dcache dtb icache interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=system.cpu0.workload
@@ -63,21 +66,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -94,21 +92,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -117,6 +110,9 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=SparcInterrupts
+[system.cpu0.isa]
+type=SparcISA
+
[system.cpu0.itb]
type=SparcTLB
size=64
@@ -132,7 +128,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
@@ -145,11 +141,11 @@ uid=100
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -157,6 +153,7 @@ dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -165,6 +162,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=system.cpu0.workload
@@ -178,21 +176,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -209,21 +202,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -232,6 +220,9 @@ mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=SparcInterrupts
+[system.cpu1.isa]
+type=SparcISA
+
[system.cpu1.itb]
type=SparcTLB
size=64
@@ -241,11 +232,11 @@ type=ExeTracer
[system.cpu2]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=2
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -253,6 +244,7 @@ dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -261,6 +253,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu2.tracer
workload=system.cpu0.workload
@@ -274,21 +267,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
@@ -305,21 +293,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
@@ -328,6 +311,9 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu2.interrupts]
type=SparcInterrupts
+[system.cpu2.isa]
+type=SparcISA
+
[system.cpu2.itb]
type=SparcTLB
size=64
@@ -337,11 +323,11 @@ type=ExeTracer
[system.cpu3]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=3
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -349,6 +335,7 @@ dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
+isa=system.cpu3.isa
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -357,6 +344,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu3.tracer
workload=system.cpu0.workload
@@ -370,21 +358,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
@@ -401,21 +384,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
@@ -424,6 +402,9 @@ mem_side=system.toL2Bus.slave[6]
[system.cpu3.interrupts]
type=SparcInterrupts
+[system.cpu3.isa]
+type=SparcISA
+
[system.cpu3.itb]
type=SparcTLB
size=64
@@ -438,21 +419,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 3b151bc02..d217747b2 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:01
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:51:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 6b9b27a43..03a5c597b 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000262 # Nu
sim_ticks 261623500 # Number of ticks simulated
final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114971 # Simulator instruction rate (inst/s)
-host_op_rate 114971 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45557694 # Simulator tick rate (ticks/s)
-host_mem_usage 232524 # Number of bytes of host memory used
-host_seconds 5.74 # Real time elapsed on the host
+host_inst_rate 226128 # Simulator instruction rate (inst/s)
+host_op_rate 226126 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 89603226 # Simulator tick rate (ticks/s)
+host_mem_usage 289396 # Number of bytes of host memory used
+host_seconds 2.92 # Real time elapsed on the host
sim_insts 660239 # Number of instructions simulated
sim_ops 660239 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 8fc3158b8..07ef89806 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -16,7 +16,7 @@ kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
num_work_ids=16
readfile=
symbolfile=
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index 1eaf6be73..4a52344b3 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Jan/14/2013 08:13:32
+Real time: Jan/23/2013 14:04:13
Profiler Stats
--------------
-Elapsed_time_in_seconds: 46
-Elapsed_time_in_minutes: 0.766667
-Elapsed_time_in_hours: 0.0127778
-Elapsed_time_in_days: 0.000532407
+Elapsed_time_in_seconds: 79
+Elapsed_time_in_minutes: 1.31667
+Elapsed_time_in_hours: 0.0219444
+Elapsed_time_in_days: 0.000914352
-Virtual_time_in_seconds: 46.4
-Virtual_time_in_minutes: 0.773333
-Virtual_time_in_hours: 0.0128889
-Virtual_time_in_days: 0.000537037
+Virtual_time_in_seconds: 47.52
+Virtual_time_in_minutes: 0.792
+Virtual_time_in_hours: 0.0132
+Virtual_time_in_days: 0.00055
Ruby_current_time: 8664886
Ruby_start_time: 0
Ruby_cycles: 8664886
-mbytes_resident: 70.9336
-mbytes_total: 415.473
-resident_ratio: 0.170758
+mbytes_resident: 71.0234
+mbytes_total: 415.48
+resident_ratio: 0.170971
ruby_cycles_executed: [ 8664887 8664887 8664887 8664887 8664887 8664887 8664887 8664887 ]
@@ -82,13 +82,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1237687 average: 0.00723931
Resource Usage
--------------
page_size: 4096
-user_time: 46
+user_time: 47
system_time: 0
-page_reclaims: 10183
+page_reclaims: 10782
page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 200
+block_inputs: 16
+block_outputs: 720
Network Stats
-------------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
index cc306c62c..2794962f3 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 10 2012 16:31:57
-gem5 started Nov 10 2012 16:32:41
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:02:54
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 18c37b3f8..e20a29e2b 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.008665 # Nu
sim_ticks 8664886 # Number of ticks simulated
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 187879 # Simulator tick rate (ticks/s)
-host_mem_usage 425448 # Number of bytes of host memory used
-host_seconds 46.12 # Real time elapsed on the host
+host_tick_rate 109516 # Simulator tick rate (ticks/s)
+host_mem_usage 425456 # Number of bytes of host memory used
+host_seconds 79.12 # Real time elapsed on the host
system.ruby.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads
system.ruby.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes
system.ruby.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
index a24f176d8..120840f6d 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=
memories=system.physmem system.funcmem
num_work_ids=16
readfile=
@@ -32,7 +33,7 @@ system_port=system.membus.slave[1]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -53,23 +54,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.test
@@ -79,7 +75,7 @@ mem_side=system.toL2Bus.slave[0]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -100,23 +96,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.test
@@ -126,7 +117,7 @@ mem_side=system.toL2Bus.slave[1]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -147,23 +138,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.test
@@ -173,7 +159,7 @@ mem_side=system.toL2Bus.slave[2]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -194,23 +180,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.test
@@ -220,7 +201,7 @@ mem_side=system.toL2Bus.slave[3]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -241,23 +222,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu4.test
@@ -267,7 +243,7 @@ mem_side=system.toL2Bus.slave[4]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -288,23 +264,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu5.test
@@ -314,7 +285,7 @@ mem_side=system.toL2Bus.slave[5]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -335,23 +306,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu6.test
@@ -361,7 +327,7 @@ mem_side=system.toL2Bus.slave[6]
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
@@ -382,23 +348,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu7.test
@@ -417,7 +378,7 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
[system.funcmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=false
latency=30000
@@ -432,23 +393,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=65536
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
@@ -457,7 +413,7 @@ mem_side=system.membus.slave[0]
[system.membus]
type=CoherentBus
block_size=64
-clock=2
+clock=1000
header_cycles=1
use_default_range=false
width=16
@@ -467,7 +423,7 @@ slave=system.l2c.mem_side system.system_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@@ -480,7 +436,7 @@ port=system.membus.master[0]
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=2
+clock=500
header_cycles=1
use_default_range=false
width=16
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
index 41e8d0489..ac8f30c3e 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu0: completed 10000 read, 5290 write accesses @74885500
-system.cpu7: completed 10000 read, 5447 write accesses @78072500
-system.cpu2: completed 10000 read, 5330 write accesses @78536500
-system.cpu5: completed 10000 read, 5401 write accesses @79479500
-system.cpu3: completed 10000 read, 5406 write accesses @80479500
-system.cpu1: completed 10000 read, 5452 write accesses @80823500
-system.cpu4: completed 10000 read, 5330 write accesses @82914500
-system.cpu6: completed 10000 read, 5363 write accesses @83627000
-system.cpu7: completed 20000 read, 10668 write accesses @150917000
-system.cpu0: completed 20000 read, 10683 write accesses @151253500
-system.cpu5: completed 20000 read, 10718 write accesses @151911500
-system.cpu2: completed 20000 read, 10688 write accesses @152119000
-system.cpu3: completed 20000 read, 10954 write accesses @159391000
-system.cpu6: completed 20000 read, 10780 write accesses @160278500
-system.cpu1: completed 20000 read, 10888 write accesses @160835000
-system.cpu4: completed 20000 read, 10745 write accesses @162137000
-system.cpu2: completed 30000 read, 16060 write accesses @225600500
-system.cpu0: completed 30000 read, 16073 write accesses @226217000
-system.cpu7: completed 30000 read, 15898 write accesses @227550500
-system.cpu5: completed 30000 read, 16102 write accesses @230201000
-system.cpu3: completed 30000 read, 16375 write accesses @233880500
-system.cpu1: completed 30000 read, 16184 write accesses @234964500
-system.cpu6: completed 30000 read, 16132 write accesses @236785500
-system.cpu4: completed 30000 read, 16103 write accesses @242571500
-system.cpu7: completed 40000 read, 21206 write accesses @298942500
-system.cpu2: completed 40000 read, 21441 write accesses @299465500
-system.cpu0: completed 40000 read, 21388 write accesses @302202500
-system.cpu5: completed 40000 read, 21578 write accesses @308632000
-system.cpu6: completed 40000 read, 21492 write accesses @314697500
-system.cpu3: completed 40000 read, 22088 write accesses @315960000
-system.cpu4: completed 40000 read, 21590 write accesses @317147500
-system.cpu1: completed 40000 read, 21566 write accesses @317423500
-system.cpu7: completed 50000 read, 26570 write accesses @373251000
-system.cpu2: completed 50000 read, 26788 write accesses @373919000
-system.cpu0: completed 50000 read, 26897 write accesses @382805000
-system.cpu5: completed 50000 read, 27003 write accesses @384437500
-system.cpu3: completed 50000 read, 27349 write accesses @389623000
-system.cpu4: completed 50000 read, 26792 write accesses @389830500
-system.cpu6: completed 50000 read, 27002 write accesses @392270000
-system.cpu1: completed 50000 read, 26853 write accesses @392392000
-system.cpu7: completed 60000 read, 31855 write accesses @449936000
-system.cpu2: completed 60000 read, 32201 write accesses @452901500
-system.cpu0: completed 60000 read, 32209 write accesses @457331000
-system.cpu5: completed 60000 read, 32356 write accesses @458864500
-system.cpu4: completed 60000 read, 32204 write accesses @464577500
-system.cpu3: completed 60000 read, 32813 write accesses @468126500
-system.cpu6: completed 60000 read, 32463 write accesses @469913500
-system.cpu1: completed 60000 read, 32376 write accesses @472262000
-system.cpu7: completed 70000 read, 37203 write accesses @526760000
-system.cpu2: completed 70000 read, 37525 write accesses @530661000
-system.cpu5: completed 70000 read, 37749 write accesses @533141500
-system.cpu0: completed 70000 read, 37615 write accesses @537691500
-system.cpu3: completed 70000 read, 38216 write accesses @538787500
-system.cpu4: completed 70000 read, 37614 write accesses @545810500
-system.cpu6: completed 70000 read, 37722 write accesses @546307000
-system.cpu1: completed 70000 read, 37746 write accesses @546660500
-system.cpu7: completed 80000 read, 42460 write accesses @600681000
-system.cpu5: completed 80000 read, 42949 write accesses @604308500
-system.cpu2: completed 80000 read, 42841 write accesses @606628000
-system.cpu0: completed 80000 read, 43072 write accesses @615043500
-system.cpu3: completed 80000 read, 43808 write accesses @615907000
-system.cpu4: completed 80000 read, 43047 write accesses @622672500
-system.cpu6: completed 80000 read, 43213 write accesses @622720000
-system.cpu1: completed 80000 read, 43140 write accesses @626035000
-system.cpu2: completed 90000 read, 48140 write accesses @675974000
-system.cpu7: completed 90000 read, 48058 write accesses @680921000
-system.cpu5: completed 90000 read, 48486 write accesses @683376500
-system.cpu3: completed 90000 read, 49174 write accesses @687533500
-system.cpu0: completed 90000 read, 48447 write accesses @690023000
-system.cpu6: completed 90000 read, 48621 write accesses @702298000
-system.cpu4: completed 90000 read, 48429 write accesses @703717000
-system.cpu1: completed 90000 read, 48600 write accesses @705675000
-system.cpu2: completed 100000 read, 53454 write accesses @753126500
+system.cpu4: completed 10000 read, 5213 write accesses @76807500
+system.cpu7: completed 10000 read, 5302 write accesses @79251000
+system.cpu3: completed 10000 read, 5351 write accesses @81062000
+system.cpu5: completed 10000 read, 5541 write accesses @82066500
+system.cpu1: completed 10000 read, 5479 write accesses @82140500
+system.cpu2: completed 10000 read, 5270 write accesses @82209500
+system.cpu6: completed 10000 read, 5352 write accesses @82224000
+system.cpu0: completed 10000 read, 5437 write accesses @83502000
+system.cpu4: completed 20000 read, 10638 write accesses @152852500
+system.cpu7: completed 20000 read, 10671 write accesses @153245500
+system.cpu5: completed 20000 read, 10802 write accesses @155921500
+system.cpu1: completed 20000 read, 10780 write accesses @157898500
+system.cpu3: completed 20000 read, 10762 write accesses @158207000
+system.cpu2: completed 20000 read, 10562 write accesses @158441500
+system.cpu6: completed 20000 read, 10817 write accesses @160812000
+system.cpu0: completed 20000 read, 10942 write accesses @162138000
+system.cpu4: completed 30000 read, 15885 write accesses @226882500
+system.cpu7: completed 30000 read, 16162 write accesses @230488000
+system.cpu1: completed 30000 read, 15996 write accesses @231220000
+system.cpu5: completed 30000 read, 16227 write accesses @232272500
+system.cpu3: completed 30000 read, 16181 write accesses @234012000
+system.cpu6: completed 30000 read, 16285 write accesses @236458500
+system.cpu2: completed 30000 read, 16117 write accesses @236552000
+system.cpu0: completed 30000 read, 16426 write accesses @240306500
+system.cpu4: completed 40000 read, 21151 write accesses @301825500
+system.cpu7: completed 40000 read, 21649 write accesses @305825500
+system.cpu1: completed 40000 read, 21293 write accesses @308437500
+system.cpu3: completed 40000 read, 21436 write accesses @308497500
+system.cpu5: completed 40000 read, 21614 write accesses @310554000
+system.cpu2: completed 40000 read, 21323 write accesses @312243500
+system.cpu6: completed 40000 read, 21541 write accesses @312536000
+system.cpu0: completed 40000 read, 21919 write accesses @320331000
+system.cpu4: completed 50000 read, 26446 write accesses @376676500
+system.cpu7: completed 50000 read, 26971 write accesses @382643500
+system.cpu1: completed 50000 read, 26742 write accesses @382692500
+system.cpu3: completed 50000 read, 26868 write accesses @383729000
+system.cpu5: completed 50000 read, 26982 write accesses @388892000
+system.cpu2: completed 50000 read, 26690 write accesses @389746500
+system.cpu6: completed 50000 read, 26890 write accesses @390639500
+system.cpu0: completed 50000 read, 27239 write accesses @394395001
+system.cpu4: completed 60000 read, 31859 write accesses @454814000
+system.cpu3: completed 60000 read, 32157 write accesses @455574000
+system.cpu1: completed 60000 read, 32039 write accesses @458833000
+system.cpu7: completed 60000 read, 32494 write accesses @460248000
+system.cpu2: completed 60000 read, 32094 write accesses @465749500
+system.cpu5: completed 60000 read, 32378 write accesses @466634000
+system.cpu6: completed 60000 read, 32333 write accesses @468161500
+system.cpu0: completed 60000 read, 32569 write accesses @469644500
+system.cpu3: completed 70000 read, 37524 write accesses @531095000
+system.cpu4: completed 70000 read, 37387 write accesses @531724000
+system.cpu1: completed 70000 read, 37455 write accesses @534864500
+system.cpu2: completed 70000 read, 37386 write accesses @539742500
+system.cpu7: completed 70000 read, 38025 write accesses @540171500
+system.cpu5: completed 70000 read, 37779 write accesses @540661000
+system.cpu0: completed 70000 read, 37912 write accesses @543002000
+system.cpu6: completed 70000 read, 37876 write accesses @544926000
+system.cpu4: completed 80000 read, 42765 write accesses @607648000
+system.cpu3: completed 80000 read, 42947 write accesses @608627500
+system.cpu1: completed 80000 read, 42804 write accesses @612176500
+system.cpu5: completed 80000 read, 43215 write accesses @614679500
+system.cpu2: completed 80000 read, 42837 write accesses @616130500
+system.cpu7: completed 80000 read, 43372 write accesses @618251000
+system.cpu0: completed 80000 read, 43388 write accesses @620992000
+system.cpu6: completed 80000 read, 43420 write accesses @622851000
+system.cpu4: completed 90000 read, 48066 write accesses @681361000
+system.cpu3: completed 90000 read, 48251 write accesses @683201500
+system.cpu1: completed 90000 read, 48377 write accesses @690035500
+system.cpu5: completed 90000 read, 48546 write accesses @692142000
+system.cpu2: completed 90000 read, 48240 write accesses @693946000
+system.cpu7: completed 90000 read, 48816 write accesses @696757000
+system.cpu0: completed 90000 read, 48758 write accesses @697163500
+system.cpu6: completed 90000 read, 48649 write accesses @698059000
+system.cpu4: completed 100000 read, 53418 write accesses @758619000
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index 8e44f53e1..86075abc3 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 15 2012 19:23:25
-gem5 started Oct 15 2012 19:23:52
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:00
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 753126500 because maximum number of loads reached
+Exiting @ tick 758619000 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index cd5a28936..159c48ed1 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -4,9 +4,9 @@ sim_seconds 0.000759 # Nu
sim_ticks 758619000 # Number of ticks simulated
final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 151805189 # Simulator tick rate (ticks/s)
-host_mem_usage 345224 # Number of bytes of host memory used
-host_seconds 5.00 # Real time elapsed on the host
+host_tick_rate 45315591 # Simulator tick rate (ticks/s)
+host_mem_usage 399988 # Number of bytes of host memory used
+host_seconds 16.74 # Real time elapsed on the host
system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index 959a2542d..34ed5c5c4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jan/14/2013 08:13:02
+Real time: Jan/23/2013 14:07:36
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours: 0.000119444
-Virtual_time_in_days: 4.97685e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours: 0.000122222
+Virtual_time_in_days: 5.09259e-06
Ruby_current_time: 221941
Ruby_start_time: 0
Ruby_cycles: 221941
-mbytes_resident: 49.6133
-mbytes_total: 270.469
-resident_ratio: 0.183478
+mbytes_resident: 49.4375
+mbytes_total: 270.48
+resident_ratio: 0.18282
ruby_cycles_executed: [ 221942 ]
@@ -85,10 +85,10 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 9333
+page_reclaims: 10370
page_faults: 0
swaps: 0
-block_inputs: 0
+block_inputs: 24
block_outputs: 80
Network Stats
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index cfdf73ce9..8308e8186 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
@@ -1 +1,5 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 7d0232d91..5f78b5f64 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rub
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 1 2012 13:41:29
-gem5 started Sep 1 2012 13:48:35
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:07:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 12a80b158..1a84d2d44 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,8 +4,8 @@ sim_seconds 0.000222 # Nu
sim_ticks 221941 # Number of ticks simulated
final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 2209832 # Simulator tick rate (ticks/s)
-host_mem_usage 276964 # Number of bytes of host memory used
+host_tick_rate 2209091 # Simulator tick rate (ticks/s)
+host_mem_usage 276976 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes