diff options
Diffstat (limited to 'tests/quick/se')
15 files changed, 7624 insertions, 7412 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index dde2aed4b..3b67933ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25046000 # Number of ticks simulated -final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25485000 # Number of ticks simulated +final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22373 # Simulator instruction rate (inst/s) -host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87684145 # Simulator tick rate (ticks/s) -host_mem_usage 225308 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 27492 # Simulator instruction rate (inst/s) +host_op_rate 27490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109632626 # Simulator tick rate (ticks/s) +host_mem_usage 225100 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29952 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25031500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts +system.physmem.perBankRdBursts::5 19 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 19 # Per bank write bursts +system.physmem.perBankRdBursts::11 25 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 46 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 25470500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 469 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -150,48 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1857500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests -system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3960.55 # Average queueing delay per request -system.physmem.avgBankLat 16242.00 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25202.56 # Average memory access latency -system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 402 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 2272250 # Total ticks spent queuing +system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7645000 # Total ticks spent accessing banks +system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.20 # Data bus utilization in percentage +system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 385 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53372.07 # Average gap between requests -system.membus.throughput 1195879582 # Throughput (bytes/s) +system.physmem.avgGap 54308.10 # Average gap between requests +system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1175279576 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -202,10 +210,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.2 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -248,7 +256,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 50093 # number of cpu cycles simulated +system.cpu.numCycles 50971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -270,12 +278,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 14.724612 # Percentage of cycles cpu is active +system.cpu.activity 14.470974 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -287,36 +295,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -329,12 +337,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -347,12 +355,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -373,26 +381,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -407,21 +415,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -439,17 +447,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -472,17 +480,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,17 +510,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -524,27 +532,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -561,14 +569,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -585,19 +593,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -617,14 +625,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -633,14 +641,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 31fc74f80..0ff2f61a7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20671000 # Number of ticks simulated -final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21065000 # Number of ticks simulated +final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10783 # Simulator instruction rate (inst/s) -host_op_rate 10783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34979840 # Simulator tick rate (ticks/s) -host_mem_usage 229184 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 31290 # Simulator instruction rate (inst/s) +host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103426086 # Simulator tick rate (ticks/s) +host_mem_usage 226120 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 31168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20638000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 488 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69 # Per bank write bursts +system.physmem.perBankRdBursts::1 34 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 43 # Per bank write bursts +system.physmem.perBankRdBursts::5 21 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 24 # Per bank write bursts +system.physmem.perBankRdBursts::12 14 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 45 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21032000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 488 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,47 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2449250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests -system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7535000 # Total cycles spent in bank access -system.physmem.avgQLat 5018.95 # Average queueing delay per request -system.physmem.avgBankLat 15440.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25459.53 # Average memory access latency -system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.78 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 419 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation +system.physmem.totQLat 3258750 # Total ticks spent queuing +system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7590000 # Total ticks spent accessing banks +system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.58 # Data bus utilization in percentage +system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 403 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42290.98 # Average gap between requests -system.membus.throughput 1507812878 # Throughput (bytes/s) +system.physmem.avgGap 43098.36 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1479610729 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,39 +210,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2888 # Number of BP lookups -system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2884 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 756 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2082 # DTB read hits +system.cpu.dtb.read_hits 2076 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2129 # DTB read accesses +system.cpu.dtb.read_accesses 2123 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3145 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3223 # DTB accesses -system.cpu.itb.fetch_hits 2387 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2382 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2426 # ITB accesses +system.cpu.itb.fetch_accesses 2421 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -247,178 +256,178 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41343 # number of cpu cycles simulated +system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2764 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2623 # Number of cycles rename is running system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10787 # Type of FU issued -system.cpu.iq.rate 0.260915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 113 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10771 # Type of FU issued +system.cpu.iq.rate 0.255655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed @@ -427,57 +436,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3236 # number of memory reference insts executed -system.cpu.iew.exec_branches 1591 # Number of branches executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed +system.cpu.iew.exec_branches 1588 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.243983 # Inst execution rate -system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9625 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5058 # num instructions producing a value -system.cpu.iew.wb_consumers 6775 # num instructions consuming a value +system.cpu.iew.exec_rate 0.238945 # Inst execution rate +system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5048 # num instructions producing a value +system.cpu.iew.wb_consumers 6764 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,26 +497,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26435 # The number of ROB reads -system.cpu.rob.rob_writes 27385 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26469 # The number of ROB reads +system.cpu.rob.rob_writes 27366 # The number of ROB writes +system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12801 # number of integer regfile reads -system.cpu.int_regfile_writes 7277 # number of integer regfile writes +system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12780 # number of integer regfile reads +system.cpu.int_regfile_writes 7264 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -522,55 +531,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits -system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits +system.cpu.icache.overall_hits::total 1893 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -638,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -671,17 +680,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,17 +710,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -723,35 +732,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits -system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits +system.cpu.dcache.overall_hits::total 2230 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -760,43 +769,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -816,30 +825,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2906fdf0c..5e19e4b84 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11933500 # Number of ticks simulated -final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11990500 # Number of ticks simulated +final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3639 # Simulator instruction rate (inst/s) -host_op_rate 3638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18189727 # Simulator tick rate (ticks/s) -host_mem_usage 227880 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 47015 # Simulator instruction rate (inst/s) +host_op_rate 46988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 235942636 # Simulator tick rate (ticks/s) +host_mem_usage 225832 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 17472 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11844000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 273 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 1003461073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 453692507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457153580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1003461073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 453692507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457153580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 17472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 17472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 2 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 24 # Per bank write bursts +system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::8 61 # Per bank write bursts +system.physmem.perBankRdBursts::9 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 14 # Per bank write bursts +system.physmem.perBankRdBursts::11 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 12 # Per bank write bursts +system.physmem.perBankRdBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 11901000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 273 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,43 +152,51 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1190000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests -system.physmem.totBusLat 1365000 # Total cycles spent in databus access -system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 4358.97 # Average queueing delay per request -system.physmem.avgBankLat 15311.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24670.33 # Average memory access latency -system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 240 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 42 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.809524 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.784505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 471.889985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 54.76% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 2.38% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 3 7.14% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 2.38% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 2.38% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 4.76% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.38% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 2.38% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 2.38% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 2.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42 # Bytes accessed per row activation +system.physmem.totQLat 1695750 # Total ticks spent queuing +system.physmem.totMemAccLat 7213250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 4152500 # Total ticks spent accessing banks +system.physmem.avgQLat 6211.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15210.62 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26422.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1457.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1457.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 231 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43384.62 # Average gap between requests -system.membus.throughput 1464113630 # Throughput (bytes/s) +system.physmem.avgGap 43593.41 # Average gap between requests +system.physmem.pageHitRate 84.62 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1457153580 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -199,10 +209,10 @@ system.membus.data_through_bus 17472 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1175 # Number of BP lookups -system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.cpu.branchPred.lookups 1176 # Number of BP lookups +system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups system.cpu.branchPred.BTBHits 253 # Number of BTB hits @@ -218,18 +228,18 @@ system.cpu.dtb.read_hits 707 # DT system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations system.cpu.dtb.read_accesses 738 # DTB read accesses -system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_hits 368 # DTB write hits system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 391 # DTB write accesses -system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.write_accesses 388 # DTB write accesses +system.cpu.dtb.data_hits 1075 # DTB hits system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.dtb.data_accesses 1126 # DTB accesses +system.cpu.itb.fetch_hits 1065 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1097 # ITB accesses +system.cpu.itb.fetch_accesses 1095 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -243,96 +253,96 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23868 # number of cpu cycles simulated +system.cpu.numCycles 23982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 4347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.314945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6511 84.34% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1062 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5897 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6679 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6663 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2508 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 955 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 468 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4960 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4040 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1384 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.523316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.238697 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6098 78.99% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 566 7.33% 86.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 399 5.17% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 262 3.39% 94.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.58% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.57% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -368,69 +378,69 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2861 70.82% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.38% 90.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 395 9.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4046 # Type of FU issued -system.cpu.iq.rate 0.169516 # Inst issue rate +system.cpu.iq.FU_type_0::total 4040 # Type of FU issued +system.cpu.iq.rate 0.168460 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15885 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7299 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3649 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4077 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 540 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 174 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5302 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 955 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 468 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -438,43 +448,43 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 3849 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 391 # Number of stores executed -system.cpu.iew.exec_rate 0.161513 # Inst execution rate -system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1709 # num instructions producing a value -system.cpu.iew.wb_consumers 2209 # num instructions consuming a value +system.cpu.iew.exec_nop 336 # number of nop insts executed +system.cpu.iew.exec_refs 1127 # number of memory reference insts executed +system.cpu.iew.exec_branches 643 # Number of branches executed +system.cpu.iew.exec_stores 388 # Number of stores executed +system.cpu.iew.exec_rate 0.160495 # Inst execution rate +system.cpu.iew.wb_sent 3735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2206 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152406 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.774252 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.356490 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.198597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6357 87.97% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.35% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7226 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,23 +497,23 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12303 # The number of ROB reads -system.cpu.rob.rob_writes 11127 # The number of ROB writes -system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12212 # The number of ROB reads +system.cpu.rob.rob_writes 11099 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16262 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4674 # number of integer regfile reads -system.cpu.int_regfile_writes 2826 # number of integer regfile writes +system.cpu.cpi 10.046921 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.046921 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4665 # number of integer regfile reads +system.cpu.int_regfile_writes 2823 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1457153580 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -518,55 +528,55 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 93.236237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits -system.cpu.icache.overall_hits::total 816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses -system.cpu.icache.overall_misses::total 251 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits +system.cpu.icache.overall_hits::total 815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17655999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17655999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17655999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17655999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70623.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -575,48 +585,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 56 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13162749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 122.122128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.433851 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -628,17 +638,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4692750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17666750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19332500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19332500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -661,17 +671,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10604500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3946250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14550750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10604500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10604500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -713,27 +723,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.667407 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -750,14 +760,14 @@ system.cpu.dcache.demand_misses::cpu.data 194 # n system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses system.cpu.dcache.overall_misses::total 194 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7226000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5211250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12437250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12437250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -774,14 +784,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64109.536082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -806,14 +816,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6445000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6445000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -822,14 +832,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ca5a55de6..6f535bcb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19652 # Simulator instruction rate (inst/s) -host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70593484 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 41552 # Simulator instruction rate (inst/s) +host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153628168 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -302,179 +312,179 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -482,55 +492,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -541,93 +551,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -637,42 +647,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -682,61 +692,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,124 +761,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -877,16 +887,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -895,30 +905,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index add5a91d0..1007daea2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22159 # Simulator instruction rate (inst/s) -host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79599293 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 59313 # Simulator instruction rate (inst/s) +host_op_rate 73997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219275591 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -257,179 +267,179 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -437,55 +447,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -496,93 +506,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -592,42 +602,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -637,61 +647,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,124 +716,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -832,16 +842,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -850,30 +860,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index aeb0e2e25..3c2a96518 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24587000 # Number of ticks simulated -final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24975000 # Number of ticks simulated +final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52979 # Simulator instruction rate (inst/s) -host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223940501 # Simulator tick rate (ticks/s) -host_mem_usage 224928 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 84511 # Simulator instruction rate (inst/s) +host_op_rate 84494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362882134 # Simulator tick rate (ticks/s) +host_mem_usage 254488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29120 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24519000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 8 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 12 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts +system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::9 75 # Per bank write bursts +system.physmem.perBankRdBursts::10 36 # Per bank write bursts +system.physmem.perBankRdBursts::11 19 # Per bank write bursts +system.physmem.perBankRdBursts::12 52 # Per bank write bursts +system.physmem.perBankRdBursts::13 28 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24894000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 455 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,48 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2305250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests -system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8195000 # Total cycles spent in bank access -system.physmem.avgQLat 5066.48 # Average queueing delay per request -system.physmem.avgBankLat 18010.99 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28077.47 # Average memory access latency -system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.25 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.52 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 361 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation +system.physmem.totQLat 3167500 # Total ticks spent queuing +system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8112500 # Total ticks spent accessing banks +system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.11 # Data bus utilization in percentage +system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53887.91 # Average gap between requests -system.membus.throughput 1184365722 # Throughput (bytes/s) +system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1165965966 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -202,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -234,14 +240,14 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49175 # number of cpu cycles simulated +system.cpu.numCycles 49951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File @@ -256,12 +262,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.946619 # Percentage of cycles cpu is active +system.cpu.activity 10.776561 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -273,36 +279,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -315,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -333,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +365,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -393,21 +399,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -425,17 +431,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -458,17 +464,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,17 +494,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -510,27 +516,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -547,14 +553,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -571,14 +577,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -603,14 +609,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -619,14 +625,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 423a70e1a..1c2de0612 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21805500 # Number of ticks simulated -final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21898500 # Number of ticks simulated +final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31004 # Simulator instruction rate (inst/s) -host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131093072 # Simulator tick rate (ticks/s) -host_mem_usage 229800 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 64871 # Simulator instruction rate (inst/s) +host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275425114 # Simulator tick rate (ticks/s) +host_mem_usage 255508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30528 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21726000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 477 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 30 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 7 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 13 # Per bank write bursts +system.physmem.perBankRdBursts::7 54 # Per bank write bursts +system.physmem.perBankRdBursts::8 63 # Per bank write bursts +system.physmem.perBankRdBursts::9 77 # Per bank write bursts +system.physmem.perBankRdBursts::10 44 # Per bank write bursts +system.physmem.perBankRdBursts::11 20 # Per bank write bursts +system.physmem.perBankRdBursts::12 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 29 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21819000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 477 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,47 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2353250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests -system.physmem.totBusLat 2385000 # Total cycles spent in databus access -system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 4933.44 # Average queueing delay per request -system.physmem.avgBankLat 18189.20 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28122.64 # Average memory access latency -system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 374 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation +system.physmem.totQLat 2620250 # Total ticks spent queuing +system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8662500 # Total ticks spent accessing banks +system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.89 # Data bus utilization in percentage +system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45547.17 # Average gap between requests -system.membus.throughput 1400013758 # Throughput (bytes/s) +system.physmem.avgGap 45742.14 # Average gap between requests +system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1394068087 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) -system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups +system.cpu.branchPred.BTBHits 492 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -233,94 +240,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43612 # number of cpu cycles simulated +system.cpu.numCycles 43798 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3043 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3026 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2916 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2899 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -356,68 +363,68 @@ system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8306 # Type of FU issued -system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.FU_type_0::total 8293 # Type of FU issued +system.cpu.iq.rate 0.189347 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall @@ -426,43 +433,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1525 # number of nop insts executed -system.cpu.iew.exec_refs 3189 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3186 # number of memory reference insts executed +system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.181716 # Inst execution rate -system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.180648 # Inst execution rate +system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,23 +482,23 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24237 # The number of ROB reads -system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.rob.rob_reads 24172 # The number of ROB reads +system.cpu.rob.rob_writes 22333 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10746 # number of integer regfile reads -system.cpu.int_regfile_writes 5233 # number of integer regfile writes +system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads +system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10743 # number of integer regfile reads +system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -506,55 +513,55 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits -system.cpu.icache.overall_hits::total 1531 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses -system.cpu.icache.overall_misses::total 454 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits +system.cpu.icache.overall_hits::total 1514 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses +system.cpu.icache.overall_misses::total 451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,48 +570,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 47 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -622,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -655,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,17 +692,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -707,27 +714,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits @@ -744,14 +751,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -768,19 +775,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -800,14 +807,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -816,14 +823,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index bf93774ff..800440e86 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18469500 # Number of ticks simulated -final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18905500 # Number of ticks simulated +final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33738 # Simulator instruction rate (inst/s) -host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107564291 # Simulator tick rate (ticks/s) -host_mem_usage 225768 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 83485 # Simulator instruction rate (inst/s) +host_op_rate 83467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272386071 # Simulator tick rate (ticks/s) +host_mem_usage 250488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28544 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18341000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::1 42 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::4 53 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 13 # Per bank write bursts +system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 4 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 18777000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 1996500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests -system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 4476.46 # Average queueing delay per request -system.physmem.avgBankLat 15168.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24644.62 # Average memory access latency -system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.07 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3018500 # Total ticks spent queuing +system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6710000 # Total ticks spent accessing banks +system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 368 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41123.32 # Average gap between requests -system.membus.throughput 1545466851 # Throughput (bytes/s) +system.physmem.avgGap 42100.90 # Average gap between requests +system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1509825183 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -202,10 +211,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -234,10 +243,10 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36940 # number of cpu cycles simulated +system.cpu.numCycles 37812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken @@ -245,27 +254,27 @@ system.cpu.fetch.Cycles 2263 # Nu system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2098 # Number of cycles decode is running system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking @@ -275,7 +284,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1987 # Number of cycles rename is running @@ -298,66 +307,66 @@ system.cpu.memDep0.conflictingLoads 52 # Nu system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued @@ -384,21 +393,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.241012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8904 # Type of FU issued +system.cpu.iq.rate 0.235481 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -425,43 +434,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed -system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.230157 # Inst execution rate -system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4221 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_stores 1524 # Number of stores executed +system.cpu.iew.exec_rate 0.224876 # Inst execution rate +system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4220 # num instructions producing a value +system.cpu.iew.wb_consumers 6682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,22 +483,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_reads 21334 # The number of ROB reads system.cpu.rob.rob_writes 21446 # The number of ROB writes system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13476 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -504,19 +513,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -529,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 442 # n system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses @@ -547,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -573,36 +582,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -623,17 +632,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -656,17 +665,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,17 +695,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -708,51 +717,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits -system.cpu.dcache.overall_hits::total 2192 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses -system.cpu.dcache.overall_misses::total 431 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -763,20 +772,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -787,12 +796,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -801,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -817,14 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 68c96c714..b34a38ab7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20802500 # Number of ticks simulated -final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20892500 # Number of ticks simulated +final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86492 # Simulator instruction rate (inst/s) -host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337526822 # Simulator tick rate (ticks/s) -host_mem_usage 231936 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 70791 # Simulator instruction rate (inst/s) +host_op_rate 70777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277537926 # Simulator tick rate (ticks/s) +host_mem_usage 260788 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27072 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20733000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24 # Per bank write bursts +system.physmem.perBankRdBursts::1 7 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 78 # Per bank write bursts +system.physmem.perBankRdBursts::6 80 # Per bank write bursts +system.physmem.perBankRdBursts::7 62 # Per bank write bursts +system.physmem.perBankRdBursts::8 35 # Per bank write bursts +system.physmem.perBankRdBursts::9 18 # Per bank write bursts +system.physmem.perBankRdBursts::10 10 # Per bank write bursts +system.physmem.perBankRdBursts::11 52 # Per bank write bursts +system.physmem.perBankRdBursts::12 12 # Per bank write bursts +system.physmem.perBankRdBursts::13 21 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 20823000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 423 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,48 +152,53 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 2859500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests -system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6490000 # Total cycles spent in bank access -system.physmem.avgQLat 6760.05 # Average queueing delay per request -system.physmem.avgBankLat 15342.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27102.84 # Average memory access latency -system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.55 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation +system.physmem.totQLat 3229250 # Total ticks spent queuing +system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6490000 # Total ticks spent accessing banks +system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.12 # Data bus utilization in percentage +system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 343 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49014.18 # Average gap between requests -system.membus.throughput 1301382045 # Throughput (bytes/s) +system.physmem.avgGap 49226.95 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1295775996 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -204,8 +211,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -216,7 +223,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41606 # number of cpu cycles simulated +system.cpu.numCycles 41786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -238,12 +245,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 15.009854 # Percentage of cycles cpu is active +system.cpu.activity 14.945197 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -255,36 +262,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -297,12 +304,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -315,12 +322,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +348,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -375,21 +382,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -410,17 +417,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -443,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +480,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -495,27 +502,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -532,14 +539,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -556,14 +563,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -588,14 +595,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -604,14 +611,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 45776fad9..b42a03bbb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19639500 # Number of ticks simulated -final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19970500 # Number of ticks simulated +final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27608 # Simulator instruction rate (inst/s) -host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100764572 # Simulator tick rate (ticks/s) -host_mem_usage 247304 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37809 # Simulator instruction rate (inst/s) +host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140319695 # Simulator tick rate (ticks/s) +host_mem_usage 243588 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 26624 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19591000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 417 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 414 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::10 63 # Per bank write bursts +system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::12 2 # Per bank write bursts +system.physmem.perBankRdBursts::13 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 17 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 19922000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,300 +152,305 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation -system.physmem.totQLat 1395750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests -system.physmem.totBusLat 2085000 # Total cycles spent in databus access -system.physmem.totBankLat 7645000 # Total cycles spent in bank access -system.physmem.avgQLat 3347.12 # Average queueing delay per request -system.physmem.avgBankLat 18333.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26680.46 # Average memory access latency -system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 329 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2039250 # Total ticks spent queuing +system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7617500 # Total ticks spent accessing banks +system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 312 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46980.82 # Average gap between requests -system.membus.throughput 1355635327 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution +system.physmem.avgGap 48004.82 # Average gap between requests +system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1326756967 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 338 # Transaction distribution +system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu.branchPred.lookups 3060 # Number of BP lookups -system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 719 # Number of BTB hits +system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu.branchPred.lookups 3084 # Number of BP lookups +system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39280 # number of cpu cycles simulated +system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17094 # Type of FU issued -system.cpu.iq.rate 0.435183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17027 # Type of FU issued +system.cpu.iq.rate 0.426293 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3125 # number of memory reference insts executed -system.cpu.iew.exec_branches 1615 # Number of branches executed -system.cpu.iew.exec_stores 1277 # Number of stores executed -system.cpu.iew.exec_rate 0.411965 # Inst execution rate -system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10139 # num instructions producing a value -system.cpu.iew.wb_consumers 15623 # num instructions consuming a value +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1623 # Number of branches executed +system.cpu.iew.exec_stores 1273 # Number of stores executed +system.cpu.iew.exec_rate 0.403685 # Inst execution rate +system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10128 # num instructions producing a value +system.cpu.iew.wb_consumers 15579 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +463,138 @@ system.cpu.commit.int_insts 9653 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40219 # The number of ROB reads -system.cpu.rob.rob_writes 42582 # The number of ROB writes -system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40049 # The number of ROB reads +system.cpu.rob.rob_writes 42426 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20780 # number of integer regfile reads -system.cpu.int_regfile_writes 12385 # number of integer regfile writes +system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20727 # number of integer regfile reads +system.cpu.int_regfile_writes 12358 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8044 # number of cc regfile reads -system.cpu.cc_regfile_writes 4852 # number of cc regfile writes -system.cpu.misc_regfile_reads 7122 # number of misc regfile reads +system.cpu.cc_regfile_reads 8004 # number of cc regfile reads +system.cpu.cc_regfile_writes 4850 # number of cc regfile writes +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution +system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits -system.cpu.icache.overall_hits::total 1608 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,113 +667,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +783,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 12317fca2..15c806f18 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24404000 # Number of ticks simulated -final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24229500 # Number of ticks simulated +final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12749 # Simulator instruction rate (inst/s) -host_op_rate 12749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24410850 # Simulator tick rate (ticks/s) -host_mem_usage 229776 # Number of bytes of host memory used -host_seconds 1.00 # Real time elapsed on the host +host_inst_rate 81251 # Simulator instruction rate (inst/s) +host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154440285 # Simulator tick rate (ticks/s) +host_mem_usage 227736 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1636453040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 917882314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2554335355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 62336 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 87 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24245500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 974 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 82 # Per bank write bursts +system.physmem.perBankRdBursts::1 153 # Per bank write bursts +system.physmem.perBankRdBursts::2 77 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 87 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 49 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts +system.physmem.perBankRdBursts::10 30 # Per bank write bursts +system.physmem.perBankRdBursts::11 33 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 121 # Per bank write bursts +system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24081000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,101 +152,101 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.957672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.277128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 472.297416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 80 42.33% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 30 15.87% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 19 10.05% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20 10.58% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 1.59% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 2.65% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.12% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 1.59% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 6 3.17% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.53% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 0.53% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 0.53% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 1.06% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 0.53% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 1.06% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 0.53% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1 0.53% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 0.53% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 1 0.53% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 1.06% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.53% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 1 0.53% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 1 0.53% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 189 # Bytes accessed per row activation -system.physmem.totQLat 8948500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 30593500 # Sum of mem lat for all requests -system.physmem.totBusLat 4870000 # Total cycles spent in databus access -system.physmem.totBankLat 16775000 # Total cycles spent in bank access -system.physmem.avgQLat 9187.37 # Average queueing delay per request -system.physmem.avgBankLat 17222.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.16 # Average memory access latency -system.physmem.avgRdBW 2554.34 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2554.34 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.25 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 785 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation +system.physmem.totQLat 9442250 # Total ticks spent queuing +system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.totBankLat 16940000 # Total ticks spent accessing banks +system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 20.12 # Data bus utilization in percentage +system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 758 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 24892.71 # Average gap between requests -system.membus.throughput 2554335355 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 828 # Transaction distribution -system.membus.trans_dist::ReadResp 828 # Transaction distribution +system.physmem.avgGap 24698.46 # Average gap between requests +system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2575372996 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 829 # Transaction distribution +system.membus.trans_dist::ReadResp 829 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62336 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 9049000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 37.1 # Layer utilization (%) -system.cpu.branchPred.lookups 6717 # Number of BP lookups -system.cpu.branchPred.condPredicted 3814 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4787 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 37.4 # Layer utilization (%) +system.cpu.branchPred.lookups 6676 # Number of BP lookups +system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups +system.cpu.branchPred.BTBHits 873 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.257781 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4630 # DTB read hits -system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.read_hits 4588 # DTB read hits +system.cpu.dtb.read_misses 111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4739 # DTB read accesses -system.cpu.dtb.write_hits 2007 # DTB write hits -system.cpu.dtb.write_misses 95 # DTB write misses +system.cpu.dtb.read_accesses 4699 # DTB read accesses +system.cpu.dtb.write_hits 2013 # DTB write hits +system.cpu.dtb.write_misses 87 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2102 # DTB write accesses -system.cpu.dtb.data_hits 6637 # DTB hits -system.cpu.dtb.data_misses 204 # DTB misses +system.cpu.dtb.write_accesses 2100 # DTB write accesses +system.cpu.dtb.data_hits 6601 # DTB hits +system.cpu.dtb.data_misses 198 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6841 # DTB accesses -system.cpu.itb.fetch_hits 5430 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 6799 # DTB accesses +system.cpu.itb.fetch_hits 5373 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5485 # ITB accesses +system.cpu.itb.fetch_accesses 5430 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -259,316 +261,316 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48809 # number of cpu cycles simulated +system.cpu.numCycles 48460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1620 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37306 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1770 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 908 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.300949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.721933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22422 78.19% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 547 1.91% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 376 1.31% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 432 1.51% 82.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 434 1.51% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 433 1.51% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 459 1.60% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 528 1.84% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3045 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137618 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.764326 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2766 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 575 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32748 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 724 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2766 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40726 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5410 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 972 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5017 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37071 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5023 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.760078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341515 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19237 67.08% 67.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3397 11.85% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2648 9.23% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1591 5.55% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1050 3.66% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 477 1.66% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 210 0.73% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.15% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 102 58.29% 62.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 37.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7221 65.66% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2635 23.96% 89.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1137 10.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10998 # Type of FU issued +system.cpu.iq.FU_type_0::total 10800 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7106 65.81% 65.83% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2582 23.91% 89.77% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10798 # Type of FU issued -system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.446557 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 175 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004083 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003946 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008029 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72523 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18760 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 10826 # Type of FU issued +system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.446265 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21945 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1840 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1820 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 537 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2766 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26762 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 628 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6026 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2758 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 225 # Number of branches that were predicted taken incorrectly +system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20286 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2395 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2362 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1510 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 112 # number of nop insts executed -system.cpu.iew.exec_nop::1 87 # number of nop insts executed +system.cpu.iew.exec_nop::0 109 # number of nop insts executed +system.cpu.iew.exec_nop::1 90 # number of nop insts executed system.cpu.iew.exec_nop::total 199 # number of nop insts executed -system.cpu.iew.exec_refs::0 3467 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3404 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6871 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1580 # Number of branches executed -system.cpu.iew.exec_branches::1 1582 # Number of branches executed -system.cpu.iew.exec_branches::total 3162 # Number of branches executed -system.cpu.iew.exec_stores::0 1072 # Number of stores executed -system.cpu.iew.exec_stores::1 1042 # Number of stores executed +system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1584 # Number of branches executed +system.cpu.iew.exec_branches::1 1595 # Number of branches executed +system.cpu.iew.exec_branches::total 3179 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1048 # Number of stores executed system.cpu.iew.exec_stores::total 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.415620 # Inst execution rate -system.cpu.iew.wb_sent::0 9597 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9491 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19088 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9418 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9362 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18780 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4881 # num instructions producing a value -system.cpu.iew.wb_producers::1 4800 # num instructions producing a value -system.cpu.iew.wb_producers::total 9681 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6383 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6247 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12630 # num instructions consuming a value +system.cpu.iew.exec_rate 0.416096 # Inst execution rate +system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4798 # num instructions producing a value +system.cpu.iew.wb_producers::1 4829 # num instructions producing a value +system.cpu.iew.wb_producers::total 9627 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.192956 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.191809 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.384765 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764687 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768369 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766508 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13991 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.446662 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.213615 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22891 80.01% 80.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3017 10.55% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1097 3.83% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 546 1.91% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 330 1.15% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 253 0.88% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.70% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.21% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 214 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 341 1.16% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 269 0.91% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 187 0.63% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.22% 99.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -599,102 +601,102 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131690 # The number of ROB reads -system.cpu.rob.rob_writes 56322 # The number of ROB writes -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132694 # The number of ROB reads +system.cpu.rob.rob_writes 55968 # The number of ROB writes +system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.658716 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.659918 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.829659 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.130570 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.130550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.261120 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25473 # number of integer regfile reads -system.cpu.int_regfile_writes 14213 # number of integer regfile writes +system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25291 # number of integer regfile reads +system.cpu.int_regfile_writes 14128 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2559580397 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution +system.cpu.toL2Bus.throughput 2580655812 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 562500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.icache.tags.replacements::0 6 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4375 # number of overall hits -system.cpu.icache.overall_hits::total 4375 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits +system.cpu.icache.overall_hits::total 4319 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses system.cpu.icache.overall_misses::total 1049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69677745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69677745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69677745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69677745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5424 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5424 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5424 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5424 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193400 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193400 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193400 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193400 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66423.017159 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66423.017159 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2785 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69934495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69934495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2561 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.859649 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.155172 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74276.442308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80364.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76464.065708 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507 # 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mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61815.705128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67138.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63127.113527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 214.018929 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4470 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.735043 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4493 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4493 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4493 # number of overall hits -system.cpu.dcache.overall_hits::total 4493 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1030 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1030 # number of overall misses -system.cpu.dcache.overall_misses::total 1030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22955250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22955250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48876949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48876949 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 71832199 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 71832199 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4470 # number of overall hits +system.cpu.dcache.overall_hits::total 4470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1037 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1037 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1037 # number of overall misses +system.cpu.dcache.overall_misses::total 1037 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23849750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23849750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50904202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50904202 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74753952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74753952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3777 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3777 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.186493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.186493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.186493 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.186493 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70849.537037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70849.537037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69230.805949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69230.805949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4722 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188306 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188306 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188306 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188306 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4541 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.358974 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.483051 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 686 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 686 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053783 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053783 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054276 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054276 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 0c812fe4f..9f174a09c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27282000 # Number of ticks simulated -final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27705000 # Number of ticks simulated +final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96636 # Simulator instruction rate (inst/s) -host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173854426 # Simulator tick rate (ticks/s) -host_mem_usage 231852 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 72386 # Simulator instruction rate (inst/s) +host_op_rate 72381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132251643 # Simulator tick rate (ticks/s) +host_mem_usage 260736 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27904 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27248500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 436 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts +system.physmem.perBankRdBursts::2 38 # Per bank write bursts +system.physmem.perBankRdBursts::3 20 # Per bank write bursts +system.physmem.perBankRdBursts::4 16 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 29 # Per bank write bursts +system.physmem.perBankRdBursts::7 32 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 58 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 27671500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 436 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1525500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests -system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6325000 # Total cycles spent in bank access -system.physmem.avgQLat 3498.85 # Average queueing delay per request -system.physmem.avgBankLat 14506.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23005.73 # Average memory access latency -system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.37 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 387 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation +system.physmem.totQLat 2393750 # Total ticks spent queuing +system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6256250 # Total ticks spent accessing banks +system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.87 # Data bus utilization in percentage +system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 372 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62496.56 # Average gap between requests -system.membus.throughput 1020453046 # Throughput (bytes/s) +system.physmem.avgGap 63466.74 # Average gap between requests +system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1004872767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -204,8 +213,8 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -216,7 +225,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54565 # number of cpu cycles simulated +system.cpu.numCycles 55411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -238,12 +247,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.196463 # Percentage of cycles cpu is active +system.cpu.activity 31.704896 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -255,36 +264,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads -system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -297,12 +306,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -315,12 +324,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +350,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -375,21 +384,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -407,17 +416,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -440,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,17 +479,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -492,27 +501,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -531,14 +540,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -557,14 +566,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -589,14 +598,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -605,14 +614,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 6e72806cb..dcf709c59 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26524500 # Number of ticks simulated -final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26616500 # Number of ticks simulated +final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19767 # Simulator instruction rate (inst/s) -host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36317578 # Simulator tick rate (ticks/s) -host_mem_usage 236084 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host +host_inst_rate 75478 # Simulator instruction rate (inst/s) +host_op_rate 75473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139143595 # Simulator tick rate (ticks/s) +host_mem_usage 260732 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30848 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26363500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 482 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 482 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 102 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 50 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 35 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 57 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 61 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26455500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 482 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,47 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1755500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests -system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 3642.12 # Average queueing delay per request -system.physmem.avgBankLat 14035.27 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22677.39 # Average memory access latency -system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 430 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation +system.physmem.totQLat 2423000 # Total ticks spent queuing +system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6778750 # Total ticks spent accessing banks +system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.05 # Data bus utilization in percentage +system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 413 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54696.06 # Average gap between requests -system.membus.throughput 1163000245 # Throughput (bytes/s) +system.physmem.avgGap 54886.93 # Average gap between requests +system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1158980332 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -201,63 +211,63 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6716 # Number of BP lookups -system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.cpu.branchPred.lookups 6713 # Number of BP lookups +system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53050 # number of cpu cycles simulated +system.cpu.numCycles 53234 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8343 # Number of cycles decode is running system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename @@ -282,15 +292,15 @@ system.cpu.iq.iqSquashedInstsIssued 97 # Nu system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle @@ -298,7 +308,7 @@ system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -368,10 +378,10 @@ system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 21122 # Type of FU issued -system.cpu.iq.rate 0.398153 # Inst issue rate +system.cpu.iq.rate 0.396776 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads @@ -412,35 +422,35 @@ system.cpu.iew.exec_nop 1134 # nu system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.exec_rate 0.377090 # Inst execution rate system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19522 # cumulative count of insts written-back system.cpu.iew.wb_producers 9120 # num instructions producing a value system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -453,22 +463,22 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_reads 54530 # The number of ROB reads system.cpu.rob.rob_writes 50298 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -483,55 +493,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits -system.cpu.icache.overall_hits::total 4873 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits +system.cpu.icache.overall_hits::total 4872 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,36 +562,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337 system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -599,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -632,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,17 +672,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -684,27 +694,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -723,14 +733,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -749,14 +759,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked @@ -781,14 +791,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -797,14 +807,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1df87c21b..b78a3e4ce 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110804500 # Number of ticks simulated -final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 111025500 # Number of ticks simulated +final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91896 # Simulator instruction rate (inst/s) -host_op_rate 91896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9765210 # Simulator tick rate (ticks/s) -host_mem_usage 250112 # Number of bytes of host memory used -host_seconds 11.35 # Real time elapsed on the host -sim_insts 1042724 # Number of instructions simulated -sim_ops 1042724 # Number of ops (including micro ops) simulated +host_inst_rate 119782 # Simulator instruction rate (inst/s) +host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12747983 # Simulator tick rate (ticks/s) +host_mem_usage 275656 # Number of bytes of host memory used +host_seconds 8.71 # Real time elapsed on the host +sim_insts 1043212 # Number of instructions simulated +sim_ops 1043212 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -34,92 +34,94 @@ system.physmem.num_reads::cpu2.data 20 # Nu system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 42176 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110776500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 660 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 660 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts +system.physmem.perBankRdBursts::1 39 # Per bank write bursts +system.physmem.perBankRdBursts::2 29 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts +system.physmem.perBankRdBursts::6 18 # Per bank write bursts +system.physmem.perBankRdBursts::7 24 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 12 # Per bank write bursts +system.physmem.perBankRdBursts::12 60 # Per bank write bursts +system.physmem.perBankRdBursts::13 38 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 98 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 110997500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 660 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -180,100 +182,104 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3818750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests -system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11000000 # Total cycles spent in bank access -system.physmem.avgQLat 5785.98 # Average queueing delay per request -system.physmem.avgBankLat 16666.67 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27452.65 # Average memory access latency -system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation +system.physmem.totQLat 4010250 # Total ticks spent queuing +system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers +system.physmem.totBankLat 10848750 # Total ticks spent accessing banks +system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 532 # Number of row buffer hits during reads +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 509 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167843.18 # Average gap between requests -system.membus.throughput 380634361 # Throughput (bytes/s) +system.physmem.avgGap 168178.03 # Average gap between requests +system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 379876695 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeReq 289 # Transaction distribution system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 164 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use +system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits @@ -284,18 +290,18 @@ system.l2c.demand_hits::cpu1.inst 412 # nu system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits +system.l2c.demand_hits::total 1442 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 412 # number of overall hits system.l2c.overall_hits::cpu1.data 11 # number of overall hits system.l2c.overall_hits::cpu2.inst 349 # number of overall hits system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 421 # number of overall hits +system.l2c.overall_hits::cpu3.inst 420 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits +system.l2c.overall_hits::total 1442 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses @@ -305,10 +311,10 @@ system.l2c.ReadReq_misses::cpu2.data 7 # nu system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 543 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses @@ -333,53 +339,53 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37776250 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) @@ -392,28 +398,28 @@ system.l2c.demand_accesses::cpu1.inst 428 # nu system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 430 # 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miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses @@ -429,50 +435,50 @@ system.l2c.demand_miss_rate::cpu1.inst 0.037383 # mi system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.020979 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # 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mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses @@ -595,410 +601,411 @@ system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution +system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135424 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 82992 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits +system.cpu0.branchPred.lookups 83087 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221610 # number of cpu cycles simulated +system.cpu0.numCycles 222052 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733333 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued -system.cpu0.iq.rate 1.824931 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued +system.cpu0.iq.rate 1.824118 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76515 # number of nop insts executed -system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80132 # Number of branches executed -system.cpu0.iew.exec_stores 78029 # Number of stores executed -system.cpu0.iew.exec_rate 1.820098 # Inst execution rate -system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238549 # num instructions producing a value -system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value +system.cpu0.iew.exec_nop 76577 # number of nop insts executed +system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80250 # Number of branches executed +system.cpu0.iew.exec_stores 78134 # Number of stores executed +system.cpu0.iew.exec_rate 1.819295 # Inst execution rate +system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238895 # num instructions producing a value +system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472284 # Number of instructions committed -system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472968 # Number of instructions committed +system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230857 # Number of memory references committed -system.cpu0.commit.loads 153567 # Number of loads committed +system.cpu0.commit.refs 231199 # Number of memory references committed +system.cpu0.commit.loads 153795 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79177 # Number of branches committed +system.cpu0.commit.branches 79291 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677374 # The number of ROB reads -system.cpu0.rob.rob_writes 971507 # The number of ROB writes -system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396291 # Number of Instructions Simulated -system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated -system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 721592 # number of integer regfile reads -system.cpu0.int_regfile_writes 325227 # number of integer regfile writes +system.cpu0.rob.rob_reads 678234 # The number of ROB reads +system.cpu0.rob.rob_writes 972657 # The number of ROB writes +system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396861 # Number of Instructions Simulated +system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated +system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 722661 # number of integer regfile reads +system.cpu0.int_regfile_writes 325773 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads +system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits -system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits +system.cpu0.icache.overall_hits::total 5113 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1019,94 +1026,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits -system.cpu0.dcache.overall_hits::total 155698 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits +system.cpu0.dcache.overall_hits::total 155902 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses -system.cpu0.dcache.overall_misses::total 955 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses +system.cpu0.dcache.overall_misses::total 965 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -1117,365 +1124,365 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 43495 # Number of BP lookups -system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits +system.cpu1.branchPred.lookups 47485 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177681 # number of cpu cycles simulated +system.cpu1.numCycles 177933 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 330316 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued -system.cpu1.iq.rate 1.067177 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued +system.cpu1.iq.rate 1.191033 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 30958 # number of nop insts executed -system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed -system.cpu1.iew.exec_branches 40129 # Number of branches executed -system.cpu1.iew.exec_stores 26101 # Number of stores executed -system.cpu1.iew.exec_rate 1.060603 # Inst execution rate -system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 102456 # num instructions producing a value -system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value +system.cpu1.iew.exec_nop 34927 # number of nop insts executed +system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44131 # Number of branches executed +system.cpu1.iew.exec_stores 31196 # Number of stores executed +system.cpu1.iew.exec_rate 1.184317 # Inst execution rate +system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 116723 # num instructions producing a value +system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 212432 # Number of instructions committed -system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 238705 # Number of instructions committed +system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 83673 # Number of memory references committed -system.cpu1.commit.loads 58239 # Number of loads committed -system.cpu1.commit.membars 7917 # Number of memory barriers committed -system.cpu1.commit.branches 39308 # Number of branches committed +system.cpu1.commit.refs 97880 # Number of memory references committed +system.cpu1.commit.loads 67361 # Number of loads committed +system.cpu1.commit.membars 6845 # Number of memory barriers committed +system.cpu1.commit.branches 43327 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. +system.cpu1.commit.int_insts 163326 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 388816 # The number of ROB reads -system.cpu1.rob.rob_writes 452512 # The number of ROB writes -system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 174425 # Number of Instructions Simulated -system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated -system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 315718 # number of integer regfile reads -system.cpu1.int_regfile_writes 148477 # number of integer regfile writes +system.cpu1.rob.rob_reads 415361 # The number of ROB reads +system.cpu1.rob.rob_writes 504754 # The number of ROB writes +system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 197745 # Number of Instructions Simulated +system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated +system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 358439 # number of integer regfile reads +system.cpu1.int_regfile_writes 167816 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads +system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits -system.cpu1.icache.overall_hits::total 25178 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses -system.cpu1.icache.overall_misses::total 478 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits +system.cpu1.icache.overall_hits::total 22903 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses +system.cpu1.icache.overall_misses::total 476 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1484,106 +1491,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits -system.cpu1.dcache.overall_hits::total 62948 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses -system.cpu1.dcache.overall_misses::total 451 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits +system.cpu1.dcache.overall_hits::total 72046 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses +system.cpu1.dcache.overall_misses::total 491 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1592,365 +1599,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51236 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu2.branchPred.lookups 51290 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177316 # number of cpu cycles simulated +system.cpu2.numCycles 177568 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418050 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename +system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued -system.cpu2.iq.rate 1.322842 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued +system.cpu2.iq.rate 1.322924 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38706 # number of nop insts executed -system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47927 # Number of branches executed -system.cpu2.iew.exec_stores 36792 # Number of stores executed -system.cpu2.iew.exec_rate 1.316311 # Inst execution rate -system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131730 # num instructions producing a value -system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value +system.cpu2.iew.exec_nop 38771 # number of nop insts executed +system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed +system.cpu2.iew.exec_branches 48001 # Number of branches executed +system.cpu2.iew.exec_stores 36873 # Number of stores executed +system.cpu2.iew.exec_rate 1.316482 # Inst execution rate +system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131942 # num instructions producing a value +system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 264916 # Number of instructions committed -system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 265352 # Number of instructions committed +system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 112806 # Number of memory references committed -system.cpu2.commit.loads 76707 # Number of loads committed -system.cpu2.commit.membars 5024 # Number of memory barriers committed -system.cpu2.commit.branches 47088 # Number of branches committed +system.cpu2.commit.refs 113027 # Number of memory references committed +system.cpu2.commit.loads 76852 # Number of loads committed +system.cpu2.commit.membars 5022 # Number of memory barriers committed +system.cpu2.commit.branches 47160 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182307 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 437936 # The number of ROB reads -system.cpu2.rob.rob_writes 557643 # The number of ROB writes -system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 222015 # Number of Instructions Simulated -system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated -system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 403571 # number of integer regfile reads -system.cpu2.int_regfile_writes 188531 # number of integer regfile writes +system.cpu2.rob.rob_reads 438409 # The number of ROB reads +system.cpu2.rob.rob_writes 558438 # The number of ROB writes +system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222382 # Number of Instructions Simulated +system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated +system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 404230 # number of integer regfile reads +system.cpu2.int_regfile_writes 188808 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits -system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits +system.cpu2.icache.overall_hits::total 19259 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1971,94 +1977,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # 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average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1507.392857 # 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number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # 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number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 56317 # Number of BP lookups -system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits +system.cpu3.branchPred.lookups 52302 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176970 # number of cpu cycles simulated +system.cpu3.numCycles 177222 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 468076 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued -system.cpu3.iq.rate 1.478471 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued +system.cpu3.iq.rate 1.348602 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43769 # number of nop insts executed -system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed -system.cpu3.iew.exec_branches 53091 # Number of branches executed -system.cpu3.iew.exec_stores 42613 # Number of stores executed -system.cpu3.iew.exec_rate 1.471764 # Inst execution rate -system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 148532 # num instructions producing a value -system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value +system.cpu3.iew.exec_nop 39788 # number of nop insts executed +system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49028 # Number of branches executed +system.cpu3.iew.exec_stores 37424 # Number of stores executed +system.cpu3.iew.exec_rate 1.342091 # Inst execution rate +system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134044 # num instructions producing a value +system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 297438 # Number of instructions committed -system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 270725 # Number of instructions committed +system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 129728 # Number of memory references committed -system.cpu3.commit.loads 87775 # Number of loads committed -system.cpu3.commit.membars 4366 # Number of memory barriers committed -system.cpu3.commit.branches 52284 # Number of branches committed +system.cpu3.commit.refs 115239 # Number of memory references committed +system.cpu3.commit.loads 78487 # Number of loads committed +system.cpu3.commit.membars 5499 # Number of memory barriers committed +system.cpu3.commit.branches 48212 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. +system.cpu3.commit.int_insts 185574 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 473500 # The number of ROB reads -system.cpu3.rob.rob_writes 621006 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249993 # Number of Instructions Simulated -system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated -system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 453881 # number of integer regfile reads -system.cpu3.int_regfile_writes 211087 # number of integer regfile writes +system.cpu3.rob.rob_reads 447315 # The number of ROB reads +system.cpu3.rob.rob_writes 568397 # The number of ROB writes +system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 226224 # Number of Instructions Simulated +system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated +system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 410473 # number of integer regfile reads +system.cpu3.int_regfile_writes 191401 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads +system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits -system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits +system.cpu3.icache.overall_hits::total 20090 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2434,106 +2440,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits -system.cpu3.dcache.overall_hits::total 92475 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses -system.cpu3.dcache.overall_misses::total 484 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits +system.cpu3.dcache.overall_hits::total 83209 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 333 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses +system.cpu3.dcache.overall_misses::total 464 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2542,54 +2548,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt index 4e4b75a44..9c1ab67e5 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 12102739985 # Simulator tick rate (ticks/s) -host_mem_usage 228608 # Number of bytes of host memory used -host_seconds 8.26 # Real time elapsed on the host +host_tick_rate 20181472495 # Simulator tick rate (ticks/s) +host_mem_usage 192916 # Number of bytes of host memory used +host_seconds 4.96 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -15,77 +15,79 @@ system.physmem.bw_read::cpu 2133311360 # To system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 213331136 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.readReqs 3333300 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 217600 # Per bank write bursts +system.physmem.perBankRdBursts::1 217600 # Per bank write bursts +system.physmem.perBankRdBursts::2 217600 # Per bank write bursts +system.physmem.perBankRdBursts::3 217600 # Per bank write bursts +system.physmem.perBankRdBursts::4 210100 # Per bank write bursts +system.physmem.perBankRdBursts::5 204800 # Per bank write bursts +system.physmem.perBankRdBursts::6 204800 # Per bank write bursts +system.physmem.perBankRdBursts::7 204800 # Per bank write bursts +system.physmem.perBankRdBursts::8 204800 # Per bank write bursts +system.physmem.perBankRdBursts::9 204800 # Per bank write bursts +system.physmem.perBankRdBursts::10 204800 # Per bank write bursts +system.physmem.perBankRdBursts::11 204800 # Per bank write bursts +system.physmem.perBankRdBursts::12 204800 # Per bank write bursts +system.physmem.perBankRdBursts::13 204800 # Per bank write bursts +system.physmem.perBankRdBursts::14 204800 # Per bank write bursts +system.physmem.perBankRdBursts::15 204800 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999960000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3333300 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3333300 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -138,35 +140,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation -system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests -system.physmem.totBusLat 16666500000 # Total cycles spent in databus access -system.physmem.totBankLat 45939671250 # Total cycles spent in bank access -system.physmem.avgQLat 383.63 # Average queueing delay per request -system.physmem.avgBankLat 13782.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19165.67 # Average memory access latency -system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation +system.physmem.totQLat 27766345550 # Total ticks spent queuing +system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks +system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.64 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3307200 # Number of row buffer hits during reads +system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3294382 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 30000.29 # Average gap between requests +system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution @@ -177,7 +279,7 @@ system.membus.tot_pkt_size::total 213331136 # Cu system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks) system.membus.respLayer0.utilization 17.2 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -231,8 +333,8 @@ system.monitor.writeBurstLengthHist::19 0 # Hi system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -284,20 +386,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333299 # Read request-response latency -system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency -system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency -system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency -system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency +system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency +system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency +system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency @@ -418,17 +520,17 @@ system.monitor.ittReqReq::min_value 30000 # Re system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions +system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions |