diff options
Diffstat (limited to 'tests/quick/se')
40 files changed, 11052 insertions, 9799 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index a38dae954..35c6d79b2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19476000 # Number of ticks simulated -final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24560000 # Number of ticks simulated +final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1322 # Simulator instruction rate (inst/s) -host_op_rate 1322 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4028719 # Simulator tick rate (ticks/s) -host_mem_usage 223696 # Number of bytes of host memory used -host_seconds 4.83 # Real time elapsed on the host +host_inst_rate 1785 # Simulator instruction rate (inst/s) +host_op_rate 1785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6860090 # Simulator tick rate (ticks/s) +host_mem_usage 225432 # Number of bytes of host memory used +host_seconds 3.58 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29952 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19461500 # Total gap between requests +system.physmem.totGap 24545500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2627750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation +system.physmem.totQLat 1607750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 8401250 # Total cycles spent in bank access -system.physmem.avgQLat 5602.88 # Average queueing delay per request -system.physmem.avgBankLat 17913.11 # Average bank access latency per request +system.physmem.totBankLat 7576250 # Total cycles spent in bank access +system.physmem.avgQLat 3428.04 # Average queueing delay per request +system.physmem.avgBankLat 16154.05 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28515.99 # Average memory access latency -system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24582.09 # Average memory access latency +system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.69 # Average read queue length over time +system.physmem.busUtil 9.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 377 # Number of row buffer hits during reads +system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41495.74 # Average gap between requests +system.physmem.avgGap 52335.82 # Average gap between requests +system.membus.throughput 1219543974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 396 # Transaction distribution +system.membus.trans_dist::ReadResp 395 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 937 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 29952 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.8 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -183,18 +218,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1184 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 866 # DTB write hits +system.cpu.dtb.read_accesses 1191 # DTB read accesses +system.cpu.dtb.write_hits 893 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 869 # DTB write accesses -system.cpu.dtb.data_hits 2049 # DTB hits +system.cpu.dtb.write_accesses 896 # DTB write accesses +system.cpu.dtb.data_hits 2077 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2059 # DTB accesses +system.cpu.dtb.data_accesses 2087 # DTB accesses system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -212,18 +247,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 38953 # number of cpu cycles simulated +system.cpu.numCycles 49121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2152 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). @@ -234,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. -system.cpu.activity 18.933073 # Percentage of cycles cpu is active +system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. +system.cpu.activity 15.015981 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -251,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads -system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads +system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use system.cpu.icache.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -293,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -311,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -337,36 +372,55 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -384,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24447000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27076500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4877500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4877500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11810000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31954000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20144000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11810000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -417,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -469,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -506,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -530,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -562,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -578,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1a9d50ed7..9e4861fce 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16032500 # Number of ticks simulated -final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20632000 # Number of ticks simulated +final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34765 # Simulator instruction rate (inst/s) -host_op_rate 34761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87452252 # Simulator tick rate (ticks/s) -host_mem_usage 269696 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 1782 # Simulator instruction rate (inst/s) +host_op_rate 1782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5769044 # Simulator tick rate (ticks/s) +host_mem_usage 227476 # Number of bytes of host memory used +host_seconds 3.58 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.num_reads::total 487 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31168 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15819000 # Total gap between requests +system.physmem.totGap 20599000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::6 488 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,90 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2907500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests -system.physmem.totBusLat 2430000 # Total cycles spent in databus access -system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 5982.51 # Average queueing delay per request -system.physmem.avgBankLat 17088.48 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation +system.physmem.totQLat 2633750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests +system.physmem.totBusLat 2440000 # Total cycles spent in databus access +system.physmem.totBankLat 7562500 # Total cycles spent in bank access +system.physmem.avgQLat 5397.03 # Average queueing delay per request +system.physmem.avgBankLat 15496.93 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28070.99 # Average memory access latency -system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25893.95 # Average memory access latency +system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.85 # Average read queue length over time +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.61 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 396 # Number of row buffer hits during reads +system.physmem.readRowHits 419 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32549.38 # Average gap between requests -system.cpu.branchPred.lookups 2896 # Number of BP lookups -system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups -system.cpu.branchPred.BTBHits 746 # Number of BTB hits +system.physmem.avgGap 42211.07 # Average gap between requests +system.membus.throughput 1510663048 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 975 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 31168 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.cpu.branchPred.lookups 2906 # Number of BP lookups +system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups +system.cpu.branchPred.BTBHits 759 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2071 # DTB read hits -system.cpu.dtb.read_misses 50 # DTB read misses +system.cpu.dtb.read_hits 2097 # DTB read hits +system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2121 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2144 # DTB read accesses +system.cpu.dtb.write_hits 1063 # DTB write hits +system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3140 # DTB hits -system.cpu.dtb.data_misses 80 # DTB misses +system.cpu.dtb.write_accesses 1094 # DTB write accesses +system.cpu.dtb.data_hits 3160 # DTB hits +system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3220 # DTB accesses -system.cpu.itb.fetch_hits 2349 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3238 # DTB accesses +system.cpu.itb.fetch_hits 2393 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2387 # ITB accesses +system.cpu.itb.fetch_accesses 2432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,236 +246,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32066 # number of cpu cycles simulated +system.cpu.numCycles 41265 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2752 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2630 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.336992 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10814 # Type of FU issued +system.cpu.iq.rate 0.262062 # Inst issue rate +system.cpu.iq.fu_busy_cnt 111 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3233 # number of memory reference insts executed -system.cpu.iew.exec_branches 1613 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316628 # Inst execution rate -system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9709 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5133 # num instructions producing a value -system.cpu.iew.wb_consumers 6918 # num instructions consuming a value +system.cpu.iew.exec_nop 89 # number of nop insts executed +system.cpu.iew.exec_refs 3251 # number of memory reference insts executed +system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_stores 1096 # Number of stores executed +system.cpu.iew.exec_rate 0.245147 # Inst execution rate +system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9641 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5053 # num instructions producing a value +system.cpu.iew.wb_consumers 6805 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back +system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,70 +487,89 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25930 # The number of ROB reads -system.cpu.rob.rob_writes 27481 # The number of ROB writes -system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26491 # The number of ROB reads +system.cpu.rob.rob_writes 27437 # The number of ROB writes +system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12887 # number of integer regfile reads -system.cpu.int_regfile_writes 7342 # number of integer regfile writes +system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads +system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12831 # number of integer regfile reads +system.cpu.int_regfile_writes 7294 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use -system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use +system.cpu.icache.total_refs 1903 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits -system.cpu.icache.overall_hits::total 1869 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses -system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.125000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46253.125000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.125000 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses -system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # 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number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 4cd56283e..469297f21 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84722 # Simulator instruction rate (inst/s) -host_op_rate 84702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42507676 # Simulator tick rate (ticks/s) -host_mem_usage 261184 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 2502 # Simulator instruction rate (inst/s) +host_op_rate 2502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1255935 # Simulator tick rate (ticks/s) +host_mem_usage 215792 # Number of bytes of host memory used +host_seconds 2.55 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 2087281796 # Wr system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12806733167 # Throughput (bytes/s) +system.membus.data_through_bus 41084 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index afd21634e..ece7545ec 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97330 # Simulator instruction rate (inst/s) -host_op_rate 97300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 495402774 # Simulator tick rate (ticks/s) -host_mem_usage 269640 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 19861 # Simulator instruction rate (inst/s) +host_op_rate 19860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101141711 # Simulator tick rate (ticks/s) +host_mem_usage 224276 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 546705998 # In system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 877089479 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.3 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -383,5 +398,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d97241466..efc4a5915 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9350000 # Number of ticks simulated -final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11848000 # Number of ticks simulated +final_tick 11848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14656 # Simulator instruction rate (inst/s) -host_op_rate 14654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57391857 # Simulator tick rate (ticks/s) -host_mem_usage 269408 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 800 # Simulator instruction rate (inst/s) +host_op_rate 800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3968846 # Simulator tick rate (ticks/s) +host_mem_usage 226160 # Number of bytes of host memory used +host_seconds 2.99 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1010128292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459149223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1469277515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1010128292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1010128292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010128292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459149223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1469277515 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 9280500 # Total gap between requests +system.physmem.totGap 11758500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,86 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 1327750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation +system.physmem.totQLat 1380750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6920750 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access -system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4881.43 # Average queueing delay per request -system.physmem.avgBankLat 19057.90 # Average bank access latency per request +system.physmem.totBankLat 4180000 # Total cycles spent in bank access +system.physmem.avgQLat 5076.29 # Average queueing delay per request +system.physmem.avgBankLat 15367.65 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28939.34 # Average memory access latency -system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25443.93 # Average memory access latency +system.physmem.avgRdBW 1469.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1469.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.55 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.84 # Average read queue length over time +system.physmem.busUtil 11.48 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 207 # Number of row buffer hits during reads +system.physmem.readRowHits 239 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34119.49 # Average gap between requests -system.cpu.branchPred.lookups 1154 # Number of BP lookups -system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.physmem.avgGap 43229.78 # Average gap between requests +system.membus.throughput 1469277515 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 544 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17408 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2542750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.cpu.branchPred.condPredicted 604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 257 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226 # Number of BTB hits +system.cpu.branchPred.BTBHits 240 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.341340 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 708 # DTB read hits +system.cpu.dtb.read_hits 704 # DTB read hits system.cpu.dtb.read_misses 28 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 736 # DTB read accesses -system.cpu.dtb.write_hits 357 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 732 # DTB read accesses +system.cpu.dtb.write_hits 354 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 377 # DTB write accesses -system.cpu.dtb.data_hits 1065 # DTB hits -system.cpu.dtb.data_misses 48 # DTB misses +system.cpu.dtb.write_accesses 373 # DTB write accesses +system.cpu.dtb.data_hits 1058 # DTB hits +system.cpu.dtb.data_misses 47 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1113 # DTB accesses -system.cpu.itb.fetch_hits 1043 # ITB hits +system.cpu.dtb.data_accesses 1105 # DTB accesses +system.cpu.itb.fetch_hits 1045 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1073 # ITB accesses +system.cpu.itb.fetch_accesses 1075 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,237 +242,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18701 # number of cpu cycles simulated +system.cpu.numCycles 23697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4326 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6897 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1157 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 858 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 471 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1121 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1045 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.895714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.301681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6510 84.55% 84.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 117 1.52% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91 1.18% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 172 2.23% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 75 0.97% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61 0.79% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 67 0.87% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 555 7.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.048825 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.291049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5567 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 499 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1144 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 485 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 163 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1056 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 6120 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 485 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1044 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 32 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5812 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4232 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6563 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6551 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2464 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4912 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4000 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1369 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.519481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.232756 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6104 79.27% 79.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 546 7.09% 86.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 391 5.08% 91.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 259 3.36% 94.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 2.69% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 122 1.58% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48 0.62% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15 0.19% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2840 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 778 19.45% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 381 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4065 # Type of FU issued -system.cpu.iq.rate 0.217368 # Inst issue rate -system.cpu.iq.fu_busy_cnt 46 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4000 # Type of FU issued +system.cpu.iq.rate 0.168798 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011000 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15794 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7204 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4037 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 485 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 153 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 948 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 212 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3798 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 733 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 202 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 339 # number of nop insts executed -system.cpu.iew.exec_refs 1114 # number of memory reference insts executed -system.cpu.iew.exec_branches 649 # Number of branches executed -system.cpu.iew.exec_stores 377 # Number of stores executed -system.cpu.iew.exec_rate 0.205978 # Inst execution rate -system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3664 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1729 # num instructions producing a value -system.cpu.iew.wb_consumers 2228 # num instructions consuming a value +system.cpu.iew.exec_nop 322 # number of nop insts executed +system.cpu.iew.exec_refs 1106 # number of memory reference insts executed +system.cpu.iew.exec_branches 638 # Number of branches executed +system.cpu.iew.exec_stores 373 # Number of stores executed +system.cpu.iew.exec_rate 0.160273 # Inst execution rate +system.cpu.iew.wb_sent 3682 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1694 # num instructions producing a value +system.cpu.iew.wb_consumers 2179 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152087 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777421 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2655 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 7215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202430 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6348 87.98% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 203 2.81% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 309 4.28% 95.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 113 1.57% 96.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69 0.96% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 52 0.72% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.46% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.30% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 66 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7215 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -453,119 +484,138 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11840 # The number of ROB reads -system.cpu.rob.rob_writes 11181 # The number of ROB writes -system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12133 # The number of ROB reads +system.cpu.rob.rob_writes 10960 # The number of ROB writes +system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15997 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4649 # number of integer regfile reads -system.cpu.int_regfile_writes 2842 # number of integer regfile writes +system.cpu.cpi 9.927524 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.927524 # CPI: Total CPI of All Threads +system.cpu.ipc 0.100730 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.100730 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4598 # number of integer regfile reads +system.cpu.int_regfile_writes 2789 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1469277515 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use -system.cpu.icache.total_refs 794 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.300481 # Cycle average of tags in use +system.cpu.icache.total_refs 795 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.251337 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 90.926534 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044398 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044398 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 794 # number of overall hits -system.cpu.icache.overall_hits::total 794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1043 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.238734 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.238734 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use -system.cpu.dcache.total_refs 763 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.834743 # Cycle average of tags in use +system.cpu.dcache.total_refs 761 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.976471 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.952941 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 44.507812 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.010866 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.010866 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 550 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 550 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.834743 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 763 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 763 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 763 # number of overall hits -system.cpu.dcache.overall_hits::total 763 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits +system.cpu.dcache.overall_hits::total 761 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses -system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5526500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5526500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4429500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4429500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9956000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9956000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9956000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9956000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 662 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 662 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses +system.cpu.dcache.overall_misses::total 190 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7852000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7852000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5307500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5307500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13159500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13159500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13159500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13159500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 657 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 657 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 956 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 956 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 956 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 956 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 951 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 951 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 951 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 951 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165906 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.165906 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.201883 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.201883 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.201883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.201883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49343.750000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.199790 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.199790 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.199790 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.199790 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72036.697248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72036.697248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65524.691358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65524.691358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69260.526316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69260.526316 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 144 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 105 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 105 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 105 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -755,30 +805,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6402000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6402000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092846 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.089380 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.089380 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76434.426230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76434.426230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 70ee5a4ad..aec79b975 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34130 # Simulator instruction rate (inst/s) -host_op_rate 34121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17175609 # Simulator tick rate (ticks/s) -host_mem_usage 260900 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 388869 # Simulator instruction rate (inst/s) +host_op_rate 388153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195100518 # Simulator tick rate (ticks/s) +host_mem_usage 215488 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1586127168 # Wr system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11879768786 # Throughput (bytes/s) +system.membus.data_through_bus 15414 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 005a80d9b..cb629b252 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14244 # Simulator instruction rate (inst/s) -host_op_rate 14243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91318433 # Simulator tick rate (ticks/s) -host_mem_usage 268332 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 252355 # Simulator instruction rate (inst/s) +host_op_rate 251860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611932908 # Simulator tick rate (ticks/s) +host_mem_usage 223992 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 631324135 # In system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 948922779 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 490 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15680 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 13.3 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -377,5 +392,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8dbb84df8..6938f2714 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13706000 # Number of ticks simulated -final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16387000 # Number of ticks simulated +final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 599 # Simulator instruction rate (inst/s) -host_op_rate 748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1788642 # Simulator tick rate (ticks/s) -host_mem_usage 284080 # Number of bytes of host memory used -host_seconds 7.66 # Real time elapsed on the host +host_inst_rate 31359 # Simulator instruction rate (inst/s) +host_op_rate 39125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111893890 # Simulator tick rate (ticks/s) +host_mem_usage 244352 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 394 # Total number of read requests seen +system.physmem.num_reads::total 393 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25216 # Total number of bytes read from memory +system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13648500 # Total gap between requests +system.physmem.totGap 16329500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 394 # Categorize read packet sizes +system.physmem.readPktSize::6 393 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,34 +149,68 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2507750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests -system.physmem.totBusLat 1970000 # Total cycles spent in databus access -system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6364.85 # Average queueing delay per request -system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation +system.physmem.totQLat 2029000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totBusLat 1965000 # Total cycles spent in databus access +system.physmem.totBankLat 5472500 # Total cycles spent in bank access +system.physmem.avgQLat 5162.85 # Average queueing delay per request +system.physmem.avgBankLat 13924.94 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24087.79 # Average memory access latency +system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.37 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 11.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 294 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34640.86 # Average gap between requests -system.cpu.branchPred.lookups 2491 # Number of BP lookups -system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.physmem.avgGap 41550.89 # Average gap between requests +system.membus.throughput 1534875206 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 352 # Transaction distribution +system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.membus.trans_dist::ReadExReq 41 # Transaction distribution +system.membus.trans_dist::ReadExResp 41 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2471 # Number of BP lookups +system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 700 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups +system.cpu.branchPred.BTBHits 695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -267,235 +301,235 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 27413 # number of cpu cycles simulated +system.cpu.numCycles 32775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2438 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2238 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups +system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8967 # Type of FU issued -system.cpu.iq.rate 0.327108 # Inst issue rate -system.cpu.iq.fu_busy_cnt 230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.272189 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3301 # number of memory reference insts executed -system.cpu.iew.exec_branches 1438 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.311713 # Inst execution rate -system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3894 # num instructions producing a value -system.cpu.iew.wb_consumers 7825 # num instructions consuming a value +system.cpu.iew.exec_refs 3294 # number of memory reference insts executed +system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_stores 1160 # Number of stores executed +system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3885 # num instructions producing a value +system.cpu.iew.wb_consumers 7780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back +system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,150 +540,169 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23047 # The number of ROB reads -system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.rob.rob_reads 23312 # The number of ROB reads +system.cpu.rob.rob_writes 23396 # The number of ROB writes system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39296 # number of integer regfile reads -system.cpu.int_regfile_writes 8001 # number of integer regfile writes +system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39187 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2981 # number of misc regfile reads +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use -system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. +system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use +system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits -system.cpu.icache.overall_hits::total 1590 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits +system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.107247 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,142 +750,142 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # 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number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits +system.cpu.dcache.overall_hits::total 2366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses +system.cpu.dcache.overall_misses::total 497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -841,30 +894,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f41a24ed6..42ebdbb61 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13706000 # Number of ticks simulated -final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16387000 # Number of ticks simulated +final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7143 # Simulator instruction rate (inst/s) -host_op_rate 8913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21323596 # Simulator tick rate (ticks/s) -host_mem_usage 284080 # Number of bytes of host memory used -host_seconds 0.64 # Real time elapsed on the host +host_inst_rate 36614 # Simulator instruction rate (inst/s) +host_op_rate 45680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130634561 # Simulator tick rate (ticks/s) +host_mem_usage 244344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 394 # Total number of read requests seen +system.physmem.num_reads::total 393 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25216 # Total number of bytes read from memory +system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13648500 # Total gap between requests +system.physmem.totGap 16329500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 394 # Categorize read packet sizes +system.physmem.readPktSize::6 393 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,34 +149,68 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2507750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests -system.physmem.totBusLat 1970000 # Total cycles spent in databus access -system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6364.85 # Average queueing delay per request -system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation +system.physmem.totQLat 2029000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totBusLat 1965000 # Total cycles spent in databus access +system.physmem.totBankLat 5472500 # Total cycles spent in bank access +system.physmem.avgQLat 5162.85 # Average queueing delay per request +system.physmem.avgBankLat 13924.94 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24087.79 # Average memory access latency +system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.37 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 11.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 294 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34640.86 # Average gap between requests -system.cpu.branchPred.lookups 2491 # Number of BP lookups -system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.physmem.avgGap 41550.89 # Average gap between requests +system.membus.throughput 1534875206 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 352 # Transaction distribution +system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.membus.trans_dist::ReadExReq 41 # Transaction distribution +system.membus.trans_dist::ReadExResp 41 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2471 # Number of BP lookups +system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 700 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups +system.cpu.branchPred.BTBHits 695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -222,235 +256,235 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 27413 # number of cpu cycles simulated +system.cpu.numCycles 32775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2438 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2238 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups +system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8967 # Type of FU issued -system.cpu.iq.rate 0.327108 # Inst issue rate -system.cpu.iq.fu_busy_cnt 230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.272189 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3301 # number of memory reference insts executed -system.cpu.iew.exec_branches 1438 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.311713 # Inst execution rate -system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3894 # num instructions producing a value -system.cpu.iew.wb_consumers 7825 # num instructions consuming a value +system.cpu.iew.exec_refs 3294 # number of memory reference insts executed +system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_stores 1160 # Number of stores executed +system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3885 # num instructions producing a value +system.cpu.iew.wb_consumers 7780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back +system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,150 +495,169 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23047 # The number of ROB reads -system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.rob.rob_reads 23312 # The number of ROB reads +system.cpu.rob.rob_writes 23396 # The number of ROB writes system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39296 # number of integer regfile reads -system.cpu.int_regfile_writes 8001 # number of integer regfile writes +system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39187 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2981 # number of misc regfile reads +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use -system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. +system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use +system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits -system.cpu.icache.overall_hits::total 1590 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits +system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # 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number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses +system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,142 +705,142 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # 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number of replacements -system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use -system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use +system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # 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number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -796,30 +849,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 9c0909975..05df8bae0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1926 # Simulator instruction rate (inst/s) -host_op_rate 2404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204405 # Simulator tick rate (ticks/s) -host_mem_usage 275696 # Number of bytes of host memory used -host_seconds 2.38 # Real time elapsed on the host +host_inst_rate 686137 # Simulator instruction rate (inst/s) +host_op_rate 854515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 427336749 # Simulator tick rate (ticks/s) +host_mem_usage 232512 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1270858735 # Wr system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9251001568 # Throughput (bytes/s) +system.membus.data_through_bus 26555 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 1d0558bdb..ea8a36796 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122854 # Simulator instruction rate (inst/s) -host_op_rate 153228 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76735417 # Simulator tick rate (ticks/s) -host_mem_usage 275692 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 723203 # Simulator instruction rate (inst/s) +host_op_rate 900650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450384934 # Simulator tick rate (ticks/s) +host_mem_usage 232532 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1270858735 # Wr system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9251001568 # Throughput (bytes/s) +system.membus.data_through_bus 26555 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 2bce78814..744017c0b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66941 # Simulator instruction rate (inst/s) -host_op_rate 83151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380602116 # Simulator tick rate (ticks/s) -host_mem_usage 284140 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 220478 # Simulator instruction rate (inst/s) +host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1251201624 # Simulator tick rate (ticks/s) +host_mem_usage 241012 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 554507297 # In system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 862566907 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22400 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -404,5 +419,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 54d30dc78..4cccc3a14 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19339000 # Number of ticks simulated -final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24539000 # Number of ticks simulated +final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26477 # Simulator instruction rate (inst/s) -host_op_rate 26474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88053451 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 40560 # Simulator instruction rate (inst/s) +host_op_rate 40552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171130571 # Simulator tick rate (ticks/s) +host_mem_usage 226208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19292000 # Total gap between requests +system.physmem.totGap 24472000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -149,34 +149,69 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation +system.physmem.totQLat 2632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5824.18 # Average queueing delay per request -system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 5784.62 # Average queueing delay per request +system.physmem.avgBankLat 18041.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30678.57 # Average memory access latency -system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28825.82 # Average memory access latency +system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.76 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.72 # Average read queue length over time +system.physmem.busUtil 9.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.53 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 334 # Number of row buffer hits during reads +system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42400.00 # Average gap between requests -system.cpu.branchPred.lookups 1154 # Number of BP lookups -system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted +system.physmem.avgGap 53784.62 # Average gap between requests +system.membus.throughput 1186682424 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 404 # Transaction distribution +system.membus.trans_dist::ReadResp 404 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 910 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 29120 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.4 # Layer utilization (%) +system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 336 # Number of BTB hits +system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -198,34 +233,34 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 38679 # number of cpu cycles simulated +system.cpu.numCycles 49079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2229 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3135 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3133 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. -system.cpu.activity 13.899015 # Percentage of cycles cpu is active +system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. +system.cpu.activity 10.968031 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -237,72 +272,72 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use -system.cpu.icache.total_refs 429 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use +system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits -system.cpu.icache.overall_hits::total 429 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses -system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits +system.cpu.icache.overall_hits::total 428 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,48 +346,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -370,17 +424,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22623500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6716000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29339500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3640500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22623500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10356500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32980000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22623500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10356500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32980000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -403,17 +457,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71367.507886 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77195.402299 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72622.524752 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71382.352941 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71382.352941 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72483.516484 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72483.516484 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,17 +487,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -455,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use -system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use +system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits -system.cpu.dcache.overall_hits::total 1644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses -system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits +system.cpu.dcache.overall_hits::total 1637 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses +system.cpu.dcache.overall_misses::total 451 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21383500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28862000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28862000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -508,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -548,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -564,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index c79016c7b..37ca97b46 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17026500 # Number of ticks simulated -final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21759500 # Number of ticks simulated +final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19281 # Simulator instruction rate (inst/s) -host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63663526 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 43168 # Simulator instruction rate (inst/s) +host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182102261 # Simulator tick rate (ticks/s) +host_mem_usage 228268 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 478 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16967000 # Total gap between requests +system.physmem.totGap 21680500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,36 +149,70 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2843000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2435500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access -system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5947.70 # Average queueing delay per request -system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.totBankLat 8676250 # Total cycles spent in bank access +system.physmem.avgQLat 5095.19 # Average queueing delay per request +system.physmem.avgBankLat 18151.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30537.13 # Average memory access latency -system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28246.34 # Average memory access latency +system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 351 # Number of row buffer hits during reads +system.physmem.readRowHits 375 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 35495.82 # Average gap between requests -system.cpu.branchPred.lookups 2218 # Number of BP lookups -system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups -system.cpu.branchPred.BTBHits 508 # Number of BTB hits +system.physmem.avgGap 45356.69 # Average gap between requests +system.membus.throughput 1405914658 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 427 # Transaction distribution +system.membus.trans_dist::ReadResp 427 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2196 # Number of BP lookups +system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -198,94 +232,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 34054 # number of cpu cycles simulated +system.cpu.numCycles 43520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3093 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3054 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2958 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available @@ -321,113 +355,113 @@ system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8318 # Type of FU issued -system.cpu.iq.rate 0.244259 # Inst issue rate +system.cpu.iq.FU_type_0::total 8313 # Type of FU issued +system.cpu.iq.rate 0.191016 # Inst issue rate system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1546 # number of nop insts executed -system.cpu.iew.exec_refs 3202 # number of memory reference insts executed -system.cpu.iew.exec_branches 1355 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.232924 # Inst execution rate -system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7467 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2949 # num instructions producing a value -system.cpu.iew.wb_consumers 4258 # num instructions consuming a value +system.cpu.iew.exec_nop 1529 # number of nop insts executed +system.cpu.iew.exec_refs 3196 # number of memory reference insts executed +system.cpu.iew.exec_branches 1356 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.182353 # Inst execution rate +system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2922 # num instructions producing a value +system.cpu.iew.wb_consumers 4200 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back +system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,119 +472,138 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23961 # The number of ROB reads -system.cpu.rob.rob_writes 22589 # The number of ROB writes -system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24277 # The number of ROB reads +system.cpu.rob.rob_writes 22442 # The number of ROB writes +system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10750 # number of integer regfile reads -system.cpu.int_regfile_writes 5236 # number of integer regfile writes +system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10757 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 148 # number of misc regfile reads +system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use +system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses -system.cpu.icache.overall_misses::total 446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.221670 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.221670 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.221670 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.221670 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50096.412556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50096.412556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits +system.cpu.icache.overall_hits::total 1541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses +system.cpu.icache.overall_misses::total 453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30806000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227182 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.227182 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.227182 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.227182 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.227182 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.584950 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.776656 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005023 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006786 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 163.410737 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.683266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004987 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006747 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34490000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23576500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34490000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) @@ -601,17 +654,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51900.297619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64978.021978 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54687.353630 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54411.087866 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54411.087866 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70168.154762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77686.813187 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71770.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75372.549020 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75372.549020 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72154.811715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72154.811715 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +684,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13259027 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4798293 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18057320 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13259027 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6830321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20089348 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13259027 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6830321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20089348 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19402750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5959000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25361750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3218500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3218500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19402750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28580250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19402750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28580250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -653,91 +706,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57746.279762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65483.516484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59395.199063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use +system.cpu.dcache.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits -system.cpu.dcache.overall_hits::total 2424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses -system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 91.370944 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -746,30 +799,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 773dc4053..e850cb6a0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85249 # Simulator instruction rate (inst/s) -host_op_rate 85225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42601271 # Simulator tick rate (ticks/s) -host_mem_usage 261900 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 727521 # Simulator instruction rate (inst/s) +host_op_rate 725084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 361375060 # Simulator tick rate (ticks/s) +host_mem_usage 216568 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1258341933 # Wr system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10764361885 # Throughput (bytes/s) +system.membus.data_through_bus 31292 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 45395bf9c..0d57ed336 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3112 # Simulator instruction rate (inst/s) -host_op_rate 3112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16931146 # Simulator tick rate (ticks/s) -host_mem_usage 270356 # Number of bytes of host memory used -host_seconds 1.87 # Real time elapsed on the host +host_inst_rate 482351 # Simulator instruction rate (inst/s) +host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2613274672 # Simulator tick rate (ticks/s) +host_mem_usage 225064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 608984289 # In system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 888186388 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 388 # Transaction distribution +system.membus.trans_dist::ReadResp 388 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28096 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.5 # Layer utilization (%) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -369,5 +384,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 30ea78059..43017685d 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14724500 # Number of ticks simulated -final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18326500 # Number of ticks simulated +final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11850 # Simulator instruction rate (inst/s) -host_op_rate 11850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30123505 # Simulator tick rate (ticks/s) -host_mem_usage 266600 # Number of bytes of host memory used -host_seconds 0.49 # Real time elapsed on the host +host_inst_rate 41507 # Simulator instruction rate (inst/s) +host_op_rate 41499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131284333 # Simulator tick rate (ticks/s) +host_mem_usage 224304 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 28544 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14617000 # Total gap between requests +system.physmem.totGap 18199000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,35 +149,70 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2285750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation +system.physmem.totQLat 2004500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 8263750 # Total cycles spent in bank access -system.physmem.avgQLat 5125.00 # Average queueing delay per request -system.physmem.avgBankLat 18528.59 # Average bank access latency per request +system.physmem.totBankLat 6737500 # Total cycles spent in bank access +system.physmem.avgQLat 4494.39 # Average queueing delay per request +system.physmem.avgBankLat 15106.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28653.59 # Average memory access latency -system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24600.90 # Average memory access latency +system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.87 # Average read queue length over time +system.physmem.busUtil 12.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 338 # Number of row buffer hits during reads +system.physmem.readRowHits 380 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32773.54 # Average gap between requests -system.cpu.branchPred.lookups 2226 # Number of BP lookups -system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted +system.physmem.avgGap 40804.93 # Average gap between requests +system.membus.throughput 1557525987 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 399 # Transaction distribution +system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.trans_dist::ReadExReq 47 # Transaction distribution +system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.cpu.branchPred.lookups 2238 # Number of BP lookups +system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 599 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups +system.cpu.branchPred.BTBHits 603 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -198,92 +233,92 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 29450 # number of cpu cycles simulated +system.cpu.numCycles 36654 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2083 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2096 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1969 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename +system.cpu.rename.RunCycles 1984 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -314,118 +349,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8907 # Type of FU issued -system.cpu.iq.rate 0.302445 # Inst issue rate +system.cpu.iq.FU_type_0::total 8903 # Type of FU issued +system.cpu.iq.rate 0.242893 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3204 # number of memory reference insts executed -system.cpu.iew.exec_branches 1349 # Number of branches executed -system.cpu.iew.exec_stores 1531 # Number of stores executed -system.cpu.iew.exec_rate 0.288387 # Inst execution rate -system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8150 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4198 # num instructions producing a value -system.cpu.iew.wb_consumers 6619 # num instructions consuming a value +system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_branches 1351 # Number of branches executed +system.cpu.iew.exec_stores 1523 # Number of stores executed +system.cpu.iew.exec_rate 0.231953 # Inst execution rate +system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8157 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4222 # num instructions producing a value +system.cpu.iew.wb_consumers 6684 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back +system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,116 +473,135 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21027 # The number of ROB reads -system.cpu.rob.rob_writes 21246 # The number of ROB writes +system.cpu.rob.rob_reads 21419 # The number of ROB reads +system.cpu.rob.rob_writes 21457 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads -system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7037 # number of integer regfile writes +system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads +system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use -system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use +system.cpu.icache.total_refs 1371 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits -system.cpu.icache.overall_hits::total 1361 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses -system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits +system.cpu.icache.overall_hits::total 1371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses +system.cpu.icache.overall_misses::total 442 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -568,17 +622,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -601,17 +655,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +685,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -653,91 +707,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use -system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use +system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits -system.cpu.dcache.overall_hits::total 2181 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses -system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -746,30 +800,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 94ea423b8..759fbed05 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57024 # Simulator instruction rate (inst/s) -host_op_rate 57013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28496468 # Simulator tick rate (ticks/s) -host_mem_usage 257792 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 671850 # Simulator instruction rate (inst/s) +host_op_rate 669870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 333940022 # Simulator tick rate (ticks/s) +host_mem_usage 212612 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10739295580 # Throughput (bytes/s) +system.membus.data_through_bus 31101 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 91942b523..45ae1e677 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16783500 # Number of ticks simulated -final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20764500 # Number of ticks simulated +final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18770 # Simulator instruction rate (inst/s) -host_op_rate 18768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59128079 # Simulator tick rate (ticks/s) -host_mem_usage 276316 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 44697 # Simulator instruction rate (inst/s) +host_op_rate 44687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174155494 # Simulator tick rate (ticks/s) +host_mem_usage 232524 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16708000 # Total gap between requests +system.physmem.totGap 20696000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2671750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation +system.physmem.totQLat 3131250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6316.19 # Average queueing delay per request -system.physmem.avgBankLat 19406.03 # Average bank access latency per request +system.physmem.totBankLat 6545000 # Total cycles spent in bank access +system.physmem.avgQLat 7402.48 # Average queueing delay per request +system.physmem.avgBankLat 15472.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30722.22 # Average memory access latency -system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27875.30 # Average memory access latency +system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.60 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.77 # Average read queue length over time +system.physmem.busUtil 10.19 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 300 # Number of row buffer hits during reads +system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39498.82 # Average gap between requests +system.physmem.avgGap 48926.71 # Average gap between requests +system.membus.throughput 1303763635 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 342 # Transaction distribution +system.membus.trans_dist::ReadResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 846 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 27072 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.0 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -180,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 33568 # number of cpu cycles simulated +system.cpu.numCycles 41530 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -202,12 +237,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 18.604028 # Percentage of cycles cpu is active +system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6246 # Number of cycles cpu stages are processed. +system.cpu.activity 15.039730 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -219,72 +254,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads -system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use -system.cpu.icache.total_refs 896 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use +system.cpu.icache.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits -system.cpu.icache.overall_hits::total 896 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits +system.cpu.icache.overall_hits::total 892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52479.281768 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52479.281768 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,48 +328,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15424000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53003.436426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53003.436426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.396977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.660763 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -355,17 +409,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15105500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3319000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8029000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15105500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8029000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -388,17 +442,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52268.166090 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62622.641509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,17 +472,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2664291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14191519 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6384078 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17911306 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6384078 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17911306 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -440,27 +494,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50269.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41495.669591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -477,14 +531,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25629500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25629500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25629500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25629500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -501,19 +555,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -533,14 +587,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -549,14 +603,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index bd3dfe2fe..b27d1e6f6 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73566 # Simulator instruction rate (inst/s) -host_op_rate 73547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37192728 # Simulator tick rate (ticks/s) -host_mem_usage 269044 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 565055 # Simulator instruction rate (inst/s) +host_op_rate 563581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 284338324 # Simulator tick rate (ticks/s) +host_mem_usage 222908 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1879755057 # Wr system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11559473001 # Throughput (bytes/s) +system.membus.data_through_bus 31147 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 4cc5c5030..404dd533e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116604 # Simulator instruction rate (inst/s) -host_op_rate 116555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 608021957 # Simulator tick rate (ticks/s) -host_mem_usage 277492 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 413138 # Simulator instruction rate (inst/s) +host_op_rate 412367 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2148212772 # Simulator tick rate (ticks/s) +host_mem_usage 231400 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 587050360 # In system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 895539568 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 778 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 24896 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.6 # Layer utilization (%) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 55600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -354,5 +369,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index add7e0659..43264ddcf 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16021500 # Number of ticks simulated -final_tick 16021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19589000 # Number of ticks simulated +final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25477 # Simulator instruction rate (inst/s) -host_op_rate 46153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75857343 # Simulator tick rate (ticks/s) -host_mem_usage 290184 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 1364 # Simulator instruction rate (inst/s) +host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4967212 # Simulator tick rate (ticks/s) +host_mem_usage 245432 # Number of bytes of host memory used +host_seconds 3.94 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory -system.physmem.bytes_read::total 26944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory -system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1110507755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 571232406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1681740162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1110507755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1110507755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1110507755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 571232406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1681740162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 422 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory +system.physmem.bytes_read::total 26432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 413 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 414 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 422 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 26944 # Total number of bytes read from memory +system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 26432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16004000 # Total gap between requests +system.physmem.totGap 19541000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 422 # Categorize read packet sizes +system.physmem.readPktSize::6 414 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,265 +149,303 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2229750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13029750 # Sum of mem lat for all requests -system.physmem.totBusLat 2110000 # Total cycles spent in databus access -system.physmem.totBankLat 8690000 # Total cycles spent in bank access -system.physmem.avgQLat 5283.77 # Average queueing delay per request -system.physmem.avgBankLat 20592.42 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation +system.physmem.totQLat 1394000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests +system.physmem.totBusLat 2070000 # Total cycles spent in databus access +system.physmem.totBankLat 7617500 # Total cycles spent in bank access +system.physmem.avgQLat 3367.15 # Average queueing delay per request +system.physmem.avgBankLat 18399.76 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30876.18 # Average memory access latency -system.physmem.avgRdBW 1681.74 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26766.91 # Average memory access latency +system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1681.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 13.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.81 # Average read queue length over time +system.physmem.busUtil 10.54 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 302 # Number of row buffer hits during reads +system.physmem.readRowHits 327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 37924.17 # Average gap between requests -system.cpu.branchPred.lookups 3090 # Number of BP lookups -system.cpu.branchPred.condPredicted 3090 # Number of conditional branches predicted +system.physmem.avgGap 47200.48 # Average gap between requests +system.membus.throughput 1349328705 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 337 # Transaction distribution +system.membus.trans_dist::ReadResp 336 # Transaction distribution +system.membus.trans_dist::ReadExReq 77 # Transaction distribution +system.membus.trans_dist::ReadExResp 77 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26432 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.7 # Layer utilization (%) +system.cpu.branchPred.lookups 3089 # Number of BP lookups +system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2310 # Number of BTB lookups -system.cpu.branchPred.BTBHits 714 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.909091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 211 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32044 # number of cpu cycles simulated +system.cpu.numCycles 39179 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9523 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14230 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 925 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2389 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3636 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 340 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 19279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.312568 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.813131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15433 80.05% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214 1.11% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 145 0.75% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.13% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.00% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 169 0.88% 84.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 290 1.50% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 155 0.80% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2464 12.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 19279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.096430 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.444077 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10008 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3780 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1785 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24215 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1785 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10348 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3350 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 726 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 620 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25234 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54863 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54847 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3578 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3333 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1819 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2277 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20098 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 251 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9536 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13688 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 19279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.881996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736426 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13831 71.74% 71.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1491 7.73% 79.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1108 5.75% 85.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 718 3.72% 88.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 686 3.56% 92.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 589 3.06% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 582 3.02% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 230 1.19% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 19279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 127 76.51% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 14.46% 90.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 9.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13619 80.09% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1977 11.63% 91.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1394 8.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17004 # Type of FU issued -system.cpu.iq.rate 0.530645 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009762 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29666 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17024 # Type of FU issued +system.cpu.iq.rate 0.434518 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17163 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 167 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1785 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2277 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 674 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16111 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3149 # number of memory reference insts executed -system.cpu.iew.exec_branches 1620 # Number of branches executed -system.cpu.iew.exec_stores 1296 # Number of stores executed -system.cpu.iew.exec_rate 0.502777 # Inst execution rate -system.cpu.iew.wb_sent 15852 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15645 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10112 # num instructions producing a value -system.cpu.iew.wb_consumers 15481 # num instructions consuming a value +system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_branches 1621 # Number of branches executed +system.cpu.iew.exec_stores 1278 # Number of stores executed +system.cpu.iew.exec_rate 0.411777 # Inst execution rate +system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10119 # num instructions producing a value +system.cpu.iew.wb_consumers 15566 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.488235 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653188 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10375 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 582 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 17494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.557162 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.425293 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13941 79.69% 79.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1339 7.65% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 594 3.40% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 714 4.08% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 361 2.06% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 136 0.78% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 122 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.42% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 213 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 17494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -420,117 +458,136 @@ system.cpu.commit.int_insts 9654 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37403 # The number of ROB reads -system.cpu.rob.rob_writes 42056 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40106 # The number of ROB reads +system.cpu.rob.rob_writes 42382 # The number of ROB writes +system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.956134 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.956134 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167894 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167894 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28607 # number of integer regfile reads -system.cpu.int_regfile_writes 17139 # number of integer regfile writes +system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28721 # number of integer regfile reads +system.cpu.int_regfile_writes 17199 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7155 # number of misc regfile reads +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 134.419040 # Cycle average of tags in use -system.cpu.icache.total_refs 1594 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.713262 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use +system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 134.419040 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.065634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.065634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1594 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1594 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1594 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1594 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1594 # number of overall hits -system.cpu.icache.overall_hits::total 1594 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses -system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19224000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19224000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19224000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19224000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19224000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19224000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.188804 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.188804 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.188804 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.188804 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.188804 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.188804 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51816.711590 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51816.711590 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51816.711590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51816.711590 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits +system.cpu.icache.overall_hits::total 1611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses +system.cpu.icache.overall_misses::total 370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186774 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65636.486486 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65636.486486 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65636.486486 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65636.486486 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15030000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15030000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15030000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15030000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15030000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15030000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142494 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142494 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142494 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53678.571429 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53678.571429 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 96 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 96 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 96 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 96 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18984000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18984000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18984000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18984000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18984000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18984000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69284.671533 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69284.671533 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.756635 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.651714 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005814 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005952 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 134.530220 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.226414 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001014 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005120 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 131.033866 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.617848 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003999 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004964 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -540,61 +597,61 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 345 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 337 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60303.030303 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54262.318841 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54629.870130 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54629.870130 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54329.383886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54329.383886 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995192 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995192 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68494.505495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76796.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70071.216617 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70370.129870 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70370.129870 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70126.811594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70126.811594 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,154 +660,154 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8307000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8307000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4438000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4438000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12745000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12745000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12745000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12745000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses +system.cpu.dcache.overall_misses::total 208 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5649500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15000000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15000000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15000000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15000000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1607 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084158 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2542 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2542 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2542 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2542 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081518 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081518 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.083497 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.083497 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.083497 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.083497 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61080.882353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61080.882353 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57636.363636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57636.363636 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59835.680751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59835.680751 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72115.384615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72115.384615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index d96944a1a..3b513d323 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12304541407 # Throughput (bytes/s) +system.membus.data_through_bus 69090 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11231 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 496e32aca..7844ef634 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 512306933 # In system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 814726003 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 23104 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.5 # Layer utilization (%) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 56716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -351,5 +370,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index a6935acc4..6de850a93 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24422500 # Number of ticks simulated -final_tick 24422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23841000 # Number of ticks simulated +final_tick 23841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26625 # Simulator instruction rate (inst/s) -host_op_rate 26623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51014333 # Simulator tick rate (ticks/s) -host_mem_usage 270288 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_inst_rate 85306 # Simulator instruction rate (inst/s) +host_op_rate 85298 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159545701 # Simulator tick rate (ticks/s) +host_mem_usage 228064 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory -system.physmem.bytes_read::total 62080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory -system.physmem.num_reads::total 970 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1629972362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 911945951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2541918313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1629972362 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1629972362 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1629972362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 911945951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2541918313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 970 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1677781972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 939557904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2617339877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1677781972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1677781972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1677781972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 939557904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2617339877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62080 # Total number of bytes read from memory +system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62400 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 121 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24269500 # Total gap between requests +system.physmem.totGap 23399000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 970 # Categorize read packet sizes +system.physmem.readPktSize::6 975 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,13 +85,13 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -149,56 +149,100 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 22107000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52930750 # Sum of mem lat for all requests -system.physmem.totBusLat 4850000 # Total cycles spent in databus access -system.physmem.totBankLat 25973750 # Total cycles spent in bank access -system.physmem.avgQLat 22790.72 # Average queueing delay per request -system.physmem.avgBankLat 26777.06 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.392265 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 160.897114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 490.133684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 75 41.44% 41.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 28 15.47% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 10.50% 67.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 11.05% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 1.10% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 4 2.21% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.21% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 1.66% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.10% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 2.21% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.10% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.55% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.55% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.10% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.10% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 1.10% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.55% 95.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1 0.55% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 1 0.55% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 0.55% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 2 1.10% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.55% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 0.55% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 2 1.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation +system.physmem.totQLat 6851500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 28281500 # Sum of mem lat for all requests +system.physmem.totBusLat 4875000 # Total cycles spent in databus access +system.physmem.totBankLat 16555000 # Total cycles spent in bank access +system.physmem.avgQLat 7027.18 # Average queueing delay per request +system.physmem.avgBankLat 16979.49 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 54567.78 # Average memory access latency -system.physmem.avgRdBW 2541.92 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 29006.67 # Average memory access latency +system.physmem.avgRdBW 2617.34 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2541.92 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2617.34 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.86 # Data bus utilization in percentage -system.physmem.avgRdQLen 2.17 # Average read queue length over time +system.physmem.busUtil 20.45 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.19 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 449 # Number of row buffer hits during reads +system.physmem.readRowHits 794 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25020.10 # Average gap between requests -system.cpu.branchPred.lookups 6091 # Number of BP lookups -system.cpu.branchPred.condPredicted 3456 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4406 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1013 # Number of BTB hits +system.physmem.avgGap 23998.97 # Average gap between requests +system.membus.throughput 2617339877 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 829 # Transaction distribution +system.membus.trans_dist::ReadResp 829 # Transaction distribution +system.membus.trans_dist::ReadExReq 146 # Transaction distribution +system.membus.trans_dist::ReadExResp 146 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1950 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62400 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9055000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 38.0 # Layer utilization (%) +system.cpu.branchPred.lookups 6923 # Number of BP lookups +system.cpu.branchPred.condPredicted 3910 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1532 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5090 # Number of BTB lookups +system.cpu.branchPred.BTBHits 950 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 22.991375 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 798 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.664047 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 864 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 198 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4448 # DTB read hits -system.cpu.dtb.read_misses 96 # DTB read misses +system.cpu.dtb.read_hits 4694 # DTB read hits +system.cpu.dtb.read_misses 109 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4544 # DTB read accesses -system.cpu.dtb.write_hits 2020 # DTB write hits -system.cpu.dtb.write_misses 84 # DTB write misses +system.cpu.dtb.read_accesses 4803 # DTB read accesses +system.cpu.dtb.write_hits 2055 # DTB write hits +system.cpu.dtb.write_misses 93 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2104 # DTB write accesses -system.cpu.dtb.data_hits 6468 # DTB hits -system.cpu.dtb.data_misses 180 # DTB misses +system.cpu.dtb.write_accesses 2148 # DTB write accesses +system.cpu.dtb.data_hits 6749 # DTB hits +system.cpu.dtb.data_misses 202 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6648 # DTB accesses -system.cpu.itb.fetch_hits 4827 # ITB hits -system.cpu.itb.fetch_misses 49 # ITB misses +system.cpu.dtb.data_accesses 6951 # DTB accesses +system.cpu.itb.fetch_hits 5431 # ITB hits +system.cpu.itb.fetch_misses 58 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 4876 # ITB accesses +system.cpu.itb.fetch_accesses 5489 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -213,356 +257,355 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48846 # number of cpu cycles simulated +system.cpu.numCycles 47683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 33885 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6091 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1593 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 523 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4827 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28036 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.208625 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.641797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1647 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37826 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6923 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1907 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 435 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5431 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 913 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.308677 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.731944 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22313 79.59% 79.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 519 1.85% 81.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 362 1.29% 82.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 384 1.37% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 439 1.57% 85.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 391 1.39% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 437 1.56% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 371 1.32% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2820 10.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22552 78.02% 78.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 590 2.04% 80.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 356 1.23% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 460 1.59% 82.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 445 1.54% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 430 1.49% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 481 1.66% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 392 1.36% 88.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3198 11.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28036 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.124698 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.693711 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38743 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4948 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 475 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2422 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 482 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30410 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 547 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2422 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 39365 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6014 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 28904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.145188 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.793281 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 39785 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9139 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5505 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2806 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33037 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 796 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2806 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40500 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6036 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2126 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28231 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2058 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21224 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 34730 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 34696 # Number of integer rename lookups +system.cpu.rename.RunCycles 5106 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2260 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30593 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2227 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37660 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12084 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5609 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2913 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1333 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 54 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5822 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3090 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1408 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1281 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 3019 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1424 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25056 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 20851 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7098 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28036 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.743722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.323178 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26797 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22164 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13006 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28904 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.766814 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.345310 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18861 67.27% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3429 12.23% 79.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2549 9.09% 88.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1540 5.49% 94.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 935 3.33% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 455 1.62% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 194 0.69% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19221 66.50% 66.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3610 12.49% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2656 9.19% 88.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1611 5.57% 93.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1014 3.51% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 491 1.70% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 230 0.80% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 50 0.17% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28036 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28904 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.99% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 103 61.68% 64.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 59 35.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.84% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 106 60.23% 63.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 36.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6975 65.76% 65.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2523 23.79% 89.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1103 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7310 65.49% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2686 24.06% 89.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1161 10.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10606 # Type of FU issued +system.cpu.iq.FU_type_0::total 11162 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6760 65.98% 66.00% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.01% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.03% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2371 23.14% 89.18% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1109 10.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7255 65.94% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2595 23.59% 89.57% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1147 10.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10245 # Type of FU issued +system.cpu.iq.FU_type_1::total 11002 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13735 65.87% 65.89% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.90% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.92% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4894 23.47% 89.39% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2212 10.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14565 65.71% 65.73% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.74% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::MemRead 5281 23.83% 89.59% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2308 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 20851 # Type of FU issued -system.cpu.iq.rate 0.426872 # Inst issue rate +system.cpu.iq.FU_type::total 22164 # Type of FU issued +system.cpu.iq.rate 0.464820 # Inst issue rate system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 81 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 167 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004125 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003885 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008009 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 69931 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 36600 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18226 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads +system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 176 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.003880 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004061 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.007941 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73490 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 39895 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 20993 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 22314 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1730 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 468 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1907 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 543 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 56 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1537 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 416 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1836 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 559 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 292 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2853 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25308 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 582 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5633 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2614 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 221 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 19605 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2207 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1246 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2806 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27087 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 546 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6109 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2832 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 255 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1333 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20623 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2441 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2376 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1541 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 98 # number of nop insts executed -system.cpu.iew.exec_nop::1 81 # number of nop insts executed -system.cpu.iew.exec_nop::total 179 # number of nop insts executed -system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3257 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6671 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1525 # Number of branches executed -system.cpu.iew.exec_branches::1 1521 # Number of branches executed -system.cpu.iew.exec_branches::total 3046 # Number of branches executed -system.cpu.iew.exec_stores::0 1066 # Number of stores executed -system.cpu.iew.exec_stores::1 1050 # Number of stores executed -system.cpu.iew.exec_stores::total 2116 # Number of stores executed -system.cpu.iew.exec_rate 0.401363 # Inst execution rate -system.cpu.iew.wb_sent::0 9356 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9171 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18527 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9033 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18246 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4732 # num instructions producing a value -system.cpu.iew.wb_producers::1 4628 # num instructions producing a value -system.cpu.iew.wb_producers::total 9360 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6204 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6054 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12258 # num instructions consuming a value +system.cpu.iew.exec_nop::0 115 # number of nop insts executed +system.cpu.iew.exec_nop::1 92 # number of nop insts executed +system.cpu.iew.exec_nop::total 207 # number of nop insts executed +system.cpu.iew.exec_refs::0 3520 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3467 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6987 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1642 # Number of branches executed +system.cpu.iew.exec_branches::1 1654 # Number of branches executed +system.cpu.iew.exec_branches::total 3296 # Number of branches executed +system.cpu.iew.exec_stores::0 1079 # Number of stores executed +system.cpu.iew.exec_stores::1 1091 # Number of stores executed +system.cpu.iew.exec_stores::total 2170 # Number of stores executed +system.cpu.iew.exec_rate 0.432502 # Inst execution rate +system.cpu.iew.wb_sent::0 9753 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9719 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19472 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9565 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19146 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4912 # num instructions producing a value +system.cpu.iew.wb_producers::1 4854 # num instructions producing a value +system.cpu.iew.wb_producers::total 9766 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6410 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6363 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12773 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.188613 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.184928 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.373541 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.762734 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.764453 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.763583 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.200596 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.200931 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.401527 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.766303 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.762848 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.764582 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14336 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 961 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27993 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.456507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.239608 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1138 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.443084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.197327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22231 79.42% 79.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3185 11.38% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1025 3.66% 94.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 479 1.71% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 332 1.19% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 227 0.81% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 194 0.69% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 80 0.29% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 240 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22992 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3164 10.97% 90.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1129 3.91% 94.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 501 1.74% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 358 1.24% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 236 0.82% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 188 0.65% 99.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70 0.24% 99.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 203 0.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27993 # Number of insts commited each cycle -system.cpu.commit.committedInsts::0 6389 # Number of instructions committed -system.cpu.commit.committedInsts::1 6390 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 28841 # Number of insts commited each cycle +system.cpu.commit.committedInsts::0 6390 # Number of instructions committed +system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed -system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed @@ -588,191 +631,210 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 240 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 126718 # The number of ROB reads -system.cpu.rob.rob_writes 53072 # The number of ROB writes -system.cpu.timesIdled 387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20810 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts::0 6372 # Number of Instructions Simulated -system.cpu.committedInsts::1 6373 # Number of Instructions Simulated -system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated +system.cpu.rob.rob_reads 132883 # The number of ROB reads +system.cpu.rob.rob_writes 57054 # The number of ROB writes +system.cpu.timesIdled 370 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18779 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6373 # Number of Instructions Simulated +system.cpu.committedInsts::1 6372 # Number of Instructions Simulated +system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.665725 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.664522 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.832562 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.130451 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.130471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.260922 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24678 # number of integer regfile reads -system.cpu.int_regfile_writes 13757 # number of integer regfile writes +system.cpu.cpi::0 7.482034 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.483208 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.741310 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.133654 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.133633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.267286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25857 # number of integer regfile reads +system.cpu.int_regfile_writes 14461 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes +system.cpu.toL2Bus.throughput 2622708779 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 525000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 293.126270 # Cycle average of tags in use -system.cpu.icache.total_refs 3772 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.044872 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 313.799979 # Cycle average of tags in use +system.cpu.icache.total_refs 4370 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.969697 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 293.126270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.143128 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.143128 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3772 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3772 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3772 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3772 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3772 # number of overall hits -system.cpu.icache.overall_hits::total 3772 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1048 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1048 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1048 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1048 # number of overall misses -system.cpu.icache.overall_misses::total 1048 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 78261996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 78261996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 78261996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 78261996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 78261996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 78261996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4820 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4820 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4820 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4820 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217427 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217427 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217427 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217427 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217427 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217427 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74677.477099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74677.477099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74677.477099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74677.477099 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3131 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 313.799979 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.153223 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.153223 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4370 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4370 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4370 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4370 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4370 # number of overall hits +system.cpu.icache.overall_hits::total 4370 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1055 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1055 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1055 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1055 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1055 # number of overall misses +system.cpu.icache.overall_misses::total 1055 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67889996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67889996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67889996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67889996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67889996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67889996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5425 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5425 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5425 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5425 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194470 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.194470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.194470 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.194470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.194470 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.194470 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64350.707109 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64350.707109 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64350.707109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64350.707109 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2740 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.439394 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.153846 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 424 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 424 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 424 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 424 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 624 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48109998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 48109998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48109998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 48109998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48109998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 48109998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.129461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.129461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77099.355769 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77099.355769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77099.355769 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77099.355769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77099.355769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77099.355769 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 428 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 428 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 428 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 428 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45895996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45895996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45895996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45895996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45895996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45895996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115576 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115576 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115576 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73199.355662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73199.355662 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73199.355662 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73199.355662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73199.355662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73199.355662 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 408.674581 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 433.839977 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 829 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002413 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 293.629007 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 115.045574 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.008961 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003511 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.012472 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 314.320815 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 119.519162 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009592 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003647 # 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miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997579 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76307.877814 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88131.188119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79206.310680 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83126.712329 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83126.712329 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76307.877814 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86031.609195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79796.391753 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76307.877814 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86031.609195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79796.391753 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72393.600000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80460.784314 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74378.769602 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71650.684932 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71650.684932 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72393.600000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76785.714286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73970.256410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72393.600000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76785.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73970.256410 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,158 +843,158 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 622 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.344051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73845.905172 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.200000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68253.676471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62092.279855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59359.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59359.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.200000 # 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Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.454023 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 213.416851 # Cycle average of tags in use +system.cpu.dcache.total_refs 4586 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.102857 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 203.203118 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.049610 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.049610 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3312 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3312 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4334 # number of overall hits -system.cpu.dcache.overall_hits::total 4334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses -system.cpu.dcache.overall_misses::total 1031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25422500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25422500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 53416467 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 53416467 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 78838967 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 78838967 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 78838967 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 78838967 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3635 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3635 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 213.416851 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.052104 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4586 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4586 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4586 # number of overall hits +system.cpu.dcache.overall_hits::total 4586 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 326 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1039 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1039 # number of overall misses +system.cpu.dcache.overall_misses::total 1039 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23287500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23287500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 43025436 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 43025436 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 66312936 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 66312936 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 66312936 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 66312936 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5365 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5365 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5365 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5365 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088858 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.088858 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192171 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192171 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192171 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192171 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78707.430341 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78707.430341 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75446.987288 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75446.987288 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76468.445199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76468.445199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4608 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5625 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5625 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5625 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5625 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184711 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184711 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184711 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184711 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71434.049080 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71434.049080 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60344.230014 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60344.230014 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63823.807507 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63823.807507 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63823.807507 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63823.807507 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4266 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 128 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.086957 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.328125 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 121 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 122 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 567 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 567 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 689 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 689 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 689 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 689 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12283998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12283998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30297498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30297498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30297498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30297498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055571 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055571 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16628000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16628000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10609995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10609995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27237995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27237995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27237995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27237995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052375 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064865 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064865 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89175.742574 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89175.742574 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84136.972603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84136.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062222 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062222 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81509.803922 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81509.803922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72671.198630 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72671.198630 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 7316b9759..d7ab6a34e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23146500 # Number of ticks simulated -final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27167500 # Number of ticks simulated +final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95077 # Simulator instruction rate (inst/s) -host_op_rate 95070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145124480 # Simulator tick rate (ticks/s) -host_mem_usage 230244 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 49297 # Simulator instruction rate (inst/s) +host_op_rate 49293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88314525 # Simulator tick rate (ticks/s) +host_mem_usage 232472 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27904 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23113000 # Total gap between requests +system.physmem.totGap 27134000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2156250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation +system.physmem.totQLat 1645750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 4945.53 # Average queueing delay per request -system.physmem.avgBankLat 17723.62 # Average bank access latency per request +system.physmem.totBankLat 6311250 # Total cycles spent in bank access +system.physmem.avgQLat 3774.66 # Average queueing delay per request +system.physmem.avgBankLat 14475.34 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27669.15 # Average memory access latency -system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23250.00 # Average memory access latency +system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.42 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.52 # Average read queue length over time +system.physmem.busUtil 8.02 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.37 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 339 # Number of row buffer hits during reads +system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53011.47 # Average gap between requests +system.physmem.avgGap 62233.94 # Average gap between requests +system.membus.throughput 1024753842 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 871 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 27840 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.9 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -180,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46294 # number of cpu cycles simulated +system.cpu.numCycles 54336 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -202,12 +237,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 37.948762 # Percentage of cycles cpu is active +system.cpu.activity 32.332155 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -219,36 +254,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads -system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads +system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use +system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -261,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -279,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,36 +340,55 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -352,17 +406,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -385,17 +439,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,17 +469,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -437,27 +491,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -476,14 +530,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -502,19 +556,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -534,14 +588,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -550,14 +604,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3bff44537..3e2a9c814 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23775500 # Number of ticks simulated -final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 26399500 # Number of ticks simulated +final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12604 # Simulator instruction rate (inst/s) -host_op_rate 12604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20757401 # Simulator tick rate (ticks/s) -host_mem_usage 277264 # Number of bytes of host memory used -host_seconds 1.15 # Real time elapsed on the host +host_inst_rate 93938 # Simulator instruction rate (inst/s) +host_op_rate 93929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171756334 # Simulator tick rate (ticks/s) +host_mem_usage 234512 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 483 # Total number of read requests seen +system.physmem.num_reads::total 482 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 482 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30912 # Total number of bytes read from memory +system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30848 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23715500 # Total gap between requests +system.physmem.totGap 26239500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 483 # Categorize read packet sizes +system.physmem.readPktSize::6 482 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,157 +149,191 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 4632000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests -system.physmem.totBusLat 2415000 # Total cycles spent in databus access -system.physmem.totBankLat 8566250 # Total cycles spent in bank access -system.physmem.avgQLat 9590.06 # Average queueing delay per request -system.physmem.avgBankLat 17735.51 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation +system.physmem.totQLat 1765750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests +system.physmem.totBusLat 2410000 # Total cycles spent in databus access +system.physmem.totBankLat 6751250 # Total cycles spent in bank access +system.physmem.avgQLat 3663.38 # Average queueing delay per request +system.physmem.avgBankLat 14006.74 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32325.57 # Average memory access latency -system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22670.12 # Average memory access latency +system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.66 # Average read queue length over time +system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.41 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 369 # Number of row buffer hits during reads +system.physmem.readRowHits 430 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49100.41 # Average gap between requests -system.cpu.branchPred.lookups 6770 # Number of BP lookups -system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2447 # Number of BTB hits +system.physmem.avgGap 54438.80 # Average gap between requests +system.membus.throughput 1168506979 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 399 # Transaction distribution +system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.trans_dist::ReadExReq 83 # Transaction distribution +system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 964 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30848 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.0 # Layer utilization (%) +system.cpu.branchPred.lookups 6719 # Number of BP lookups +system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2433 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 47552 # number of cpu cycles simulated +system.cpu.numCycles 52800 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12221 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8387 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9300 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13601 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8395 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8002 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7953 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued @@ -328,84 +362,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21278 # Type of FU issued -system.cpu.iq.rate 0.447468 # Inst issue rate -system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21113 # Type of FU issued +system.cpu.iq.rate 0.399867 # Inst issue rate +system.cpu.iq.fu_busy_cnt 147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1136 # number of nop insts executed -system.cpu.iew.exec_refs 5272 # number of memory reference insts executed -system.cpu.iew.exec_branches 4246 # Number of branches executed -system.cpu.iew.exec_stores 2053 # Number of stores executed -system.cpu.iew.exec_rate 0.424882 # Inst execution rate -system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19647 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9208 # num instructions producing a value -system.cpu.iew.wb_consumers 11364 # num instructions consuming a value +system.cpu.iew.exec_nop 1134 # number of nop insts executed +system.cpu.iew.exec_refs 5224 # number of memory reference insts executed +system.cpu.iew.exec_branches 4238 # Number of branches executed +system.cpu.iew.exec_stores 2022 # Number of stores executed +system.cpu.iew.exec_rate 0.380076 # Inst execution rate +system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19513 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9111 # num instructions producing a value +system.cpu.iew.wb_consumers 11226 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back +system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -416,68 +450,87 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54359 # The number of ROB reads -system.cpu.rob.rob_writes 50813 # The number of ROB writes -system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54580 # The number of ROB reads +system.cpu.rob.rob_writes 50280 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads -system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32289 # number of integer regfile reads -system.cpu.int_regfile_writes 17967 # number of integer regfile writes -system.cpu.misc_regfile_reads 6962 # number of misc regfile reads +system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32029 # number of integer regfile reads +system.cpu.int_regfile_writes 17831 # number of integer regfile writes +system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use -system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use +system.cpu.icache.total_refs 4874 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits -system.cpu.icache.overall_hits::total 4850 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses -system.cpu.icache.overall_misses::total 491 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits +system.cpu.icache.overall_hits::total 4874 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses +system.cpu.icache.overall_misses::total 507 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30807500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30807500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30807500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30807500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30807500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30807500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5381 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5381 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5381 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5381 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5381 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5381 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094220 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094220 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094220 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094220 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094220 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094220 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60764.299803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60764.299803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60764.299803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60764.299803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -486,109 +539,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66016.320475 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.715806 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005000 # 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miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65344.776119 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71742.187500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66370.927318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68746.987952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68746.987952 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66780.082988 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66780.082988 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,128 +650,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use -system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 98.861742 # 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number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits +system.cpu.dcache.overall_hits::total 3995 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses -system.cpu.dcache.overall_misses::total 540 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -727,30 +780,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 9a48953c1..082962efb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30969 # Simulator instruction rate (inst/s) -host_op_rate 30968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15546804 # Simulator tick rate (ticks/s) -host_mem_usage 268968 # Number of bytes of host memory used -host_seconds 0.49 # Real time elapsed on the host +host_inst_rate 451796 # Simulator instruction rate (inst/s) +host_op_rate 451441 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226479305 # Simulator tick rate (ticks/s) +host_mem_usage 222832 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 1187861272 # Wr system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10676563321 # Throughput (bytes/s) +system.membus.data_through_bus 81270 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15225 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index d366271d4..b595d4238 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26295 # Simulator instruction rate (inst/s) -host_op_rate 26295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71739884 # Simulator tick rate (ticks/s) -host_mem_usage 277420 # Number of bytes of host memory used -host_seconds 0.58 # Real time elapsed on the host +host_inst_rate 479032 # Simulator instruction rate (inst/s) +host_op_rate 478642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1304958787 # Simulator tick rate (ticks/s) +host_mem_usage 231320 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 430090892 # In system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 643589248 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 331 # Transaction distribution +system.membus.trans_dist::ReadResp 331 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 832 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.1 # Layer utilization (%) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 82736 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -355,5 +370,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index f2f028686..6295c2feb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,87 +1,87 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105945500 # Number of ticks simulated -final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000110 # Number of seconds simulated +sim_ticks 110344500 # Number of ticks simulated +final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48441 # Simulator instruction rate (inst/s) -host_op_rate 48441 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4953275 # Simulator tick rate (ticks/s) -host_mem_usage 291288 # Number of bytes of host memory used -host_seconds 21.39 # Real time elapsed on the host -sim_insts 1036095 # Number of instructions simulated -sim_ops 1036095 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory +host_inst_rate 97195 # Simulator instruction rate (inst/s) +host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10306929 # Simulator tick rate (ticks/s) +host_mem_usage 249456 # Number of bytes of host memory used +host_seconds 10.71 # Real time elapsed on the host +sim_insts 1040548 # Number of instructions simulated +sim_ops 1040548 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 660 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 661 # Total number of read requests seen +system.physmem.num_reads::total 659 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 660 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42240 # Total number of bytes read from memory +system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 105917500 # Total gap between requests +system.physmem.totGap 110316500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 661 # Categorize read packet sizes +system.physmem.readPktSize::6 660 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -115,11 +115,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -179,336 +179,420 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 4080500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests -system.physmem.totBusLat 3305000 # Total cycles spent in databus access -system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6173.22 # Average queueing delay per request -system.physmem.avgBankLat 20136.16 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation +system.physmem.totQLat 3607500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests +system.physmem.totBusLat 3300000 # Total cycles spent in databus access +system.physmem.totBankLat 11013750 # Total cycles spent in bank access +system.physmem.avgQLat 5465.91 # Average queueing delay per request +system.physmem.avgBankLat 16687.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31309.38 # Average memory access latency -system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27153.41 # Average memory access latency +system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 465 # Number of row buffer hits during reads +system.physmem.readRowHits 532 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160238.28 # Average gap between requests -system.cpu0.branchPred.lookups 82343 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits +system.physmem.avgGap 167146.21 # Average gap between requests +system.membus.throughput 382221135 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 529 # Transaction distribution +system.membus.trans_dist::ReadResp 528 # Transaction distribution +system.membus.trans_dist::UpgradeReq 284 # Transaction distribution +system.membus.trans_dist::UpgradeResp 75 # Transaction distribution +system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 42176 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 5.7 # Layer utilization (%) +system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135488 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.cpu0.branchPred.lookups 82851 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211892 # number of cpu cycles simulated +system.cpu0.numCycles 220690 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued -system.cpu0.iq.rate 1.891860 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued +system.cpu0.iq.rate 1.829381 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75778 # number of nop insts executed -system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79388 # Number of branches executed -system.cpu0.iew.exec_stores 77294 # Number of stores executed -system.cpu0.iew.exec_rate 1.886744 # Inst execution rate -system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 236486 # num instructions producing a value -system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value +system.cpu0.iew.exec_nop 76372 # number of nop insts executed +system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79993 # Number of branches executed +system.cpu0.iew.exec_stores 77893 # Number of stores executed +system.cpu0.iew.exec_rate 1.824559 # Inst execution rate +system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238133 # num instructions producing a value +system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 467838 # Number of instructions committed -system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 471462 # Number of instructions committed +system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 228634 # Number of memory references committed -system.cpu0.commit.loads 152085 # Number of loads committed +system.cpu0.commit.refs 230446 # Number of memory references committed +system.cpu0.commit.loads 153293 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78436 # Number of branches committed +system.cpu0.commit.branches 79040 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 315322 # Number of committed integer instructions. +system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 670698 # The number of ROB reads -system.cpu0.rob.rob_writes 963274 # The number of ROB writes -system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 392586 # Number of Instructions Simulated -system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated -system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 715161 # number of integer regfile reads -system.cpu0.int_regfile_writes 322387 # number of integer regfile writes +system.cpu0.rob.rob_reads 676185 # The number of ROB reads +system.cpu0.rob.rob_writes 969800 # The number of ROB writes +system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 395606 # Number of Instructions Simulated +system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated +system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 720352 # number of integer regfile reads +system.cpu0.int_regfile_writes 324661 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 298 # number of replacements -system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use -system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks. +system.cpu0.icache.replacements 297 # number of replacements +system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use +system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits -system.cpu0.icache.overall_hits::total 5155 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses -system.cpu0.icache.overall_misses::total 746 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits +system.cpu0.icache.overall_hits::total 5081 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses +system.cpu0.icache.overall_misses::total 754 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.129220 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45945.623342 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 45945.623342 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 45945.623342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,583 +601,582 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 156 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 156 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 156 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21166500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21166500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21166500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21166500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21166500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21166500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099983 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.099983 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.099983 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35875.423729 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 166 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 166 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 166 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27004002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27004002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27004002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27004002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27004002 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27004002 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45925.173469 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use -system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 141.846177 # Cycle average of tags in use +system.cpu0.dcache.total_refs 155338 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 913.752941 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78219 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75963 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 141.846177 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.277043 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.277043 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78856 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78856 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76566 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76566 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # 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number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 406 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 406 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses -system.cpu0.dcache.overall_misses::total 1019 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 951 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 951 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 951 # number of overall misses +system.cpu0.dcache.overall_misses::total 951 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12750500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12750500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35495482 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35495482 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 416500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 416500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 48245982 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48245982 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48245982 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48245982 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79262 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79262 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77111 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77111 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 155201 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 155201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156373 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156373 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156373 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156373 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005122 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005122 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007068 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007068 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 56473 # Number of BP lookups -system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits +system.cpu1.branchPred.lookups 58259 # Number of BP lookups +system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 175078 # number of cpu cycles simulated +system.cpu1.numCycles 176870 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename +system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued -system.cpu1.iq.rate 1.510424 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued +system.cpu1.iq.rate 1.550964 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44011 # number of nop insts executed -system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed -system.cpu1.iew.exec_branches 53318 # Number of branches executed -system.cpu1.iew.exec_stores 43665 # Number of stores executed -system.cpu1.iew.exec_rate 1.503964 # Inst execution rate -system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 150856 # num instructions producing a value -system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value +system.cpu1.iew.exec_nop 45766 # number of nop insts executed +system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed +system.cpu1.iew.exec_branches 55097 # Number of branches executed +system.cpu1.iew.exec_stores 45923 # Number of stores executed +system.cpu1.iew.exec_rate 1.544264 # Inst execution rate +system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 157153 # num instructions producing a value +system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 300197 # Number of instructions committed -system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 311949 # Number of instructions committed +system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 131930 # Number of memory references committed -system.cpu1.commit.loads 88970 # Number of loads committed -system.cpu1.commit.membars 3544 # Number of memory barriers committed -system.cpu1.commit.branches 52469 # Number of branches committed +system.cpu1.commit.refs 138308 # Number of memory references committed +system.cpu1.commit.loads 93049 # Number of loads committed +system.cpu1.commit.membars 3038 # Number of memory barriers committed +system.cpu1.commit.branches 54264 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 206526 # Number of committed integer instructions. +system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 472949 # The number of ROB reads -system.cpu1.rob.rob_writes 627337 # The number of ROB writes -system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 253388 # Number of Instructions Simulated -system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated -system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 460976 # number of integer regfile reads -system.cpu1.int_regfile_writes 214498 # number of integer regfile writes +system.cpu1.rob.rob_reads 484071 # The number of ROB reads +system.cpu1.rob.rob_writes 650455 # The number of ROB writes +system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 263856 # Number of Instructions Simulated +system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated +system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 479823 # number of integer regfile reads +system.cpu1.int_regfile_writes 223101 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads +system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use -system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use +system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits -system.cpu1.icache.overall_hits::total 16176 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses -system.cpu1.icache.overall_misses::total 484 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits +system.cpu1.icache.overall_hits::total 15036 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses +system.cpu1.icache.overall_misses::total 487 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 59 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8244000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8244000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8244000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8244000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025510 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.025510 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.025510 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19397.647059 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # 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Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.052885 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 50842 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 50842 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 42756 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 42756 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 93598 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 93598 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 93598 # number of overall hits -system.cpu1.dcache.overall_hits::total 93598 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits +system.cpu1.dcache.overall_hits::total 97736 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 557 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 557 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 557 # number of overall misses -system.cpu1.dcache.overall_misses::total 557 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8012000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8012000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3190500 # 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number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1102,473 +1185,473 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 264 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 48435 # Number of BP lookups -system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits +system.cpu2.branchPred.lookups 40256 # Number of BP lookups +system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 174747 # number of cpu cycles simulated +system.cpu2.numCycles 176505 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename +system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle +system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued -system.cpu2.iq.rate 1.246190 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued +system.cpu2.iq.rate 0.975530 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35937 # number of nop insts executed -system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45106 # Number of branches executed -system.cpu2.iew.exec_stores 32695 # Number of stores executed -system.cpu2.iew.exec_rate 1.239535 # Inst execution rate -system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 120625 # num instructions producing a value -system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value +system.cpu2.iew.exec_nop 27820 # number of nop insts executed +system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed +system.cpu2.iew.exec_branches 36982 # Number of branches executed +system.cpu2.iew.exec_stores 22143 # Number of stores executed +system.cpu2.iew.exec_rate 0.969321 # Inst execution rate +system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 91387 # num instructions producing a value +system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 245558 # Number of instructions committed -system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 192088 # Number of instructions committed +system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 101851 # Number of memory references committed -system.cpu2.commit.loads 69824 # Number of loads committed -system.cpu2.commit.membars 6301 # Number of memory barriers committed -system.cpu2.commit.branches 44289 # Number of branches committed +system.cpu2.commit.refs 72624 # Number of memory references committed +system.cpu2.commit.loads 51171 # Number of loads committed +system.cpu2.commit.membars 8798 # Number of memory barriers committed +system.cpu2.commit.branches 36206 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 168258 # Number of committed integer instructions. +system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 421045 # The number of ROB reads -system.cpu2.rob.rob_writes 518771 # The number of ROB writes -system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 204183 # Number of Instructions Simulated -system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated -system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370277 # number of integer regfile reads -system.cpu2.int_regfile_writes 173276 # number of integer regfile writes +system.cpu2.rob.rob_reads 367870 # The number of ROB reads +system.cpu2.rob.rob_writes 411061 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 156297 # Number of Instructions Simulated +system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated +system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 282509 # number of integer regfile reads +system.cpu2.int_regfile_writes 133289 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads +system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use -system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks. +system.cpu2.icache.replacements 318 # number of replacements +system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use +system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits -system.cpu2.icache.overall_hits::total 21789 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses -system.cpu2.icache.overall_misses::total 478 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 22267 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 22267 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 22267 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021467 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.021467 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021467 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.021467 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021467 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.021467 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14296.025105 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14296.025105 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits +system.cpu2.icache.overall_hits::total 26999 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses +system.cpu2.icache.overall_misses::total 474 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5518500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5518500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5518500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5518500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5518500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5518500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.019311 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.019311 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12833.720930 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 428 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 428 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 428 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5331008 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5331008 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5331008 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5331008 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5331008 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5331008 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.015579 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.015579 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.015579 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12455.626168 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.660288 # Cycle average of tags in use -system.cpu2.dcache.total_refs 38032 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1358.285714 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 23.628047 # Cycle average of tags in use +system.cpu2.dcache.total_refs 27574 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 950.827586 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.660288 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050118 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050118 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42624 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42624 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 31820 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 31820 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 74444 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 74444 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 74444 # number of overall hits -system.cpu2.dcache.overall_hits::total 74444 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 407 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu2.dcache.occ_blocks::cpu2.data 23.628047 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.046149 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.046149 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 34611 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 34611 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 21248 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 21248 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 55859 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 55859 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 55859 # number of overall hits +system.cpu2.dcache.overall_hits::total 55859 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 317 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 317 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 541 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 541 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 541 # number of overall misses -system.cpu2.dcache.overall_misses::total 541 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5612500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5612500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2750000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 572000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 572000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8362500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8362500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8362500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8362500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 43031 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 43031 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 31954 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 31954 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 74985 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 74985 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 74985 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 74985 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009458 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009458 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004194 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004194 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007215 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007215 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007215 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007215 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13789.926290 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 13789.926290 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20522.388060 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20522.388060 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9862.068966 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9862.068966 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15457.486137 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15457.486137 # average overall miss latency +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 451 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 451 # number of overall misses +system.cpu2.dcache.overall_misses::total 451 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3712500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3712500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2774500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2774500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 533000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 533000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 6487000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 6487000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 6487000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 6487000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 34928 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 34928 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 21382 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 21382 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 56310 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 56310 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 56310 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 56310 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009076 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009076 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006267 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006267 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.760563 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.760563 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008009 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008009 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008009 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008009 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 11711.356467 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 11711.356467 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20705.223881 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20705.223881 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9870.370370 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9870.370370 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14383.592018 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14383.592018 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1577,365 +1660,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 45379 # Number of BP lookups -system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits +system.cpu3.branchPred.lookups 52069 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 174437 # number of cpu cycles simulated +system.cpu3.numCycles 176161 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued -system.cpu3.iq.rate 1.148908 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued +system.cpu3.iq.rate 1.349169 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32807 # number of nop insts executed -system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41971 # Number of branches executed -system.cpu3.iew.exec_stores 28736 # Number of stores executed -system.cpu3.iew.exec_rate 1.142235 # Inst execution rate -system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 109565 # num instructions producing a value -system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value +system.cpu3.iew.exec_nop 39523 # number of nop insts executed +system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed +system.cpu3.iew.exec_branches 48746 # Number of branches executed +system.cpu3.iew.exec_stores 37155 # Number of stores executed +system.cpu3.iew.exec_rate 1.342386 # Inst execution rate +system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 133214 # num instructions producing a value +system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 225028 # Number of instructions committed -system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 268955 # Number of instructions committed +system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 90734 # Number of memory references committed -system.cpu3.commit.loads 62697 # Number of loads committed -system.cpu3.commit.membars 7153 # Number of memory barriers committed -system.cpu3.commit.branches 41151 # Number of branches committed +system.cpu3.commit.refs 114381 # Number of memory references committed +system.cpu3.commit.loads 77904 # Number of loads committed +system.cpu3.commit.membars 5468 # Number of memory barriers committed +system.cpu3.commit.branches 47910 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154003 # Number of committed integer instructions. +system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 400338 # The number of ROB reads -system.cpu3.rob.rob_writes 477767 # The number of ROB writes -system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 185938 # Number of Instructions Simulated -system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated -system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 337021 # number of integer regfile reads -system.cpu3.int_regfile_writes 158120 # number of integer regfile writes +system.cpu3.rob.rob_reads 445085 # The number of ROB reads +system.cpu3.rob.rob_writes 565364 # The number of ROB writes +system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 224789 # Number of Instructions Simulated +system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated +system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 408025 # number of integer regfile reads +system.cpu3.int_regfile_writes 190344 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads +system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use -system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks. +system.cpu3.icache.replacements 319 # number of replacements +system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use +system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23677 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23677 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23677 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23677 # number of overall hits -system.cpu3.icache.overall_hits::total 23677 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses -system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6195500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6195500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6195500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24152 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24152 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24152 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.019667 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.019667 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.019667 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.019667 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13043.157895 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13043.157895 # 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average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12491.176471 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19630.434783 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19630.434783 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9456.896552 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9456.896552 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14552.301255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14552.301255 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2052,288 +2135,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 258 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 258 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 290 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 290 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 290 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1447000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1447000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1250000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1250000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 487500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 487500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2697000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2697000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2697000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2697000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004086 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004086 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003790 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003790 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003964 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003964 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8877.300613 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8877.300613 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 62.204312 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.605545 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 4.564656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.760691 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.668516 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.722445 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000902 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000949 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000070 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61550.675676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 45b73a0af..3469c3943 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205117 # Simulator instruction rate (inst/s) -host_op_rate 205116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26560282 # Simulator tick rate (ticks/s) -host_mem_usage 1206900 # Number of bytes of host memory used -host_seconds 3.30 # Real time elapsed on the host +host_inst_rate 1256528 # Simulator instruction rate (inst/s) +host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162691956 # Simulator tick rate (ticks/s) +host_mem_usage 1160656 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -57,6 +57,12 @@ system.physmem.bw_total::cpu2.data 9486130 # To system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 407903588 # Throughput (bytes/s) +system.membus.data_through_bus 35776 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 166080 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index f34b8a118..a78d037d9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,193 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262970500 # Number of ticks simulated -final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262793500 # Number of ticks simulated +final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110323 # Simulator instruction rate (inst/s) -host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43749084 # Simulator tick rate (ticks/s) -host_mem_usage 287188 # Number of bytes of host memory used -host_seconds 6.01 # Real time elapsed on the host -sim_insts 663135 # Number of instructions simulated -sim_ops 663135 # Number of ops (including micro ops) simulated +host_inst_rate 1490059 # Simulator instruction rate (inst/s) +host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 590046557 # Simulator tick rate (ticks/s) +host_mem_usage 244196 # Number of bytes of host memory used +host_seconds 0.45 # Real time elapsed on the host +sim_insts 663601 # Number of instructions simulated +sim_ops 663601 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 139303293 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 430 # Transaction distribution +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36608 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 2.1 # Layer utilization (%) +system.toL2Bus.throughput 646591335 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 116032 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525941 # number of cpu cycles simulated +system.cpu0.numCycles 525587 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158580 # Number of instructions committed -system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses +system.cpu0.committedInsts 158574 # Number of instructions committed +system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109212 # number of integer instructions +system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109208 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 74024 # number of memory refs -system.cpu0.num_load_insts 49009 # Number of load instructions -system.cpu0.num_store_insts 25015 # Number of store instructions +system.cpu0.num_mem_refs 74021 # number of memory refs +system.cpu0.num_load_insts 49007 # Number of load instructions +system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525941 # Number of busy cycles +system.cpu0.num_busy_cycles 525587 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use -system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use +system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits -system.cpu0.icache.overall_hits::total 158176 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits +system.cpu0.icache.overall_hits::total 158170 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,94 +202,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17209000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17209000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36850.107066 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73608 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73608 # number of overall hits -system.cpu0.dcache.overall_hits::total 73608 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 171 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 171 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 184 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 184 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits +system.cpu0.dcache.overall_hits::total 73607 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses -system.cpu0.dcache.overall_misses::total 355 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses +system.cpu0.dcache.overall_misses::total 353 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,114 +300,114 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525940 # number of cpu cycles simulated +system.cpu1.numCycles 525587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 166746 # Number of instructions committed -system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses +system.cpu1.committedInsts 173389 # Number of instructions committed +system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107707 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110403 # number of integer instructions +system.cpu1.num_conditional_control_insts 36848 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107707 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written +system.cpu1.num_int_register_reads 245634 # number of times the integer registers were read +system.cpu1.num_int_register_writes 91167 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54388 # number of memory refs -system.cpu1.num_load_insts 40871 # Number of load instructions -system.cpu1.num_store_insts 13517 # Number of store instructions -system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles -system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles +system.cpu1.num_mem_refs 47028 # number of memory refs +system.cpu1.num_load_insts 39502 # Number of load instructions +system.cpu1.num_store_insts 7526 # Number of store instructions +system.cpu1.num_idle_cycles 69346.001736 # Number of idle cycles +system.cpu1.num_busy_cycles 456240.998264 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868060 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131940 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use -system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.017443 # Cycle average of tags in use +system.cpu1.icache.total_refs 173056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits -system.cpu1.icache.overall_hits::total 166413 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.017443 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 173056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 173056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 173056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 173056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 173056 # number of overall hits +system.cpu1.icache.overall_hits::total 173056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7565000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7565000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7565000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7565000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 166779 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 166779 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 166779 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 166779 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 166779 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 166779 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002195 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20669.398907 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7542000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7542000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7542000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7542000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7542000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7542000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173422 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173422 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +422,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6833000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6833000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6833000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6833000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6833000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6833000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002195 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002195 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002195 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18669.398907 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806511 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806511 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806511 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6806511 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806511 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6806511 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002110 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002110 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.686467 # Cycle average of tags in use -system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.692937 # Cycle average of tags in use +system.cpu1.dcache.total_refs 17380 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.686467 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054075 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054075 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40710 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40710 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13344 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13344 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # 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number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4916500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40863 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40863 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13450 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13450 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 278 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 278 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 278 # number of overall misses +system.cpu1.dcache.overall_misses::total 278 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3331000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3331000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2174000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2174000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 282000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 282000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5505000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5505000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39494 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39494 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7440 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7440 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 84 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 84 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 46934 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 46934 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 46934 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 46934 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004355 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004355 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014247 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.014247 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.773810 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.773810 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005923 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005923 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005923 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005923 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4338.461538 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +518,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525941 # number of cpu cycles simulated +system.cpu2.numCycles 525587 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 169995 # Number of instructions committed -system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses +system.cpu2.committedInsts 164870 # Number of instructions committed +system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110917 # number of integer instructions +system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112982 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read -system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read +system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 53535 # number of memory refs -system.cpu2.num_load_insts 41127 # Number of load instructions -system.cpu2.num_store_insts 12408 # Number of store instructions -system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles -system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles +system.cpu2.num_mem_refs 59198 # number of memory refs +system.cpu2.num_load_insts 42166 # Number of load instructions +system.cpu2.num_store_insts 17032 # Number of store instructions +system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles +system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use -system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use +system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits -system.cpu2.icache.overall_hits::total 169662 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 67.624903 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 164537 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164537 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164537 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164537 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164537 # number of overall hits +system.cpu2.icache.overall_hits::total 164537 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5281000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5281000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5281000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5281000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5281000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5281000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 170028 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 170028 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 170028 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 170028 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 170028 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 170028 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002153 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002153 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002153 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14428.961749 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14428.961749 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14428.961749 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14428.961749 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5251500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5251500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5251500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5251500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5251500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164903 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164903 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 164903 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 164903 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 164903 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 164903 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002219 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002219 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002219 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002219 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002219 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002219 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14348.360656 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14348.360656 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14348.360656 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14348.360656 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14348.360656 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +640,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4549000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4549000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4549000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4549000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4549000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4549000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12428.961749 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4514513 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4514513 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4514513 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4514513 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4514513 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4514513 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002219 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002219 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002219 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002219 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12334.734973 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12334.734973 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12334.734973 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.908378 # Cycle average of tags in use -system.cpu2.dcache.total_refs 27066 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.764140 # Cycle average of tags in use +system.cpu2.dcache.total_refs 36333 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 933.310345 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1252.862069 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.908378 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050602 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050602 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40963 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40963 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 12235 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 12235 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 53198 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 53198 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 53198 # number of overall hits -system.cpu2.dcache.overall_hits::total 53198 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 157 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses -system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2754500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2754500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1914500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1914500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 286000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 286000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4669000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4669000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4669000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4669000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41120 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41120 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 12340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 12340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 53460 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 53460 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 53460 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 53460 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003818 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003818 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008509 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.008509 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.772727 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.772727 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004901 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004901 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004901 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004901 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17544.585987 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17544.585987 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18233.333333 # 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number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42000 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 16859 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 16859 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58859 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58859 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58859 # number of overall hits +system.cpu2.dcache.overall_hits::total 58859 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 158 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 158 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2136000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2136000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1926500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1926500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 214000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 214000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4062500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4062500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4062500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4062500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42158 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42158 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16968 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16968 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 59126 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59126 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59126 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59126 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003748 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003748 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006424 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006424 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.838710 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.838710 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004516 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004516 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004516 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004516 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13518.987342 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13518.987342 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17674.311927 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17674.311927 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4115.384615 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4115.384615 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15215.355805 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15215.355805 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +736,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2440500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2440500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 184000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 184000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4145000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4145000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4145000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4145000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003818 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008509 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008509 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.772727 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 158 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814014 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1814014 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1708500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1708500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 110000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 110000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3522514 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3522514 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3522514 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3522514 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003748 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003748 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006424 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.838710 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.838710 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004516 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004516 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2115.384615 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2115.384615 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525940 # number of cpu cycles simulated +system.cpu3.numCycles 525586 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167814 # Number of instructions committed -system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses +system.cpu3.committedInsts 166768 # Number of instructions committed +system.cpu3.committedOps 166768 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112266 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111369 # number of integer instructions +system.cpu3.num_conditional_control_insts 31259 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112266 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 278793 # number of times the integer registers were read -system.cpu3.num_int_register_writes 105918 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 55316 # number of memory refs -system.cpu3.num_load_insts 41342 # Number of load instructions -system.cpu3.num_store_insts 13974 # Number of store instructions -system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles -system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles +system.cpu3.num_mem_refs 57176 # number of memory refs +system.cpu3.num_load_insts 41805 # Number of load instructions +system.cpu3.num_store_insts 15371 # Number of store instructions +system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles +system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use -system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use +system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167480 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167480 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167480 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167480 # number of overall hits -system.cpu3.icache.overall_hits::total 167480 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166434 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166434 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166434 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166434 # number of overall hits +system.cpu3.icache.overall_hits::total 166434 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5162000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5162000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5149000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5149000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5149000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5149000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5149000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # 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Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050668 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41638 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41638 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15196 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15196 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 56834 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56834 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56834 # number of overall hits +system.cpu3.dcache.overall_hits::total 56834 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 159 # 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number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57102 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57102 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57102 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57102 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003804 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007122 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828125 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.828125 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004693 # 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average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,70 +954,70 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 171 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # 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Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.123911 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.843759 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 1.030265 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.831019 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000789 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.005326 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits @@ -998,10 +1061,10 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses @@ -1025,38 +1088,38 @@ system.l2c.overall_misses::cpu2.data 16 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 14926500 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 385500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 835500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30832000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3437500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1219000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 598000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 851000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 834499 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30956999 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -1069,10 +1132,10 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1109,7 +1172,7 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1133,38 +1196,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.640000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52348.484848 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 47375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 50000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 42833.333333 # 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mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40236.368421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index fa768666b..810fd780f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.007257 # Nu sim_ticks 7257449 # Number of ticks simulated final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 64474 # Simulator tick rate (ticks/s) -host_mem_usage 299312 # Number of bytes of host memory used -host_seconds 112.56 # Real time elapsed on the host +host_tick_rate 119266 # Simulator tick rate (ticks/s) +host_mem_usage 252632 # Number of bytes of host memory used +host_seconds 60.85 # Real time elapsed on the host +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 76641 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76643 # Number of cache demand accesses diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 3d47d6198..f7f66d759 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.007481 # Nu sim_ticks 7481441 # Number of ticks simulated final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 40613 # Simulator tick rate (ticks/s) -host_mem_usage 299464 # Number of bytes of host memory used -host_seconds 184.21 # Real time elapsed on the host +host_tick_rate 59106 # Simulator tick rate (ticks/s) +host_mem_usage 252804 # Number of bytes of host memory used +host_seconds 126.58 # Real time elapsed on the host +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) system.ruby.l1_cntrl4.L1Dcache.demand_hits 21 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 77428 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77449 # Number of cache demand accesses diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index a0899442c..11bfc67d2 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.006151 # Nu sim_ticks 6151475 # Number of ticks simulated final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 46771 # Simulator tick rate (ticks/s) -host_mem_usage 298400 # Number of bytes of host memory used -host_seconds 131.52 # Real time elapsed on the host +host_tick_rate 50702 # Simulator tick rate (ticks/s) +host_mem_usage 252748 # Number of bytes of host memory used +host_seconds 121.33 # Real time elapsed on the host +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 76947 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76967 # Number of cache demand accesses diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 781075885..decabd123 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.005796 # Nu sim_ticks 5795833 # Number of ticks simulated final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 45179 # Simulator tick rate (ticks/s) -host_mem_usage 298344 # Number of bytes of host memory used -host_seconds 128.29 # Real time elapsed on the host +host_tick_rate 39688 # Simulator tick rate (ticks/s) +host_mem_usage 251648 # Number of bytes of host memory used +host_seconds 146.03 # Real time elapsed on the host +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 77212 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77226 # Number of cache demand accesses diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index af88cf774..007aee21a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.008665 # Nu sim_ticks 8664886 # Number of ticks simulated final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 174865 # Simulator tick rate (ticks/s) -host_mem_usage 297912 # Number of bytes of host memory used -host_seconds 49.55 # Real time elapsed on the host +host_tick_rate 321644 # Simulator tick rate (ticks/s) +host_mem_usage 252216 # Number of bytes of host memory used +host_seconds 26.94 # Real time elapsed on the host +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.cacheMemory.demand_misses 77331 # Number of cache demand misses system.ruby.l1_cntrl4.cacheMemory.demand_accesses 77331 # Number of cache demand accesses diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 5ed14465a..e56d497e2 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,656 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000761 # Number of seconds simulated -sim_ticks 761435500 # Number of ticks simulated -final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000650 # Number of seconds simulated +sim_ticks 649827000 # Number of ticks simulated +final_tick 649827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 112752764 # Simulator tick rate (ticks/s) -host_mem_usage 399024 # Number of bytes of host memory used -host_seconds 6.75 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 92287 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 88521 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 93126 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 92216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 93858 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 91205 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 94911 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 89917 # Number of bytes read from this memory -system.physmem.bytes_read::total 736041 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 486336 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5427 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5222 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5377 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5288 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5289 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5340 # Number of bytes written to this memory -system.physmem.bytes_written::total 529238 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11206 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11261 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11258 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11247 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11104 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89661 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7599 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5427 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5222 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5288 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5289 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5340 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50501 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 121201336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124647459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 118088794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 966649178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 638709385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7127327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7061662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6944777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7158847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7233705 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7013069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 695052962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 638709385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 128328663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 123113514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 129364864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 128052869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 130210635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 126939183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 131881164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125101864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1661702140 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15611 # number of replacements -system.l2c.tagsinuse 803.524746 # Cycle average of tags in use -system.l2c.total_refs 152738 # Total number of references to valid blocks. -system.l2c.sampled_refs 16409 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.308185 # Average number of references to valid blocks. +host_tick_rate 87337651 # Simulator tick rate (ticks/s) +host_mem_usage 355516 # Number of bytes of host memory used +host_seconds 7.44 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 81682 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82403 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82634 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80397 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83903 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 81493 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 81053 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80348 # Number of bytes read from this memory +system.physmem.bytes_read::total 653913 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 411392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5164 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5249 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5478 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5343 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5429 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5399 # Number of bytes written to this memory +system.physmem.bytes_written::total 454226 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10859 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87795 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6428 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5164 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5249 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5343 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5429 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5380 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5399 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49262 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 125698070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 126807596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 127163076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 123720621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 129115903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 125407224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 124730120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 123645216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1006287827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 633079266 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 8297593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 7946730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 8077534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 8429936 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 8222188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 8354531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 8279127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 8308365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 698995271 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 633079266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 133995663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 134754327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 135240610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 132150557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 137338092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 133761755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 133009247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131953581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1705283098 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1705280021 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 84626 # Transaction distribution +system.membus.trans_dist::ReadResp 84624 # Transaction distribution +system.membus.trans_dist::WriteReq 42834 # Transaction distribution +system.membus.trans_dist::WriteResp 42832 # Transaction distribution +system.membus.trans_dist::Writeback 6428 # Transaction distribution +system.membus.trans_dist::UpgradeReq 56782 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46322 # Transaction distribution +system.membus.trans_dist::ReadExReq 48493 # Transaction distribution +system.membus.trans_dist::ReadExResp 3169 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 416110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 416110 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 1108137 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1108137 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1108137 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 287607668 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 44.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 310731500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 47.8 # Layer utilization (%) +system.l2c.replacements 13443 # number of replacements +system.l2c.tagsinuse 785.847638 # Cycle average of tags in use +system.l2c.total_refs 148477 # Total number of references to valid blocks. +system.l2c.sampled_refs 14254 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.416515 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 740.398086 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.878873 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.659983 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 8.123766 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.474129 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 8.226019 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.053219 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.543884 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.166787 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.723045 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007694 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007480 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007933 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007299 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.008033 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007864 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006999 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784692 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10939 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10998 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10816 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 11039 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10812 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 11089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 11073 # number of ReadReq hits -system.l2c.ReadReq_hits::total 87666 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77271 # number of Writeback hits -system.l2c.Writeback_hits::total 77271 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 381 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 354 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 406 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2895 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2136 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2005 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1979 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2046 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2088 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16315 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12878 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 13075 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 13003 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12812 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 13018 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12858 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13176 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13161 # number of demand (read+write) hits -system.l2c.demand_hits::total 103981 # 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number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 820 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6744 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1862 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1924 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1971 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1858 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1882 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1937 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1981 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15347 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4273 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4400 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4210 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34363 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5159 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5073 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5272 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses -system.l2c.demand_misses::total 41107 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 52891428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 49101459 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 404015481 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54966909 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 55263407 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 54925394 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53857894 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54541411 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 53722422 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 55425398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 56851911 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 439554746 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 229863626 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 234328104 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 229945624 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 229282087 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 236284615 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 232406616 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 230024647 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 226955142 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1849090461 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 280699572 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 282743032 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 281424044 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 277864023 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 288925045 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 282477550 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 282916075 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 276056601 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2253105942 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 280699572 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 282743032 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 281424044 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 277864023 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 288925045 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 282477550 # 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number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77271 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2209 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2281 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2352 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2208 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2228 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2335 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18242 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6251 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6489 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6273 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6379 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6366 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6369 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6298 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50678 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18234 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18129 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17885 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18290 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18027 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18339 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18191 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 145088 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18234 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18129 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17885 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18290 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18027 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18339 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18191 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 145088 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071708 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.068625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.072368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.070151 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.073210 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.072807 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.073601 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.068948 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.071433 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.842915 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.843490 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.838010 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.841486 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.845144 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.844704 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.826718 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.848394 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.841300 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.683571 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.670828 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.680376 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.680793 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.689763 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.678605 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.672319 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.668466 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.678065 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.284277 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.282751 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.283646 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288245 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.286737 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.281531 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.276510 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.283325 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.284277 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.282751 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.283646 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288245 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.286737 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.281531 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.276510 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.283325 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60375.232779 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 60068.148883 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59998.158508 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59536.686275 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60367.465596 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58976.365135 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 60035.673099 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59879.828049 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59907.396352 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29520.359291 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28723.184511 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27866.765094 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28987.025834 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28230.543996 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28545.388948 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28614.041301 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28698.592125 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28641.085945 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53794.436227 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.404549 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53876.669166 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.015739 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53701.048864 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53797.827778 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53718.974078 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53908.584798 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53810.507261 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54877.726686 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54805.782516 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54901.296137 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54773.117090 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54803.688354 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54648.394274 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54796.838079 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54882.028032 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54810.760746 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54877.726686 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54805.782516 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54901.296137 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54773.117090 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54803.688354 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54648.394274 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54796.838079 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54882.028032 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54810.760746 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11382 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 727.764026 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.053915 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.581472 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.416719 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.244884 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.857651 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.082573 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 6.903381 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 6.943017 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.710707 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.006889 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007404 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007243 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.006917 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.006742 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.006780 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.767429 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10664 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10479 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10758 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10530 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10691 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10867 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85444 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 73993 # number of Writeback hits +system.l2c.Writeback_hits::total 73993 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 310 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 313 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 344 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 344 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2664 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1874 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1837 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1846 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1867 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1842 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14873 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12353 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12678 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12558 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12709 # number of demand (read+write) hits +system.l2c.demand_hits::total 100317 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12485 # number of overall hits +system.l2c.overall_hits::cpu1 12353 # number of overall hits +system.l2c.overall_hits::cpu2 12678 # number of overall hits +system.l2c.overall_hits::cpu3 12604 # number of overall hits +system.l2c.overall_hits::cpu4 12514 # number of overall hits +system.l2c.overall_hits::cpu5 12416 # number of overall hits +system.l2c.overall_hits::cpu6 12558 # number of overall hits +system.l2c.overall_hits::cpu7 12709 # number of overall hits +system.l2c.overall_hits::total 100317 # number of overall hits +system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 740 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 751 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 714 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 782 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 720 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 737 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 688 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5877 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1883 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1791 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1910 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1895 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1890 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15128 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4230 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4311 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4330 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4249 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4380 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4201 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4403 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34390 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 4975 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5051 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5081 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 4963 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5068 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5100 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4938 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5091 # number of demand (read+write) misses +system.l2c.demand_misses::total 40267 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 4975 # number of overall misses +system.l2c.overall_misses::cpu1 5051 # number of overall misses +system.l2c.overall_misses::cpu2 5081 # number of overall misses +system.l2c.overall_misses::cpu3 4963 # number of overall misses +system.l2c.overall_misses::cpu4 5068 # number of overall misses +system.l2c.overall_misses::cpu5 5100 # number of overall misses +system.l2c.overall_misses::cpu6 4938 # number of overall misses +system.l2c.overall_misses::cpu7 5091 # number of overall misses +system.l2c.overall_misses::total 40267 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 46342500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 45732000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 46640500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 44232499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 48395500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 43931000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 45019000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 42654500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 362947499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57720500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 54568500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 56051000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 51373500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 56366000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 55004000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55764000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54598000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 441445500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 227493499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 232269500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 233545000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 229482499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 231206500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 236797000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 226713000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 237470499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1854977497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 273835999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 278001500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 280185500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 273714998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 279602000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 280728000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 271732000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 280124999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2217924996 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 273835999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 278001500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 280185500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 273714998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 279602000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 280728000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 271732000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 280124999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2217924996 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11409 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11219 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11592 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11472 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11396 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11250 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91321 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 73993 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 73993 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2350 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2192 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2101 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2220 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2239 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2234 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6051 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6185 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6167 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6095 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6186 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6266 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6068 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49263 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17460 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17404 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17567 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17496 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17800 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 140584 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17460 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17404 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17567 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17582 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17496 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17800 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 140584 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.065299 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065960 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064786 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.062238 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068621 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.064491 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.059541 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.064355 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.845532 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.848198 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.850821 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.852451 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.859009 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.854204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.846360 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.846016 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.850270 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.699058 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.697009 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.702124 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.697129 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.692855 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.699011 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.692320 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.705044 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.698090 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.284937 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.290221 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286108 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.282518 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291162 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.282236 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.286011 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286427 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.284937 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.290221 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286108 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.282518 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291162 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.282236 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.286011 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286427 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 62204.697987 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61800 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62104.527297 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61950.278711 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61886.828645 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61015.277778 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61084.124830 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61997.819767 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61757.273949 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29049.068948 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28979.553903 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30054.155496 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 28684.254606 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29557.420031 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28797.905759 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29426.912929 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28887.830688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29180.691433 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53780.969031 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.334493 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53936.489607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54008.590021 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53944.587028 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54063.242009 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53966.436563 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53933.794913 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53939.444519 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55042.411859 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55038.903187 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55143.770911 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55151.117872 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55170.086819 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55044.705882 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55028.756582 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55023.570811 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55080.462811 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55042.411859 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55038.903187 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55143.770911 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55151.117872 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55170.086819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55044.705882 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55028.756582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55023.570811 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55080.462811 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 13397 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1550 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1907 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.343226 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.025170 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7599 # number of writebacks -system.l2c.writebacks::total 7599 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 9 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6428 # number of writebacks +system.l2c.writebacks::total 6428 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 25 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 833 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 800 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 853 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 808 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 867 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 841 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 874 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 817 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6693 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1862 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1924 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1858 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1932 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1881 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1937 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1981 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15345 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4271 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4264 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4253 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4393 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4317 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4280 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4210 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34338 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5150 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5117 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5061 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5260 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5154 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5027 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 41031 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5150 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5117 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5061 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5260 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5154 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5027 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 41031 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 40464447 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 38550929 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 41027920 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 38515937 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 41941930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 39649436 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 41931428 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 39012959 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 321094986 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76446342 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78808343 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80788312 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76138817 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79209815 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77051840 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 79478835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81341333 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 629263637 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 178032127 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 181508104 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 178129124 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 177575588 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 182792115 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 179941616 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 178029147 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 175952642 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1431960463 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218496574 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 220059033 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 219157044 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 216091525 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 224734045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 219591052 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 219960575 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214965601 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1753055449 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218496574 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 220059033 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 219157044 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 216091525 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 224734045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 219591052 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 219960575 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214965601 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1753055449 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408840154 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409932127 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406697168 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412407125 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 410618544 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 412439590 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408986543 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406399119 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3276320370 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229120490 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 221422480 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227576980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223709488 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225472990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232298486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233243987 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227452978 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1820297879 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 637960644 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 631354607 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634274148 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 636116613 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 636091534 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 644738076 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 642230530 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 633852097 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5096618249 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070942 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068114 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.071947 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069464 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.072790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072121 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073016 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.068696 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.070893 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842915 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.843490 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.837585 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841486 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.845144 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844255 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.826718 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.848394 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.841191 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.683251 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.670365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679739 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680154 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.688666 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.678134 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.672005 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.668466 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.677572 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.282801 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.282801 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48576.767107 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48188.661250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48098.382181 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47668.238861 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48375.928489 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47145.583829 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 47976.462243 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47751.479804 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47974.747647 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.037594 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40960.677235 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41009.295431 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40978.911195 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40998.869048 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40963.232323 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41031.923077 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41060.743564 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41007.731313 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41683.944509 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41726.000920 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41775.122889 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41753.018575 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41609.860005 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41682.097753 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41595.595093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41793.976722 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41701.918079 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 28 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 739 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 734 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 745 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 710 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 775 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 713 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 727 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 683 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5826 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1882 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1865 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1791 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1894 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1889 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15124 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4226 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4305 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4324 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4247 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4284 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4198 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4400 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34362 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 4965 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5039 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5069 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4957 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5059 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4925 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40188 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 4965 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5039 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5069 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4957 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5059 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4925 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40188 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 37216000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 36653500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37301500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 35511499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 38736500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34925000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 35756000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 34110500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 290210499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81531000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 77219000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76527500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 73571500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78291500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 78487500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77899500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77615500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 621143000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 176232999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 179835500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 181021500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 177936499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 179280500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 183709500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 175748500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 184108999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1437873997 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 213448999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 216489000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 218323000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 213447998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 218017000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 218634500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 211504500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 218219499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1728084496 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 213448999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 216489000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 218323000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 213447998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 218017000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 218634500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 211504500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 218219499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1728084496 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 406261500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408851000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 410764500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 410830500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407460500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 403658000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409230500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 404004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3261061000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227401000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 218592500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221548500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 231869500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226934000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230334000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226902000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 228628000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1812209500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 633662500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 627443500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 632313000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 642700000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634394500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 633992000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 636132500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 632632500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5073270500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064773 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.065425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064268 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061890 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.068006 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063378 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063616 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059109 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.063797 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.845106 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850821 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.852451 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.859009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.845913 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.845568 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.850045 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.698397 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.696039 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.701151 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.696801 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.692532 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698691 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691826 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.704564 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.697521 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285865 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50359.945873 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49936.648501 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50069.127517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50016.195775 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49982.580645 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48983.169705 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49182.943604 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49942.166911 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49812.993306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41052.870091 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41030.286929 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41033.512064 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41078.447795 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41054.798112 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41092.931937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41129.619852 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41088.141874 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41070.021158 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41702.082111 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41773.635308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41864.361702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41896.985872 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41848.856209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41961.968936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41864.816579 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41842.954318 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41844.886706 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +679,165 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99397 # number of read accesses completed -system.cpu0.num_writes 53728 # number of write accesses completed +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) +system.toL2Bus.throughput 51050793519 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 365486 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 365476 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 42834 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 42830 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 73993 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28250 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28248 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 155786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 155781 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118183 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 117760 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118671 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 118343 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 117990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118461 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 118625 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 946355 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1725217 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1723022 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1747851 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1725043 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1729886 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1731401 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1727521 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1744371 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 13854312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 13854312 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 19319872 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 649780490 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 156586979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 156968437 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 157751073 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 24.3 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 157263428 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 156564098 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 157250041 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 157464901 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 157629539 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 24.3 # Layer utilization (%) +system.cpu0.num_reads 98049 # number of read accesses completed +system.cpu0.num_writes 53278 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22406 # number of replacements -system.cpu0.l1c.tagsinuse 396.107523 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13328 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22796 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.584664 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21910 # number of replacements +system.cpu0.l1c.tagsinuse 394.044184 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13156 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22301 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.589929 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.107523 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.773648 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.773648 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1114 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1114 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9865 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9865 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9865 # number of overall hits -system.cpu0.l1c.overall_hits::total 9865 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36190 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36190 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23005 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23005 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59195 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59195 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59195 # number of overall misses -system.cpu0.l1c.overall_misses::total 59195 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1343389412 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1343389412 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1089518245 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1089518245 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2432907657 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2432907657 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2432907657 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2432907657 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44941 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24119 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69060 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69060 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69060 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69060 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953812 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953812 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.857153 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.857153 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.857153 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.857153 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37120.459022 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37120.459022 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47360.062812 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 47360.062812 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 41099.884399 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 41099.884399 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 41099.884399 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 41099.884399 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1437100 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 394.044184 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.769618 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.769618 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8471 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8471 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1074 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1074 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9545 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9545 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9545 # number of overall hits +system.cpu0.l1c.overall_hits::total 9545 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35640 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35640 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23074 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23074 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58714 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58714 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58714 # number of overall misses +system.cpu0.l1c.overall_misses::total 58714 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 933901812 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 933901812 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 856280361 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 856280361 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1790182173 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1790182173 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1790182173 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1790182173 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44111 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44111 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24148 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24148 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68259 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68259 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68259 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68259 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807962 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807962 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955524 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955524 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860165 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860165 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860165 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860165 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26203.754545 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 26203.754545 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37110.182933 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 37110.182933 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.869077 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30489.869077 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.869077 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30489.869077 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1011011 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67352 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61585 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.337154 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.416514 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks -system.cpu0.l1c.writebacks::total 9722 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36190 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23005 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23005 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59195 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59195 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59195 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59195 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1271011412 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1271011412 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1043514245 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1043514245 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2314525657 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2314525657 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2314525657 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2314525657 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 712928581 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 712928581 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 437133462 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 437133462 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1150062043 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1150062043 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953812 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953812 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.857153 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.857153 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35120.514286 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35120.514286 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45360.323625 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45360.323625 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9569 # number of writebacks +system.cpu0.l1c.writebacks::total 9569 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35640 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35640 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23074 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23074 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58714 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58714 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58714 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58714 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860177811 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860177811 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 808764395 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 808764395 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1668942206 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1668942206 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1668942206 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1668942206 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 696207485 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 696207485 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1651009618 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1651009618 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2347217103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2347217103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807962 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807962 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955524 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955524 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860165 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860165 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24135.179882 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24135.179882 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35050.896897 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35050.896897 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +845,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98684 # number of read accesses completed -system.cpu1.num_writes 53281 # number of write accesses completed +system.cpu1.num_reads 98391 # number of read accesses completed +system.cpu1.num_writes 53060 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21834 # number of replacements -system.cpu1.l1c.tagsinuse 394.001606 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13244 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22217 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.596120 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21908 # number of replacements +system.cpu1.l1c.tagsinuse 394.826417 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13138 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22318 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.588673 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 394.001606 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.769534 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.769534 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8661 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8661 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1083 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9744 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9744 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9744 # number of overall hits -system.cpu1.l1c.overall_hits::total 9744 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35792 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35792 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23021 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23021 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58813 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58813 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58813 # number of overall misses -system.cpu1.l1c.overall_misses::total 58813 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1333175718 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1333175718 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1095650216 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1095650216 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2428825934 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2428825934 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2428825934 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2428825934 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44453 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44453 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24104 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24104 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68557 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68557 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68557 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68557 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805165 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805165 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955070 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955070 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857870 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857870 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857870 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857870 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37247.868742 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37247.868742 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47593.510968 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47593.510968 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41297.433119 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41297.433119 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41297.433119 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41297.433119 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1437849 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 394.826417 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.771145 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.771145 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8563 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8563 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1113 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1113 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9676 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9676 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9676 # number of overall hits +system.cpu1.l1c.overall_hits::total 9676 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35632 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35632 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23114 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23114 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58746 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58746 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58746 # number of overall misses +system.cpu1.l1c.overall_misses::total 58746 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 934157803 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 934157803 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 854823705 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 854823705 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1788981508 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1788981508 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1788981508 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1788981508 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44195 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44195 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24227 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24227 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68422 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68422 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68422 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68422 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806245 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806245 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954060 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954060 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858583 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858583 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26216.822042 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 26216.822042 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36982.941291 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 36982.941291 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30452.822456 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30452.822456 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30452.822456 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30452.822456 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1014678 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66915 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61858 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.487693 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.403343 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9612 # number of writebacks -system.cpu1.l1c.writebacks::total 9612 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35792 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23021 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23021 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58813 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58813 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58813 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58813 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1261597219 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1261597219 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1049610216 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1049610216 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2311207435 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2311207435 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2311207435 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2311207435 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 716556549 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 716556549 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 420969607 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 420969607 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1137526156 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1137526156 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805165 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805165 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955070 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955070 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857870 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857870 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35248.022435 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35248.022435 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45593.597845 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45593.597845 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9599 # number of writebacks +system.cpu1.l1c.writebacks::total 9599 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35632 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35632 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23114 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23114 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58746 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58746 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58746 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58746 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 860390916 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 860390916 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 807278180 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 807278180 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1667669096 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1667669096 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1667669096 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1667669096 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 703500956 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 703500956 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1594898180 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1594898180 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2298399136 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2298399136 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806245 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806245 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954060 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954060 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24146.579367 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24146.579367 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34925.940123 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34925.940123 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +960,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99895 # number of read accesses completed -system.cpu2.num_writes 53724 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 53426 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22670 # number of replacements -system.cpu2.l1c.tagsinuse 395.972858 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13513 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 23058 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.586044 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22360 # number of replacements +system.cpu2.l1c.tagsinuse 394.888678 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13327 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22756 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.585648 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 395.972858 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.773384 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.773384 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8816 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8816 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1120 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1120 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits -system.cpu2.l1c.overall_hits::total 9936 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36217 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36217 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23141 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23141 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59358 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59358 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59358 # number of overall misses -system.cpu2.l1c.overall_misses::total 59358 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1347141340 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1347141340 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1089667259 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1089667259 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2436808599 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2436808599 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2436808599 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2436808599 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45033 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45033 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24261 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69294 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69294 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69294 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69294 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804232 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.804232 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953835 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953835 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856611 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856611 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856611 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856611 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37196.381257 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37196.381257 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47088.166415 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47088.166415 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41052.740978 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41052.740978 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41052.740978 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41052.740978 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1437012 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.888678 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.771267 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.771267 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8771 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8771 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1101 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1101 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9872 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9872 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9872 # number of overall hits +system.cpu2.l1c.overall_hits::total 9872 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36112 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36112 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22938 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22938 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59050 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59050 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59050 # number of overall misses +system.cpu2.l1c.overall_misses::total 59050 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 945591370 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 945591370 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 849320343 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 849320343 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1794911713 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1794911713 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1794911713 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1794911713 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44883 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44883 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24039 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24039 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68922 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68922 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68922 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68922 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804581 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.804581 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954199 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954199 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.856766 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.856766 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.856766 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.856766 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26184.962616 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26184.962616 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37026.782762 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 37026.782762 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30396.472701 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30396.472701 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30396.472701 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30396.472701 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1018235 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 67454 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62319 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.303585 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.339078 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9964 # number of writebacks -system.cpu2.l1c.writebacks::total 9964 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36217 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36217 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23141 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23141 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59358 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59358 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1274713340 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1274713340 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1043385259 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1043385259 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2318098599 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2318098599 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2318098599 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2318098599 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 709358616 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 709358616 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 436023988 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 436023988 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1145382604 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1145382604 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953835 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953835 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856611 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856611 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35196.546925 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35196.546925 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45088.166415 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45088.166415 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9616 # number of writebacks +system.cpu2.l1c.writebacks::total 9616 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36112 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36112 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22938 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22938 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59050 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59050 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59050 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59050 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870903925 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870903925 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 802151745 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 802151745 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1673055670 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1673055670 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1673055670 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1673055670 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702585995 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702585995 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1602698265 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1602698265 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2305284260 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2305284260 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804581 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804581 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954199 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954199 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.856766 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.856766 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24116.745819 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24116.745819 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34970.430944 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34970.430944 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1075,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98442 # number of read accesses completed -system.cpu3.num_writes 53057 # number of write accesses completed +system.cpu3.num_reads 98539 # number of read accesses completed +system.cpu3.num_writes 53510 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21593 # number of replacements -system.cpu3.l1c.tagsinuse 392.026155 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13022 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 21995 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.592044 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21926 # number of replacements +system.cpu3.l1c.tagsinuse 394.806744 # Cycle average of tags in use +system.cpu3.l1c.total_refs 12847 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22328 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.575376 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 392.026155 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.765676 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.765676 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8553 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8553 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1036 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1036 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9589 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9589 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9589 # number of overall hits -system.cpu3.l1c.overall_hits::total 9589 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35616 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35616 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22828 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22828 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58444 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58444 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58444 # number of overall misses -system.cpu3.l1c.overall_misses::total 58444 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1343250290 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1343250290 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1077342427 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1077342427 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2420592717 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2420592717 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2420592717 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2420592717 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44169 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44169 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23864 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23864 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68033 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68033 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68033 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68033 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806357 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806357 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956587 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956587 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859054 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859054 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859054 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859054 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37714.799248 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 37714.799248 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47193.903408 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47193.903408 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 41417.300613 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 41417.300613 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 41417.300613 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 41417.300613 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1437847 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 394.806744 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.771107 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.771107 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8426 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8426 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1071 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1071 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9497 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9497 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9497 # number of overall hits +system.cpu3.l1c.overall_hits::total 9497 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35942 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35942 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22767 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22767 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58709 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58709 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58709 # number of overall misses +system.cpu3.l1c.overall_misses::total 58709 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 940164359 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 940164359 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 841530610 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 841530610 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1781694969 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1781694969 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1781694969 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1781694969 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44368 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44368 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23838 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23838 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68206 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68206 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68206 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68206 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810088 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.810088 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955072 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955072 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860760 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860760 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860760 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860760 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26157.819793 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 26157.819793 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36962.735978 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 36962.735978 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30347.901838 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30347.901838 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30347.901838 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30347.901838 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1011201 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66560 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61773 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.602269 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.369628 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9543 # number of writebacks -system.cpu3.l1c.writebacks::total 9543 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35616 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35616 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22828 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22828 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58444 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58444 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58444 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58444 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1272022290 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1272022290 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1031688427 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1031688427 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2303710717 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2303710717 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2303710717 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2303710717 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723405993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723405993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 425307050 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 425307050 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1148713043 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1148713043 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806357 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806357 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956587 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956587 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859054 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859054 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35714.911557 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35714.911557 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45193.991020 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45193.991020 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9447 # number of writebacks +system.cpu3.l1c.writebacks::total 9447 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35942 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35942 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22767 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22767 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58709 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58709 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58709 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58709 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 865819865 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 865819865 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794633661 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794633661 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1660453526 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1660453526 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1660453526 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1660453526 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 705869404 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 705869404 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1670668640 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1670668640 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2376538044 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2376538044 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810088 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810088 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955072 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955072 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860760 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860760 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24089.362445 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24089.362445 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34902.870866 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34902.870866 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1190,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99668 # number of read accesses completed -system.cpu4.num_writes 53668 # number of write accesses completed +system.cpu4.num_reads 98567 # number of read accesses completed +system.cpu4.num_writes 53142 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22398 # number of replacements -system.cpu4.l1c.tagsinuse 394.185618 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13312 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22817 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 21884 # number of replacements +system.cpu4.l1c.tagsinuse 394.848687 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13028 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22289 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.584504 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.185618 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.769894 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.769894 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8742 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8742 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1059 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1059 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9801 # 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number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1082307804 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2432340053 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2432340053 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2432340053 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2432340053 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45025 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45025 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24083 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69108 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69108 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69108 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69108 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805841 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805841 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956027 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.956027 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858179 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858179 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858179 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858179 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37208.396467 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 37208.396467 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47007.809416 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 47007.809416 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 41012.697540 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 41012.697540 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 41012.697540 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 41012.697540 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1437185 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 394.848687 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.771189 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.771189 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8503 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8503 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1105 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1105 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9608 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9608 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9608 # number of overall hits +system.cpu4.l1c.overall_hits::total 9608 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35561 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35561 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23022 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23022 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58583 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58583 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58583 # number of overall misses +system.cpu4.l1c.overall_misses::total 58583 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 936314772 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 936314772 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 859386922 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 859386922 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1795701694 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1795701694 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1795701694 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1795701694 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44064 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44064 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24127 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68191 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68191 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68191 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68191 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807031 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807031 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954201 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954201 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859102 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859102 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859102 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859102 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26329.821209 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 26329.821209 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37328.942837 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 37328.942837 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30652.265913 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30652.265913 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30652.265913 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30652.265913 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1016374 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67419 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61728 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.317210 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.465364 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9672 # number of writebacks -system.cpu4.l1c.writebacks::total 9672 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36283 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36283 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23024 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23024 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59307 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59307 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59307 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59307 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1277470249 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1277470249 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1036263804 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1036263804 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2313734053 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2313734053 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2313734053 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2313734053 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 713854071 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 713854071 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 422821531 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 422821531 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1136675602 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1136675602 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805841 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805841 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956027 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956027 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858179 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858179 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35208.506711 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35208.506711 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45007.983148 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45007.983148 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9520 # number of writebacks +system.cpu4.l1c.writebacks::total 9520 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35561 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35561 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23022 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23022 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58583 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58583 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58583 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58583 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 862769237 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 862769237 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 812030378 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 812030378 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674799615 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1674799615 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674799615 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1674799615 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 700729623 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 700729623 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1644067080 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1644067080 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2344796703 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2344796703 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807031 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807031 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954201 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954201 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859102 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859102 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24261.669722 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24261.669722 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35271.930241 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35271.930241 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1305,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98297 # number of read accesses completed -system.cpu5.num_writes 53409 # number of write accesses completed +system.cpu5.num_reads 98869 # number of read accesses completed +system.cpu5.num_writes 53477 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 21793 # number of replacements -system.cpu5.l1c.tagsinuse 394.840854 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13019 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22214 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.586072 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22131 # number of replacements +system.cpu5.l1c.tagsinuse 394.954130 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13197 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22529 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.585778 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.840854 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771174 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771174 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8574 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8574 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1037 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1037 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9611 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9611 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9611 # number of overall hits -system.cpu5.l1c.overall_hits::total 9611 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35608 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35608 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22949 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22949 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58557 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58557 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58557 # number of overall misses -system.cpu5.l1c.overall_misses::total 58557 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1333115373 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1333115373 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1089027179 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1089027179 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2422142552 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2422142552 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2422142552 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2422142552 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44182 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44182 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 23986 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 23986 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68168 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68168 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68168 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68168 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805939 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805939 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956766 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956766 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859010 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859010 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859010 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859010 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37438.647860 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37438.647860 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47454.232385 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47454.232385 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41363.842956 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41363.842956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41363.842956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41363.842956 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1437965 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 394.954130 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771395 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771395 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8594 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8594 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1100 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1100 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9694 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9694 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9694 # number of overall hits +system.cpu5.l1c.overall_hits::total 9694 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35827 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35827 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23090 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23090 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58917 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58917 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58917 # number of overall misses +system.cpu5.l1c.overall_misses::total 58917 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 936035832 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 936035832 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 858178388 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 858178388 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1794214220 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1794214220 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1794214220 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1794214220 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44421 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44421 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24190 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24190 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68611 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68611 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68611 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68611 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806533 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806533 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954527 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954527 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858711 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858711 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858711 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858711 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26126.547911 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26126.547911 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37166.669034 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 37166.669034 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30453.251523 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30453.251523 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30453.251523 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30453.251523 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1010232 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66766 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61688 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.537384 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.376475 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9530 # number of writebacks -system.cpu5.l1c.writebacks::total 9530 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35608 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35608 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22949 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22949 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58557 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58557 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58557 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58557 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1261899373 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1261899373 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1043133179 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1043133179 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2305032552 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2305032552 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2305032552 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2305032552 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 722637545 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 722637545 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 432075918 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 432075918 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1154713463 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1154713463 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805939 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805939 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956766 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956766 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859010 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859010 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35438.647860 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35438.647860 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45454.406684 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45454.406684 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9611 # number of writebacks +system.cpu5.l1c.writebacks::total 9611 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35827 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35827 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23090 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23090 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58917 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58917 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58917 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58917 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 861924856 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 861924856 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 810652413 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 810652413 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1672577269 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1672577269 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1672577269 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1672577269 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 694440055 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 694440055 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1653385505 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1653385505 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2347825560 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2347825560 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806533 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806533 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954527 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954527 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858711 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858711 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24057.969018 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24057.969018 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35108.376483 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35108.376483 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28388.703922 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28388.703922 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1420,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53851 # number of write accesses completed +system.cpu6.num_reads 99583 # number of read accesses completed +system.cpu6.num_writes 53438 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22533 # number of replacements -system.cpu6.l1c.tagsinuse 396.232181 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13413 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22918 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.585260 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21939 # number of replacements +system.cpu6.l1c.tagsinuse 394.903585 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13339 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22346 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.596930 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 396.232181 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.773891 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.773891 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8765 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8765 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1112 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9877 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9877 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9877 # number of overall hits -system.cpu6.l1c.overall_hits::total 9877 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36287 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36287 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23071 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23071 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59358 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59358 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59358 # number of overall misses -system.cpu6.l1c.overall_misses::total 59358 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1346746093 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1346746093 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1082399151 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1082399151 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2429145244 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2429145244 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2429145244 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2429145244 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45052 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45052 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24183 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24183 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 69235 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 69235 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 69235 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 69235 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805447 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805447 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954017 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954017 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.857341 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.857341 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.857341 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.857341 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37113.734753 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37113.734753 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 46916.004985 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 46916.004985 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 40923.636982 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 40923.636982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 40923.636982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 40923.636982 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1436888 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 394.903585 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.771296 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.771296 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8764 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8764 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9831 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9831 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9831 # number of overall hits +system.cpu6.l1c.overall_hits::total 9831 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36046 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36046 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22895 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22895 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58941 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58941 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58941 # number of overall misses +system.cpu6.l1c.overall_misses::total 58941 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 938279687 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 938279687 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 845796556 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 845796556 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1784076243 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1784076243 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1784076243 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1784076243 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44810 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44810 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23962 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23962 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68772 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68772 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68772 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68772 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804419 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804419 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955471 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955471 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857049 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857049 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857049 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857049 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26030.064002 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26030.064002 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36942.413453 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 36942.413453 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30268.849239 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30268.849239 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30268.849239 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30268.849239 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1009249 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 67354 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61784 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.333373 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.335119 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9760 # number of writebacks -system.cpu6.l1c.writebacks::total 9760 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36287 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36287 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23071 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23071 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59358 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59358 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1274178093 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1274178093 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1036259151 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1036259151 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2310437244 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2310437244 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2310437244 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2310437244 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 716759617 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 716759617 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 439137857 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 439137857 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1155897474 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1155897474 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805447 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805447 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954017 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954017 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857341 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857341 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35113.900102 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35113.900102 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 44916.091674 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 44916.091674 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9560 # number of writebacks +system.cpu6.l1c.writebacks::total 9560 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36046 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36046 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22895 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22895 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58941 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58941 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58941 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58941 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 863686811 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 863686811 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 798668072 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 798668072 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1662354883 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1662354883 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1662354883 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1662354883 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702782954 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702782954 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1637437633 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1637437633 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2340220587 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2340220587 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804419 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804419 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955471 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955471 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857049 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857049 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 23960.683876 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 23960.683876 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34883.951605 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34883.951605 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1535,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99311 # number of read accesses completed -system.cpu7.num_writes 53396 # number of write accesses completed +system.cpu7.num_reads 99199 # number of read accesses completed +system.cpu7.num_writes 53517 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22280 # number of replacements -system.cpu7.l1c.tagsinuse 395.094392 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13351 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22696 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22063 # number of replacements +system.cpu7.l1c.tagsinuse 393.496696 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13289 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22472 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.591358 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 395.094392 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.771669 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.771669 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8656 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8656 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1129 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1129 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9785 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9785 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9785 # number of overall hits -system.cpu7.l1c.overall_hits::total 9785 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36252 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36252 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23067 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23067 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59319 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59319 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59319 # number of overall misses -system.cpu7.l1c.overall_misses::total 59319 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1344539775 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1344539775 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1092348717 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1092348717 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2436888492 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2436888492 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2436888492 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2436888492 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44908 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44908 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24196 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24196 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69104 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69104 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69104 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69104 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807250 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807250 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953339 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953339 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858402 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858402 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858402 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858402 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37088.706140 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 37088.706140 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47355.473924 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47355.473924 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 41081.078440 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 41081.078440 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 41081.078440 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 393.496696 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.768548 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.768548 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8670 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8670 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1128 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1128 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9798 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9798 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9798 # number of overall hits +system.cpu7.l1c.overall_hits::total 9798 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35926 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35926 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23139 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23139 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59065 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59065 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59065 # number of overall misses +system.cpu7.l1c.overall_misses::total 59065 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 933337082 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 933337082 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 860844547 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 860844547 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1794181629 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1794181629 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1794181629 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1794181629 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44596 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44596 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24267 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24267 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68863 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68863 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68863 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68863 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805588 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805588 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953517 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953517 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857717 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857717 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857717 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857717 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25979.432222 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 25979.432222 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37203.187130 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37203.187130 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30376.392601 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30376.392601 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30376.392601 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30376.392601 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1011426 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62031 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.332839 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.305170 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9656 # number of writebacks -system.cpu7.l1c.writebacks::total 9656 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36252 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36252 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23067 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23067 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59319 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59319 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59319 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59319 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1272035775 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1272035775 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1046218717 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1046218717 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2318254492 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2318254492 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2318254492 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2318254492 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 709343608 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 709343608 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432591529 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432591529 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1141935137 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1141935137 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807250 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807250 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953339 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953339 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858402 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858402 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35088.706140 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35088.706140 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45355.647332 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45355.647332 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9494 # number of writebacks +system.cpu7.l1c.writebacks::total 9494 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35926 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35926 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23139 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23139 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59065 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59065 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59065 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59065 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 859043599 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 859043599 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 813252475 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 813252475 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1672296074 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1672296074 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1672296074 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1672296074 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 693959592 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 693959592 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1654672592 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1654672592 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2348632184 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2348632184 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805588 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805588 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953517 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953517 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857717 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857717 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23911.473557 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23911.473557 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35146.396776 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35146.396776 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index adb4052b9..39565381c 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,42 +4,42 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 31852968745 # Simulator tick rate (ticks/s) -host_mem_usage 226592 # Number of bytes of host memory used -host_seconds 3.14 # Real time elapsed on the host -system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory -system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory -system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3333399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu 2133375360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2133375360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu 2133375360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2133375360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333400 # Total number of read requests seen +host_tick_rate 12296459257 # Simulator tick rate (ticks/s) +host_mem_usage 231220 # Number of bytes of host memory used +host_seconds 8.13 # Real time elapsed on the host +system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory +system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory +system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3333300 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3333400 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 213337536 # Total number of bytes read from memory +system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 213331136 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 213337536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -58,14 +58,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 99999990000 # Total gap between requests +system.physmem.totGap 99999960000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3333400 # Categorize read packet sizes +system.physmem.readPktSize::6 3333300 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -73,18 +73,18 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -137,28 +137,51 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests -system.physmem.totBusLat 16667000000 # Total cycles spent in databus access -system.physmem.totBankLat 46722610000 # Total cycles spent in bank access -system.physmem.avgQLat 1833.68 # Average queueing delay per request -system.physmem.avgBankLat 14016.50 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation +system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests +system.physmem.totBusLat 16666500000 # Total cycles spent in databus access +system.physmem.totBankLat 45939671250 # Total cycles spent in bank access +system.physmem.avgQLat 383.63 # Average queueing delay per request +system.physmem.avgBankLat 13782.04 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20850.18 # Average memory access latency -system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 19165.67 # Average memory access latency +system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.70 # Average read queue length over time +system.physmem.avgRdQLen 0.64 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3229200 # Number of row buffer hits during reads +system.physmem.readRowHits 3307200 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29999.40 # Average gap between requests -system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets +system.physmem.avgGap 30000.29 # Average gap between requests +system.membus.throughput 2133311360 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3333300 # Transaction distribution +system.membus.trans_dist::ReadResp 3333299 # Transaction distribution +system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 213331136 # Total data (bytes) +system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 17.2 # Layer utilization (%) +system.cpu.numPackets 3333300 # Number of packets generated +system.cpu.numRetries 0 # Number of retries +system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) +system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets @@ -178,11 +201,11 @@ system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # H system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::64-67 3333400 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::total 3333400 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets @@ -209,9 +232,9 @@ system.monitor.writeBurstLengthHist::18 0 # Hi system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::mean 2133375360 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 2133375359.990565 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 6400.010343 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -233,8 +256,8 @@ system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.averageReadBandwidth 2133375360 0.00% 0.00% # Average read bandwidth (bytes/s) -system.monitor.totalReadBytes 213337536 # Number of bytes read +system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s) +system.monitor.totalReadBytes 213331136 # Number of bytes read system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s) @@ -262,21 +285,21 @@ system.monitor.writeBandwidthHist::19 0 0.00% 100.00% # Hi system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s) system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written -system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency -system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency -system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency -system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::samples 3333299 # Read request-response latency +system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency +system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency +system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency +system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency @@ -286,7 +309,7 @@ system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::total 3333399 # Read request-response latency +system.monitor.readLatencyHist::total 3333299 # Read request-response latency system.monitor.writeLatencyHist::samples 0 # Write request-response latency system.monitor.writeLatencyHist::mean nan # Write request-response latency system.monitor.writeLatencyHist::gmean nan # Write request-response latency @@ -312,18 +335,18 @@ system.monitor.writeLatencyHist::17 0 # Wr system.monitor.writeLatencyHist::18 0 # Write request-response latency system.monitor.writeLatencyHist::19 0 # Write request-response latency system.monitor.writeLatencyHist::total 0 # Write request-response latency -system.monitor.ittReadRead::samples 3333399 # Read-to-read inter transaction time -system.monitor.ittReadRead::mean 29999.406012 # Read-to-read inter transaction time -system.monitor.ittReadRead::stdev 108.992737 # Read-to-read inter transaction time +system.monitor.ittReadRead::samples 3333299 # Read-to-read inter transaction time +system.monitor.ittReadRead::mean 30000.297003 # Read-to-read inter transaction time +system.monitor.ittReadRead::stdev 54.497186 # Read-to-read inter transaction time system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::5001-10000 99 0.00% 0.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::5001-10000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::25001-30000 3333300 100.00% 100.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::25001-30000 3333200 100.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::30001-35000 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::35001-40000 0 0.00% 100.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::35001-40000 99 0.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::40001-45000 0 0.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::45001-50000 0 0.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::50001-55000 0 0.00% 100.00% # Read-to-read inter transaction time @@ -337,9 +360,9 @@ system.monitor.ittReadRead::85001-90000 0 0.00% 100.00% # Re system.monitor.ittReadRead::90001-95000 0 0.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::95001-100000 0 0.00% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::min_value 10000 # Read-to-read inter transaction time -system.monitor.ittReadRead::max_value 30000 # Read-to-read inter transaction time -system.monitor.ittReadRead::total 3333399 # Read-to-read inter transaction time +system.monitor.ittReadRead::min_value 30000 # Read-to-read inter transaction time +system.monitor.ittReadRead::max_value 40000 # Read-to-read inter transaction time +system.monitor.ittReadRead::total 3333299 # Read-to-read inter transaction time system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time @@ -368,18 +391,18 @@ system.monitor.ittWriteWrite::overflows 0 # Wr system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time -system.monitor.ittReqReq::samples 3333399 # Request-to-request inter transaction time -system.monitor.ittReqReq::mean 29999.406012 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 108.992737 # Request-to-request inter transaction time +system.monitor.ittReqReq::samples 3333299 # Request-to-request inter transaction time +system.monitor.ittReqReq::mean 30000.297003 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 54.497186 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::25001-30000 3333300 100.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::25001-30000 3333200 100.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::35001-40000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time @@ -393,9 +416,9 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::min_value 10000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 30000 # Request-to-request inter transaction time -system.monitor.ittReqReq::total 3333399 # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 30000 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time +system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions @@ -447,8 +470,8 @@ system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.readTransHist::mean 33334 # Histogram of read transactions per sample period -system.monitor.readTransHist::gmean 33334.000000 # Histogram of read transactions per sample period +system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period +system.monitor.readTransHist::gmean 33333.000000 # Histogram of read transactions per sample period system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index 3f17aa9b6..d0c130b6b 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,23 +4,40 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 15527580566 # Simulator tick rate (ticks/s) -host_mem_usage 226756 # Number of bytes of host memory used -host_seconds 6.44 # Real time elapsed on the host +host_tick_rate 7576487056 # Simulator tick rate (ticks/s) +host_mem_usage 230980 # Number of bytes of host memory used +host_seconds 13.20 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory -system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory -system.physmem.bytes_written::total 213335552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory +system.physmem.bytes_written::total 213329152 # Number of bytes written to this memory system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory system.physmem.num_reads::total 1 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu 3333368 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3333368 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu 3333268 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3333268 # Number of write requests responded to by this memory system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu 2133355520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2133355520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu 2133356160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2133356160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu 2133291520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2133292160 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1 # Transaction distribution +system.membus.trans_dist::ReadResp 1 # Transaction distribution +system.membus.trans_dist::WriteReq 3333268 # Transaction distribution +system.membus.trans_dist::WriteResp 3333267 # Transaction distribution +system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 213329216 # Total data (bytes) +system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 16.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +system.cpu.numPackets 3333269 # Number of packets generated +system.cpu.numRetries 1 # Number of retries +system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -46,7 +63,7 @@ system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # H system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::total 1 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::samples 3333368 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::samples 3333268 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets @@ -66,11 +83,11 @@ system.monitor.writeBurstLengthHist::48-51 0 0.00% 0.00% # system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::64-67 3333368 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::64-67 3333268 100.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::total 3333368 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::total 3333268 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 640 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::gmean 0 # Histogram of read bandwidth per sample period (bytes/s) @@ -99,8 +116,8 @@ system.monitor.readBandwidthHist::total 100 # Hi system.monitor.averageReadBandwidth 640 0.00% 0.00% # Average read bandwidth (bytes/s) system.monitor.totalReadBytes 64 # Number of bytes read system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::mean 2133355520 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::gmean 2133355510.261974 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::mean 2133291520 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::gmean 2133291510.261604 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::stdev 204800 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s) @@ -123,8 +140,8 @@ system.monitor.writeBandwidthHist::2.2817e+09-2.41592e+09 0 0.00 system.monitor.writeBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s) -system.monitor.averageWriteBandwidth 2133355520 0.00% 0.00% # Average write bandwidth (bytes/s) -system.monitor.totalWrittenBytes 213335552 # Number of bytes written +system.monitor.averageWriteBandwidth 2133291520 0.00% 0.00% # Average write bandwidth (bytes/s) +system.monitor.totalWrittenBytes 213329152 # Number of bytes written system.monitor.readLatencyHist::samples 1 # Read request-response latency system.monitor.readLatencyHist::mean 30000 # Read request-response latency system.monitor.readLatencyHist::gmean 30000.000000 # Read request-response latency @@ -150,10 +167,10 @@ system.monitor.readLatencyHist::34816-36863 0 0.00% 100.00% # system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency -system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency +system.monitor.writeLatencyHist::samples 3333267 # Write request-response latency system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency -system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency +system.monitor.writeLatencyHist::stdev 0.179655 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -168,13 +185,13 @@ system.monitor.writeLatencyHist::20480-22527 0 0.00% 0.00% system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::28672-30719 3333367 100.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 3333267 100.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::total 3333367 # Write request-response latency +system.monitor.writeLatencyHist::total 3333267 # Write request-response latency system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time system.monitor.ittReadRead::stdev nan # Read-to-read inter transaction time @@ -203,18 +220,18 @@ system.monitor.ittReadRead::overflows 0 # Re system.monitor.ittReadRead::min_value 0 # Read-to-read inter transaction time system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time -system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::samples 3333267 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 30000.595310 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 547.340980 # Write-to-write inter transaction time system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::5001-10000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::10001-15000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::15001-20000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::20001-25000 0 0.00% 0.00% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::25001-30000 3333267 100.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::25001-30000 3333167 100.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::30001-35000 0 0.00% 100.00% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::35001-40000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::35001-40000 99 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::40001-45000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::45001-50000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::50001-55000 0 0.00% 100.00% # Write-to-write inter transaction time @@ -228,21 +245,21 @@ system.monitor.ittWriteWrite::85001-90000 0 0.00% 100.00% # W system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time -system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time -system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time +system.monitor.ittWriteWrite::min_value 30000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 1024328 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::total 3333267 # Write-to-write inter transaction time +system.monitor.ittReqReq::samples 3333268 # Request-to-request inter transaction time +system.monitor.ittReqReq::mean 30000.587712 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 547.516688 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::25001-30000 3333267 100.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::25001-30000 3333167 100.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::35001-40000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time @@ -257,8 +274,8 @@ system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Re system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time -system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 1024328 # Request-to-request inter transaction time +system.monitor.ittReqReq::total 3333268 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions @@ -335,8 +352,8 @@ system.monitor.readTransHist::18 0 0.00% 100.00% # Hi system.monitor.readTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.writeTransHist::mean 33333.680000 # Histogram of read transactions per sample period -system.monitor.writeTransHist::gmean 33333.679848 # Histogram of read transactions per sample period +system.monitor.writeTransHist::mean 33332.680000 # Histogram of read transactions per sample period +system.monitor.writeTransHist::gmean 33332.679848 # Histogram of read transactions per sample period system.monitor.writeTransHist::stdev 3.200000 # Histogram of read transactions per sample period system.monitor.writeTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period |