diff options
Diffstat (limited to 'tests/quick/se')
23 files changed, 547 insertions, 547 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 3eedd5023..164aeb3c8 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Feb/02/2013 08:15:30 +Real time: Apr/09/2013 02:05:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 82 -Elapsed_time_in_minutes: 1.36667 -Elapsed_time_in_hours: 0.0227778 -Elapsed_time_in_days: 0.000949074 +Elapsed_time_in_seconds: 139 +Elapsed_time_in_minutes: 2.31667 +Elapsed_time_in_hours: 0.0386111 +Elapsed_time_in_days: 0.0016088 -Virtual_time_in_seconds: 80.54 -Virtual_time_in_minutes: 1.34233 -Virtual_time_in_hours: 0.0223722 -Virtual_time_in_days: 0.000932176 +Virtual_time_in_seconds: 139.38 +Virtual_time_in_minutes: 2.323 +Virtual_time_in_hours: 0.0387167 +Virtual_time_in_days: 0.00161319 Ruby_current_time: 7257449 Ruby_start_time: 0 Ruby_cycles: 7257449 -mbytes_resident: 71.4336 -mbytes_total: 411.711 -resident_ratio: 0.173542 +mbytes_resident: 65.4102 +mbytes_total: 245.32 +resident_ratio: 0.266632 ruby_cycles_executed: [ 7257450 7257450 7257450 7257450 7257450 7257450 7257450 7257450 ] @@ -79,13 +79,13 @@ Total_delay_cycles: [binsize: 32 max: 952 count: 4856797 average: 43.4082 | stan Resource Usage -------------- page_size: 4096 -user_time: 80 +user_time: 139 system_time: 0 -page_reclaims: 10252 -page_faults: 0 +page_reclaims: 17300 +page_faults: 7 swaps: 0 -block_inputs: 0 -block_outputs: 272 +block_inputs: 1648 +block_outputs: 296 Network Stats ------------- @@ -315,40 +315,40 @@ Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [49747 49368 50044 49642 49778 49377 49516 49381 ] 396853 +Load [49778 49377 49516 49381 49747 49368 50044 49642 ] 396853 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26897 26600 26631 26746 26786 26679 26651 26574 ] 213564 -Inv [73836 73403 73975 73550 73735 73350 73434 73266 ] 588549 -L1_Replacement [533499 530493 533236 532831 533617 530929 531837 527767 ] 4254209 -Fwd_GETX [215 204 212 216 198 220 198 200 ] 1663 -Fwd_GETS [149 129 133 142 159 151 153 155 ] 1171 +Store [26786 26679 26651 26574 26897 26600 26631 26746 ] 213564 +Inv [73735 73350 73434 73266 73836 73403 73975 73550 ] 588549 +L1_Replacement [533617 530929 531837 527767 533499 530493 533236 532831 ] 4254209 +Fwd_GETX [198 220 198 200 215 204 212 216 ] 1663 +Fwd_GETS [159 151 153 155 149 129 133 142 ] 1171 Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -Data [3 2 1 1 1 2 1 0 ] 11 -Data_Exclusive [48923 48630 49230 48877 48989 48607 48775 48593 ] 390624 -DataS_fromL1 [133 124 182 136 147 148 149 152 ] 1171 -Data_all_Acks [27578 27207 27259 27370 27420 27295 27237 27204 ] 218570 -Ack [3 2 1 1 1 2 1 0 ] 11 -Ack_all [3 2 1 1 1 2 1 0 ] 11 -WB_Ack [40309 39563 40425 40081 40110 39623 40034 39662 ] 319807 +Data [1 2 1 0 3 2 1 1 ] 11 +Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624 +DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171 +Data_all_Acks [27420 27295 27237 27204 27578 27207 27259 27370 ] 218570 +Ack [1 2 1 0 3 2 1 1 ] 11 +Ack_all [1 2 1 0 3 2 1 1 ] 11 +WB_Ack [40110 39623 40034 39662 40309 39563 40425 40081 ] 319807 PF_Load [0 0 0 0 0 0 0 0 ] 0 PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 PF_Store [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load [49736 49359 50040 49632 49768 49368 49506 49370 ] 396779 +NP Load [49768 49368 49506 49370 49736 49359 50040 49632 ] 396779 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [26890 26593 26629 26744 26783 26673 26639 26570 ] 213521 -NP Inv [420 399 405 385 436 404 386 385 ] 3220 +NP Store [26783 26673 26639 26570 26890 26593 26629 26744 ] 213521 +NP Inv [436 404 386 385 420 399 405 385 ] 3220 NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 NP PF_Load [0 0 0 0 0 0 0 0 ] 0 NP PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 NP PF_Store [0 0 0 0 0 0 0 0 ] 0 -I Load [9 8 4 8 8 9 9 9 ] 64 +I Load [8 9 9 9 9 8 4 8 ] 64 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [6 6 2 2 2 6 11 4 ] 39 +I Store [2 6 11 4 6 6 2 2 ] 39 I Inv [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [35950 36049 35879 35962 36061 36066 35776 35948 ] 287691 +I L1_Replacement [36061 36066 35776 35948 35950 36049 35879 35962 ] 287691 I PF_Load [0 0 0 0 0 0 0 0 ] 0 I PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 I PF_Store [0 0 0 0 0 0 0 0 ] 0 @@ -356,29 +356,29 @@ I PF_Store [0 0 0 0 0 0 0 0 ] 0 S Load [0 0 0 0 0 0 0 0 ] 0 S Ifetch [0 0 0 0 0 0 0 0 ] 0 S Store [0 0 0 0 0 0 0 0 ] 0 -S Inv [526 446 511 500 475 488 482 528 ] 3956 -S L1_Replacement [361 336 360 328 375 347 329 325 ] 2761 +S Inv [475 488 482 528 526 446 511 500 ] 3956 +S L1_Replacement [375 347 329 325 361 336 360 328 ] 2761 S PF_Load [0 0 0 0 0 0 0 0 ] 0 S PF_Store [0 0 0 0 0 0 0 0 ] 0 -E Load [1 0 0 2 2 0 0 0 ] 5 +E Load [2 0 0 0 1 0 0 2 ] 5 E Ifetch [0 0 0 0 0 0 0 0 ] 0 E Store [0 0 0 0 0 0 0 0 ] 0 -E Inv [22694 23009 22944 22917 22855 23068 22724 22855 ] 183066 -E L1_Replacement [26159 25558 26202 25901 26080 25475 25987 25671 ] 207033 -E Fwd_GETX [56 56 77 52 47 55 52 62 ] 457 -E Fwd_GETS [14 7 7 7 7 9 12 5 ] 68 +E Inv [22855 23068 22724 22855 22694 23009 22944 22917 ] 183066 +E L1_Replacement [26080 25475 25987 25671 26159 25558 26202 25901 ] 207033 +E Fwd_GETX [47 55 52 62 56 56 77 52 ] 457 +E Fwd_GETS [7 9 12 5 14 7 7 7 ] 68 E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 E PF_Load [0 0 0 0 0 0 0 0 ] 0 E PF_Store [0 0 0 0 0 0 0 0 ] 0 -M Load [1 1 0 0 0 0 0 1 ] 3 +M Load [0 0 0 1 1 1 0 0 ] 3 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [0 1 0 0 1 0 1 0 ] 3 -M Inv [12663 12517 12326 12472 12660 12445 12509 12484 ] 100076 -M L1_Replacement [14152 14005 14224 14181 14031 14149 14049 13992 ] 112783 -M Fwd_GETX [26 36 27 32 34 25 30 32 ] 242 -M Fwd_GETS [54 40 53 61 59 60 61 63 ] 451 +M Store [1 0 1 0 0 1 0 0 ] 3 +M Inv [12660 12445 12509 12484 12663 12517 12326 12472 ] 100076 +M L1_Replacement [14031 14149 14049 13992 14152 14005 14224 14181 ] 112783 +M Fwd_GETX [34 25 30 32 26 36 27 32 ] 242 +M Fwd_GETS [59 60 61 63 54 40 53 61 ] 451 M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 M PF_Load [0 0 0 0 0 0 0 0 ] 0 M PF_Store [0 0 0 0 0 0 0 0 ] 0 @@ -386,11 +386,11 @@ M PF_Store [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS Inv [0 0 1 1 0 0 0 0 ] 2 -IS L1_Replacement [297188 294582 298840 297864 297388 295578 296859 294148 ] 2372447 -IS Data_Exclusive [48923 48630 49230 48877 48989 48607 48775 48593 ] 390624 -IS DataS_fromL1 [133 124 182 136 147 148 149 152 ] 1171 -IS Data_all_Acks [686 611 629 624 637 618 589 633 ] 5027 +IS Inv [0 0 0 0 0 0 1 1 ] 2 +IS L1_Replacement [297388 295578 296859 294148 297188 294582 298840 297864 ] 2372447 +IS Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624 +IS DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171 +IS Data_all_Acks [637 618 589 633 686 611 629 624 ] 5027 IS PF_Load [0 0 0 0 0 0 0 0 ] 0 IS PF_Store [0 0 0 0 0 0 0 0 ] 0 @@ -398,9 +398,9 @@ IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [159689 159963 157731 158595 159682 159314 158837 157683 ] 1271494 -IM Data [3 2 1 1 1 2 1 0 ] 11 -IM Data_all_Acks [26892 26596 26629 26745 26783 26677 26648 26571 ] 213541 +IM L1_Replacement [159682 159314 158837 157683 159689 159963 157731 158595 ] 1271494 +IM Data [1 2 1 0 3 2 1 1 ] 11 +IM Data_all_Acks [26783 26677 26648 26571 26892 26596 26629 26745 ] 213541 IM Ack [0 0 0 0 0 0 0 0 ] 0 IM PF_Load [0 0 0 0 0 0 0 0 ] 0 IM PF_Store [0 0 0 0 0 0 0 0 ] 0 @@ -410,8 +410,8 @@ SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM Inv [0 0 0 0 0 0 0 0 ] 0 SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM Ack [3 2 1 1 1 2 1 0 ] 11 -SM Ack_all [3 2 1 1 1 2 1 0 ] 11 +SM Ack [1 2 1 0 3 2 1 1 ] 11 +SM Ack_all [1 2 1 0 3 2 1 1 ] 11 SM PF_Load [0 0 0 0 0 0 0 0 ] 0 SM PF_Store [0 0 0 0 0 0 0 0 ] 0 @@ -422,28 +422,28 @@ IS_I Inv [0 0 0 0 0 0 0 0 ] 0 IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -IS_I Data_all_Acks [0 0 1 1 0 0 0 0 ] 2 +IS_I Data_all_Acks [0 0 0 0 0 0 1 1 ] 2 IS_I PF_Load [0 0 0 0 0 0 0 0 ] 0 IS_I PF_Store [0 0 0 0 0 0 0 0 ] 0 M_I Load [0 0 0 0 0 0 0 0 ] 0 M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 M_I Store [0 0 0 0 0 0 0 0 ] 0 -M_I Inv [37511 37013 37760 37258 37277 36920 37310 36987 ] 298036 +M_I Inv [37277 36920 37310 36987 37511 37013 37760 37258 ] 298036 M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_I Fwd_GETX [133 112 108 132 117 140 116 106 ] 964 -M_I Fwd_GETS [81 82 73 74 93 82 80 87 ] 652 +M_I Fwd_GETX [117 140 116 106 133 112 108 132 ] 964 +M_I Fwd_GETS [93 82 80 87 81 82 73 74 ] 652 M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M_I WB_Ack [2584 2356 2484 2618 2624 2482 2530 2483 ] 20161 +M_I WB_Ack [2624 2482 2530 2483 2584 2356 2484 2618 ] 20161 M_I PF_Load [0 0 0 0 0 0 0 0 ] 0 M_I PF_Store [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Load [0 0 0 0 0 0 1 1 ] 2 +SINK_WB_ACK Load [0 0 1 1 0 0 0 0 ] 2 SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Store [1 0 0 0 0 0 0 0 ] 1 -SINK_WB_ACK Inv [22 19 28 17 32 25 23 27 ] 193 +SINK_WB_ACK Store [0 0 0 0 1 0 0 0 ] 1 +SINK_WB_ACK Inv [32 25 23 27 22 19 28 17 ] 193 SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK WB_Ack [37725 37207 37941 37463 37486 37141 37504 37179 ] 299646 +SINK_WB_ACK WB_Ack [37486 37141 37504 37179 37725 37207 37941 37463 ] 299646 SINK_WB_ACK PF_Load [0 0 0 0 0 0 0 0 ] 0 SINK_WB_ACK PF_Store [0 0 0 0 0 0 0 0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr index 14677e76a..d0c477d0e 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr @@ -1,10 +1,10 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 system.cpu3: completed 10000 read, 5414 write accesses @719275 system.cpu1: completed 10000 read, 5207 write accesses @725827 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 2f163cfb2..82781df07 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memte gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 9 2012 13:23:52 -gem5 started Nov 10 2012 16:11:14 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Apr 9 2013 02:02:21 +gem5 started Apr 9 2013 02:03:11 +gem5 executing on vein command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index bbb60b174..1cc7a22a4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007257 # Nu sim_ticks 7257449 # Number of ticks simulated final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 71811 # Simulator tick rate (ticks/s) -host_mem_usage 426868 # Number of bytes of host memory used -host_seconds 101.06 # Real time elapsed on the host +host_tick_rate 51998 # Simulator tick rate (ticks/s) +host_mem_usage 251212 # Number of bytes of host memory used +host_seconds 139.57 # Real time elapsed on the host system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index a5a6e7d2f..dcffdd237 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index e8efde92a..79036f78e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Feb/02/2013 08:19:23 +Real time: Apr/09/2013 02:09:54 Profiler Stats -------------- -Elapsed_time_in_seconds: 144 -Elapsed_time_in_minutes: 2.4 -Elapsed_time_in_hours: 0.04 -Elapsed_time_in_days: 0.00166667 +Elapsed_time_in_seconds: 223 +Elapsed_time_in_minutes: 3.71667 +Elapsed_time_in_hours: 0.0619444 +Elapsed_time_in_days: 0.00258102 -Virtual_time_in_seconds: 135.17 -Virtual_time_in_minutes: 2.25283 -Virtual_time_in_hours: 0.0375472 -Virtual_time_in_days: 0.00156447 +Virtual_time_in_seconds: 221.76 +Virtual_time_in_minutes: 3.696 +Virtual_time_in_hours: 0.0616 +Virtual_time_in_days: 0.00256667 Ruby_current_time: 7481441 Ruby_start_time: 0 Ruby_cycles: 7481441 -mbytes_resident: 71.4609 -mbytes_total: 411.781 -resident_ratio: 0.173579 +mbytes_resident: 65.2656 +mbytes_total: 244.539 +resident_ratio: 0.266892 ruby_cycles_executed: [ 7481442 7481442 7481442 7481442 7481442 7481442 7481442 7481442 ] @@ -79,13 +79,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation Resource Usage -------------- page_size: 4096 -user_time: 135 +user_time: 221 system_time: 0 -page_reclaims: 10357 -page_faults: 0 +page_reclaims: 17271 +page_faults: 2 swaps: 0 -block_inputs: 0 -block_outputs: 296 +block_inputs: 240 +block_outputs: 304 Network Stats ------------- @@ -391,93 +391,93 @@ Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [50375 50577 50611 50361 50249 50370 49923 50235 ] 402701 +Load [50249 50370 49923 50235 50375 50577 50611 50361 ] 402701 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27079 26983 27113 27205 27052 27339 27175 27153 ] 217099 -L1_Replacement [9608029 9605100 9598595 9603783 9611009 9602265 9618315 9608777 ] 76855873 -Own_GETX [0 0 0 0 0 0 0 1 ] 1 -Fwd_GETX [393 374 406 457 395 352 364 433 ] 3174 -Fwd_GETS [692 715 690 649 764 770 739 739 ] 5758 +Store [27052 27339 27175 27153 27079 26983 27113 27205 ] 217099 +L1_Replacement [9611009 9602265 9618315 9608777 9608029 9605100 9598595 9603783 ] 76855873 +Own_GETX [0 0 0 1 0 0 0 0 ] 1 +Fwd_GETX [395 352 364 433 393 374 406 457 ] 3174 +Fwd_GETS [764 770 739 739 692 715 690 649 ] 5758 Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -Inv [2 1 3 1 6 3 0 3 ] 19 -Ack [372 350 417 380 376 376 382 351 ] 3004 -Data [738 721 703 719 720 712 716 661 ] 5690 -Exclusive_Data [76686 76787 76960 76807 76548 76964 76362 76663 ] 613777 -Writeback_Ack [639 632 619 639 637 632 612 579 ] 4989 -Writeback_Ack_Data [76717 76818 76980 76828 76553 76972 76401 76678 ] 613947 -Writeback_Nack [37 44 37 38 52 53 49 52 ] 362 -All_acks [27069 26960 27107 27196 27041 27326 27165 27136 ] 217000 -Use_Timeout [76686 76787 76959 76807 76548 76964 76362 76664 ] 613777 +Inv [6 3 0 3 2 1 3 1 ] 19 +Ack [376 376 382 351 372 350 417 380 ] 3004 +Data [720 712 716 661 738 721 703 719 ] 5690 +Exclusive_Data [76548 76964 76362 76663 76686 76787 76960 76807 ] 613777 +Writeback_Ack [637 632 612 579 639 632 619 639 ] 4989 +Writeback_Ack_Data [76553 76972 76401 76678 76717 76818 76980 76828 ] 613947 +Writeback_Nack [52 53 49 52 37 44 37 38 ] 362 +All_acks [27041 27326 27165 27136 27069 26960 27107 27196 ] 217000 +Use_Timeout [76548 76964 76362 76664 76686 76787 76959 76807 ] 613777 - Transitions - -I Load [50358 50550 50559 50332 50230 50351 49916 50192 ] 402488 +I Load [50230 50351 49916 50192 50358 50550 50559 50332 ] 402488 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [27070 26961 27107 27196 27042 27328 27166 27136 ] 217006 -I L1_Replacement [67 57 62 56 70 67 65 64 ] 508 +I Store [27042 27328 27166 27136 27070 26961 27107 27196 ] 217006 +I L1_Replacement [70 67 65 64 67 57 62 56 ] 508 I Inv [0 0 0 0 0 0 0 0 ] 0 -S Load [0 0 0 0 0 0 0 1 ] 1 +S Load [0 0 0 1 0 0 0 0 ] 1 S Ifetch [0 0 0 0 0 0 0 0 ] 0 S Store [0 0 0 0 0 0 0 0 ] 0 -S L1_Replacement [736 720 701 719 719 712 716 660 ] 5683 +S L1_Replacement [719 712 716 660 736 720 701 719 ] 5683 S Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 S Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -S Inv [2 1 2 0 1 0 0 1 ] 7 +S Inv [1 0 0 1 2 1 2 0 ] 7 O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [0 0 0 0 0 0 0 1 ] 1 -O L1_Replacement [37 50 34 43 50 43 42 40 ] 339 +O Store [0 0 0 1 0 0 0 0 ] 1 +O L1_Replacement [50 43 42 40 37 50 34 43 ] 339 O Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -O Fwd_GETS [1 0 1 1 0 2 1 0 ] 6 +O Fwd_GETS [0 2 1 0 1 0 1 1 ] 6 O Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M Load [2 5 2 2 2 3 2 5 ] 23 +M Load [2 3 2 5 2 5 2 2 ] 23 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [3 0 0 5 3 0 2 2 ] 15 -M L1_Replacement [49545 49751 49794 49535 49426 49555 49122 49457 ] 396185 -M Fwd_GETX [27 19 22 25 24 29 29 27 ] 202 -M Fwd_GETS [37 50 34 43 50 43 42 41 ] 340 +M Store [3 0 2 2 3 0 0 5 ] 15 +M L1_Replacement [49426 49555 49122 49457 49545 49751 49794 49535 ] 396185 +M Fwd_GETX [24 29 29 27 27 19 22 25 ] 202 +M Fwd_GETS [50 43 42 41 37 50 34 43 ] 340 M Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M_W Load [7 7 6 8 9 8 3 9 ] 57 +M_W Load [9 8 3 9 7 7 6 8 ] 57 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [5 7 2 2 4 10 2 1 ] 33 -M_W L1_Replacement [893182 893219 892511 891162 888542 887409 886648 890208 ] 7122881 +M_W Store [4 10 2 1 5 7 2 2 ] 33 +M_W L1_Replacement [888542 887409 886648 890208 893182 893219 892511 891162 ] 7122881 M_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Fwd_GETX [15 9 19 17 14 10 15 16 ] 115 -M_W Fwd_GETS [14 29 32 25 35 22 26 25 ] 208 +M_W Fwd_GETX [14 10 15 16 15 9 19 17 ] 115 +M_W Fwd_GETS [35 22 26 25 14 29 32 25 ] 208 M_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 M_W Inv [0 0 0 0 0 0 0 0 ] 0 -M_W Use_Timeout [49612 49820 49850 49609 49503 49628 49195 49527 ] 396744 +M_W Use_Timeout [49503 49628 49195 49527 49612 49820 49850 49609 ] 396744 -MM Load [3 0 3 1 3 3 0 4 ] 17 +MM Load [3 3 0 4 3 0 3 1 ] 17 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [0 1 1 1 0 0 1 3 ] 7 -MM L1_Replacement [27039 26929 27071 27171 27003 27298 27133 27103 ] 216747 -MM Fwd_GETX [11 13 10 14 9 7 14 11 ] 89 -MM Fwd_GETS [27 24 28 17 36 31 22 25 ] 210 +MM Store [0 0 1 3 0 1 1 1 ] 7 +MM L1_Replacement [27003 27298 27133 27103 27039 26929 27071 27171 ] 216747 +MM Fwd_GETX [9 7 14 11 11 13 10 14 ] 89 +MM Fwd_GETS [36 31 22 25 27 24 28 17 ] 210 MM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [1 3 4 3 4 5 2 5 ] 27 +MM_W Load [4 5 2 5 1 3 4 3 ] 27 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [0 2 3 1 2 1 2 1 ] 12 -MM_W L1_Replacement [498638 499252 498871 501742 503603 505001 504191 503264 ] 4014562 +MM_W Store [2 1 2 1 0 2 3 1 ] 12 +MM_W L1_Replacement [503603 505001 504191 503264 498638 499252 498871 501742 ] 4014562 MM_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Fwd_GETX [9 11 5 14 8 6 8 14 ] 75 -MM_W Fwd_GETS [19 12 18 2 20 15 9 19 ] 114 +MM_W Fwd_GETX [8 6 8 14 9 11 5 14 ] 75 +MM_W Fwd_GETS [20 15 9 19 19 12 18 2 ] 114 MM_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MM_W Inv [0 0 0 0 0 0 0 0 ] 0 -MM_W Use_Timeout [27074 26967 27109 27198 27045 27336 27167 27137 ] 217033 +MM_W Use_Timeout [27045 27336 27167 27137 27074 26967 27109 27198 ] 217033 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [2844320 2831082 2837633 2852830 2854379 2860141 2888247 2844877 ] 22813509 +IM L1_Replacement [2854379 2860141 2888247 2844877 2844320 2831082 2837633 2852830 ] 22813509 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM Ack [370 346 410 376 374 373 380 346 ] 2975 +IM Ack [374 373 380 346 370 346 410 376 ] 2975 IM Data [0 0 0 0 0 0 0 0 ] 0 -IM Exclusive_Data [27069 26960 27107 27196 27041 27326 27165 27135 ] 216999 +IM Exclusive_Data [27041 27326 27165 27135 27069 26960 27107 27196 ] 216999 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -493,53 +493,53 @@ SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 -OM L1_Replacement [15663 15820 15975 15323 15977 16015 16094 15787 ] 126654 -OM Own_GETX [0 0 0 0 0 0 0 1 ] 1 +OM L1_Replacement [15977 16015 16094 15787 15663 15820 15975 15323 ] 126654 +OM Own_GETX [0 0 0 1 0 0 0 0 ] 1 OM Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 OM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 OM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -OM Ack [2 4 7 4 2 3 2 5 ] 29 -OM All_acks [27069 26960 27107 27196 27041 27326 27165 27136 ] 217000 +OM Ack [2 3 2 5 2 4 7 4 ] 29 +OM All_acks [27041 27326 27165 27136 27069 26960 27107 27196 ] 217000 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [5278802 5288220 5275943 5265202 5271240 5256024 5246057 5277317 ] 42158805 +IS L1_Replacement [5271240 5256024 5246057 5277317 5278802 5288220 5275943 5265202 ] 42158805 IS Inv [0 0 0 0 0 0 0 0 ] 0 -IS Data [738 721 703 719 720 712 716 661 ] 5690 -IS Exclusive_Data [49617 49827 49853 49611 49507 49638 49197 49528 ] 396778 +IS Data [720 712 716 661 738 721 703 719 ] 5690 +IS Exclusive_Data [49507 49638 49197 49528 49617 49827 49853 49611 ] 396778 SI Load [0 0 0 0 0 0 0 0 ] 0 SI Ifetch [0 0 0 0 0 0 0 0 ] 0 SI Store [0 0 0 0 0 0 0 0 ] 0 SI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SI Fwd_GETS [1 0 1 0 2 0 3 1 ] 8 +SI Fwd_GETS [2 0 3 1 1 0 1 0 ] 8 SI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -SI Inv [0 0 1 1 5 3 0 2 ] 12 -SI Writeback_Ack [639 632 619 639 637 632 612 579 ] 4989 -SI Writeback_Ack_Data [97 88 81 79 77 77 104 79 ] 682 +SI Inv [5 3 0 2 0 0 1 1 ] 12 +SI Writeback_Ack [637 632 612 579 639 632 619 639 ] 4989 +SI Writeback_Ack_Data [77 77 104 79 97 88 81 79 ] 682 SI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 OI Load [0 0 0 0 0 0 0 0 ] 0 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 OI Store [0 0 0 0 0 0 0 0 ] 0 OI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -OI Fwd_GETX [2 1 3 1 3 1 1 0 ] 12 -OI Fwd_GETS [4 2 5 1 1 5 2 0 ] 20 +OI Fwd_GETX [3 1 1 0 2 1 3 1 ] 12 +OI Fwd_GETS [1 5 2 0 4 2 5 1 ] 20 OI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack_Data [624 647 602 602 667 694 675 668 ] 5179 -OI Writeback_Nack [36 44 36 37 45 49 49 49 ] 345 +OI Writeback_Ack_Data [667 694 675 668 624 647 602 602 ] 5179 +OI Writeback_Nack [45 49 49 49 36 44 36 37 ] 345 -MI Load [4 12 37 15 1 0 0 19 ] 88 +MI Load [1 0 0 19 4 12 37 15 ] 88 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [1 12 0 0 1 0 2 9 ] 25 +MI Store [1 0 2 9 1 12 0 0 ] 25 MI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETX [329 321 347 386 337 299 297 365 ] 2681 -MI Fwd_GETS [589 598 571 560 620 652 634 628 ] 4852 +MI Fwd_GETX [337 299 297 365 329 321 347 386 ] 2681 +MI Fwd_GETS [620 652 634 628 589 598 571 560 ] 4852 MI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack_Data [75666 75761 75947 75760 75471 75902 75324 75567 ] 605398 +MI Writeback_Ack_Data [75471 75902 75324 75567 75666 75761 75947 75760 ] 605398 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -548,8 +548,8 @@ II Store [0 0 0 0 0 0 0 0 ] 0 II L1_Replacement [0 0 0 0 0 0 0 0 ] 0 II Inv [0 0 0 0 0 0 0 0 ] 0 II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack_Data [330 322 350 387 338 299 298 364 ] 2688 -II Writeback_Nack [1 0 1 1 7 4 0 3 ] 17 +II Writeback_Ack_Data [338 299 298 364 330 322 350 387 ] 2688 +II Writeback_Nack [7 4 0 3 1 0 1 1 ] 17 Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 1087de293..30ecc5910 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 9 2012 13:27:59 -gem5 started Nov 10 2012 16:11:47 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Apr 9 2013 02:05:20 +gem5 started Apr 9 2013 02:06:11 +gem5 executing on vein command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 7473494 because maximum number of loads reached +Exiting @ tick 7481441 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 05da5ac83..16c080216 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007481 # Nu sim_ticks 7481441 # Number of ticks simulated final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 51711 # Simulator tick rate (ticks/s) -host_mem_usage 421668 # Number of bytes of host memory used -host_seconds 144.68 # Real time elapsed on the host +host_tick_rate 33553 # Simulator tick rate (ticks/s) +host_mem_usage 250412 # Number of bytes of host memory used +host_seconds 222.97 # Real time elapsed on the host system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index 831205199..940350216 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index a2ac4883d..d45693ce5 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -1,24 +1,24 @@ -Real time: Feb/02/2013 08:21:48 +Real time: Apr/09/2013 02:12:00 Profiler Stats -------------- -Elapsed_time_in_seconds: 104 -Elapsed_time_in_minutes: 1.73333 -Elapsed_time_in_hours: 0.0288889 -Elapsed_time_in_days: 0.0012037 +Elapsed_time_in_seconds: 161 +Elapsed_time_in_minutes: 2.68333 +Elapsed_time_in_hours: 0.0447222 +Elapsed_time_in_days: 0.00186343 -Virtual_time_in_seconds: 102.2 -Virtual_time_in_minutes: 1.70333 -Virtual_time_in_hours: 0.0283889 -Virtual_time_in_days: 0.00118287 +Virtual_time_in_seconds: 160.82 +Virtual_time_in_minutes: 2.68033 +Virtual_time_in_hours: 0.0446722 +Virtual_time_in_days: 0.00186134 Ruby_current_time: 6151475 Ruby_start_time: 0 Ruby_cycles: 6151475 -mbytes_resident: 70.832 -mbytes_total: 410.77 -resident_ratio: 0.172475 +mbytes_resident: 65.0859 +mbytes_total: 244.512 +resident_ratio: 0.266187 ruby_cycles_executed: [ 6151476 6151476 6151476 6151476 6151476 6151476 6151476 6151476 ] @@ -88,13 +88,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation Resource Usage -------------- page_size: 4096 -user_time: 102 +user_time: 160 system_time: 0 -page_reclaims: 10686 -page_faults: 0 +page_reclaims: 17197 +page_faults: 10 swaps: 0 -block_inputs: 0 -block_outputs: 296 +block_inputs: 1400 +block_outputs: 312 Network Stats ------------- @@ -421,99 +421,99 @@ Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [50017 50259 50136 50016 50331 49967 50254 50183 ] 401163 +Load [50331 49967 50254 50183 50017 50259 50136 50016 ] 401163 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26950 27007 27203 26930 26960 27312 26841 26622 ] 215825 +Store [26960 27312 26841 26622 26950 27007 27203 26930 ] 215825 Atomic [0 0 0 0 0 0 0 0 ] 0 -L1_Replacement [1362554 1365525 1369124 1360777 1368057 1367643 1363908 1358410 ] 10915998 -Data_Shared [242 233 202 233 236 219 237 210 ] 1812 -Data_Owner [71 66 41 52 73 74 52 50 ] 479 -Data_All_Tokens [80401 80744 80888 80464 80940 80743 80630 80297 ] 645107 -Ack [3 2 4 1 1 0 3 0 ] 14 -Ack_All_Tokens [1 0 0 1 1 1 0 1 ] 5 +L1_Replacement [1368057 1367643 1363908 1358410 1362554 1365525 1369124 1360777 ] 10915998 +Data_Shared [236 219 237 210 242 233 202 233 ] 1812 +Data_Owner [73 74 52 50 71 66 41 52 ] 479 +Data_All_Tokens [80940 80743 80630 80297 80401 80744 80888 80464 ] 645107 +Ack [1 0 3 0 3 2 4 1 ] 14 +Ack_All_Tokens [1 1 0 1 1 0 0 1 ] 5 Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETX [188828 188776 188573 188847 188823 188465 188937 189155 ] 1510404 +Transient_Local_GETX [188823 188465 188937 189155 188828 188776 188573 188847 ] 1510404 Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS [351048 350805 350930 351050 350731 351096 350807 350881 ] 2807348 +Transient_Local_GETS [350731 351096 350807 350881 351048 350805 350930 351050 ] 2807348 Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS_Last_Token [0 1 0 1 2 0 1 4 ] 9 -Persistent_GETX [40236 40319 40323 40294 40243 40235 40237 40452 ] 322339 -Persistent_GETS [74071 73914 74014 74024 74022 73973 73853 73992 ] 591863 -Persistent_GETS_Last_Token [1 0 0 0 0 0 1 1 ] 3 -Own_Lock_or_Unlock [145384 145459 145355 145374 145427 145484 145601 145247 ] 1163331 -Request_Timeout [60010 60642 60033 58941 60159 59656 60277 60879 ] 480597 -Use_TimeoutStarverX [13 10 18 16 5 4 12 11 ] 89 -Use_TimeoutStarverS [14 25 24 25 6 15 16 13 ] 138 -Use_TimeoutNoStarvers [76634 76926 77048 76616 76982 76971 76777 76512 ] 614466 +Transient_Local_GETS_Last_Token [2 0 1 4 0 1 0 1 ] 9 +Persistent_GETX [40243 40235 40237 40452 40236 40319 40323 40294 ] 322339 +Persistent_GETS [74022 73973 73853 73992 74071 73914 74014 74024 ] 591863 +Persistent_GETS_Last_Token [0 0 1 1 1 0 0 0 ] 3 +Own_Lock_or_Unlock [145427 145484 145601 145247 145384 145459 145355 145374 ] 1163331 +Request_Timeout [60159 59656 60277 60879 60010 60642 60033 58941 ] 480597 +Use_TimeoutStarverX [5 4 12 11 13 10 18 16 ] 89 +Use_TimeoutStarverS [6 15 16 13 14 25 24 25 ] 138 +Use_TimeoutNoStarvers [76982 76971 76777 76512 76634 76926 77048 76616 ] 614466 Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load [49920 50179 50054 49912 50234 49878 50162 50102 ] 400441 +NP Load [50234 49878 50162 50102 49920 50179 50054 49912 ] 400441 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [26907 26962 27158 26896 26908 27274 26779 26582 ] 215466 +NP Store [26908 27274 26779 26582 26907 26962 27158 26896 ] 215466 NP Atomic [0 0 0 0 0 0 0 0 ] 0 -NP Data_Shared [11 6 6 5 15 7 5 4 ] 59 -NP Data_Owner [18 16 11 12 21 15 12 10 ] 115 -NP Data_All_Tokens [3722 3775 3791 3803 3905 3708 3801 3744 ] 30249 +NP Data_Shared [15 7 5 4 11 6 6 5 ] 59 +NP Data_Owner [21 15 12 10 18 16 11 12 ] 115 +NP Data_All_Tokens [3905 3708 3801 3744 3722 3775 3791 3803 ] 30249 NP Ack [0 0 1 0 0 0 1 0 ] 2 NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETX [188229 188157 187989 188206 188213 187862 188356 188542 ] 1505554 +NP Transient_Local_GETX [188213 187862 188356 188542 188229 188157 187989 188206 ] 1505554 NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETS [349922 349655 349776 349964 349628 349983 349669 349728 ] 2798325 +NP Transient_Local_GETS [349628 349983 349669 349728 349922 349655 349776 349964 ] 2798325 NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -NP Own_Lock_or_Unlock [126881 126869 126992 126955 126885 126871 126751 126905 ] 1015109 +NP Own_Lock_or_Unlock [126885 126871 126751 126905 126881 126869 126992 126955 ] 1015109 -I Load [0 0 1 0 0 0 0 0 ] 1 +I Load [0 0 0 0 0 0 1 0 ] 1 I Ifetch [0 0 0 0 0 0 0 0 ] 0 I Store [0 0 0 0 0 0 0 0 ] 0 I Atomic [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [173 164 159 191 183 170 174 180 ] 1394 +I L1_Replacement [183 170 174 180 173 164 159 191 ] 1394 I Data_Shared [0 0 0 0 0 0 0 0 ] 0 I Data_Owner [0 0 0 0 0 0 0 0 ] 0 I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 I Ack [0 0 0 0 0 0 0 0 ] 0 I Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1 +I Transient_Local_GETX [0 0 0 1 0 0 0 0 ] 1 I Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETS [0 1 0 0 0 0 0 2 ] 3 +I Transient_Local_GETS [0 0 0 2 0 1 0 0 ] 3 I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Persistent_GETX [1 0 0 0 0 0 0 0 ] 1 -I Persistent_GETS [0 0 0 0 1 1 0 1 ] 3 +I Persistent_GETX [0 0 0 0 1 0 0 0 ] 1 +I Persistent_GETS [1 1 0 1 0 0 0 0 ] 3 I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Own_Lock_or_Unlock [1 0 0 0 0 1 0 0 ] 2 +I Own_Lock_or_Unlock [0 1 0 0 1 0 0 0 ] 2 -S Load [0 0 0 0 0 0 1 0 ] 1 +S Load [0 0 1 0 0 0 0 0 ] 1 S Ifetch [0 0 0 0 0 0 0 0 ] 0 S Store [0 0 0 0 0 0 0 0 ] 0 S Atomic [0 0 0 0 0 0 0 0 ] 0 -S L1_Replacement [272 281 241 271 249 252 274 244 ] 2084 -S Data_Shared [1 0 0 1 1 0 2 0 ] 5 +S L1_Replacement [249 252 274 244 272 281 241 271 ] 2084 +S Data_Shared [1 0 2 0 1 0 0 1 ] 5 S Data_Owner [0 0 0 0 0 0 0 0 ] 0 -S Data_All_Tokens [0 0 0 0 0 1 0 0 ] 1 +S Data_All_Tokens [0 1 0 0 0 0 0 0 ] 1 S Ack [0 0 0 0 0 0 0 0 ] 0 S Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETX [2 0 0 1 1 2 1 1 ] 8 +S Transient_Local_GETX [1 2 1 1 2 0 0 1 ] 8 S Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS [1 0 0 0 0 0 0 0 ] 1 +S Transient_Local_GETS [0 0 0 0 1 0 0 0 ] 1 S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS_Last_Token [0 1 0 1 2 0 1 4 ] 9 -S Persistent_GETX [0 0 0 0 1 0 0 0 ] 1 -S Persistent_GETS [0 1 1 0 0 0 0 0 ] 2 -S Persistent_GETS_Last_Token [1 0 0 0 0 0 1 1 ] 3 +S Transient_Local_GETS_Last_Token [2 0 1 4 0 1 0 1 ] 9 +S Persistent_GETX [1 0 0 0 0 0 0 0 ] 1 +S Persistent_GETS [0 0 0 0 0 1 1 0 ] 2 +S Persistent_GETS_Last_Token [0 0 1 1 1 0 0 0 ] 3 S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 O Store [0 0 0 0 0 0 0 0 ] 0 O Atomic [0 0 0 0 0 0 0 0 ] 0 -O L1_Replacement [132 145 111 121 133 127 116 134 ] 1019 +O L1_Replacement [133 127 116 134 132 145 111 121 ] 1019 O Data_Shared [0 0 0 0 0 0 0 0 ] 0 -O Data_All_Tokens [0 0 0 1 1 0 0 0 ] 2 +O Data_All_Tokens [1 0 0 0 0 0 0 1 ] 2 O Ack [0 0 0 0 0 0 0 0 ] 0 -O Ack_All_Tokens [1 0 0 0 0 0 0 0 ] 1 +O Ack_All_Tokens [0 0 0 0 1 0 0 0 ] 1 O Transient_GETX [0 0 0 0 0 0 0 0 ] 0 O Transient_Local_GETX [0 1 0 0 0 1 0 0 ] 2 O Transient_GETS [0 0 0 0 0 0 0 0 ] 0 @@ -521,90 +521,90 @@ O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -O Persistent_GETS [0 0 0 0 0 1 0 1 ] 2 +O Persistent_GETS [0 1 0 1 0 0 0 0 ] 2 O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -O Own_Lock_or_Unlock [12 13 10 6 12 15 17 13 ] 98 +O Own_Lock_or_Unlock [12 15 17 13 12 13 10 6 ] 98 -M Load [5 3 8 10 5 2 3 5 ] 41 +M Load [5 2 3 5 5 3 8 10 ] 41 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [3 4 0 0 3 2 5 4 ] 21 +M Store [3 2 5 4 3 4 0 0 ] 21 M Atomic [0 0 0 0 0 0 0 0 ] 0 -M L1_Replacement [49519 49733 49702 49527 49847 49500 49774 49713 ] 397315 +M L1_Replacement [49847 49500 49774 49713 49519 49733 49702 49527 ] 397315 M Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETX [46 55 33 55 50 36 52 40 ] 367 +M Transient_Local_GETX [50 36 52 40 46 55 33 55 ] 367 M Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETS [80 96 81 84 83 71 76 96 ] 667 -M Persistent_GETX [21 13 18 11 25 26 14 21 ] 149 -M Persistent_GETS [36 38 28 29 27 31 33 32 ] 254 -M Own_Lock_or_Unlock [1221 1249 1131 1186 1187 1229 1293 1200 ] 9696 +M Transient_Local_GETS [83 71 76 96 80 96 81 84 ] 667 +M Persistent_GETX [25 26 14 21 21 13 18 11 ] 149 +M Persistent_GETS [27 31 33 32 36 38 28 29 ] 254 +M Own_Lock_or_Unlock [1187 1229 1293 1200 1221 1249 1131 1186 ] 9696 -MM Load [3 2 3 1 1 5 2 7 ] 24 +MM Load [1 5 2 7 3 2 3 1 ] 24 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [0 3 1 3 5 1 1 1 ] 15 +MM Store [5 1 1 1 0 3 1 3 ] 15 MM Atomic [0 0 0 0 0 0 0 0 ] 0 -MM L1_Replacement [26847 26914 27102 26811 26851 27209 26736 26508 ] 214978 +MM L1_Replacement [26851 27209 26736 26508 26847 26914 27102 26811 ] 214978 MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETX [17 21 25 28 31 33 27 28 ] 210 +MM Transient_Local_GETX [31 33 27 28 17 21 25 28 ] 210 MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETS [49 33 36 42 45 36 37 41 ] 319 -MM Persistent_GETX [10 10 8 7 11 11 10 17 ] 84 -MM Persistent_GETS [9 12 15 22 12 17 17 14 ] 118 -MM Own_Lock_or_Unlock [668 648 636 641 712 667 685 670 ] 5327 +MM Transient_Local_GETS [45 36 37 41 49 33 36 42 ] 319 +MM Persistent_GETX [11 11 10 17 10 10 8 7 ] 84 +MM Persistent_GETS [12 17 17 14 9 12 15 22 ] 118 +MM Own_Lock_or_Unlock [712 667 685 670 668 648 636 641 ] 5327 -M_W Load [3 4 3 4 2 4 5 3 ] 28 +M_W Load [2 4 5 3 3 4 3 4 ] 28 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [1 2 2 1 1 2 0 0 ] 9 +M_W Store [1 2 0 0 1 2 2 1 ] 9 M_W Atomic [0 0 0 0 0 0 0 0 ] 0 -M_W L1_Replacement [288045 288216 288197 287895 291266 289622 289644 290259 ] 2313144 +M_W L1_Replacement [291266 289622 289644 290259 288045 288216 288197 287895 ] 2313144 M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETX [39 45 33 39 42 27 30 37 ] 292 +M_W Transient_Local_GETX [42 27 30 37 39 45 33 39 ] 292 M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETS [63 60 78 60 66 79 75 88 ] 569 -M_W Persistent_GETX [4 6 8 8 3 4 4 5 ] 42 -M_W Persistent_GETS [7 15 15 17 5 11 11 4 ] 85 -M_W Own_Lock_or_Unlock [496 466 481 459 469 479 514 489 ] 3853 -M_W Use_TimeoutStarverX [5 7 11 10 4 4 5 6 ] 52 -M_W Use_TimeoutStarverS [8 17 17 17 5 11 12 6 ] 93 -M_W Use_TimeoutNoStarvers [49705 49940 49862 49706 50035 49666 49954 49907 ] 398775 +M_W Transient_Local_GETS [66 79 75 88 63 60 78 60 ] 569 +M_W Persistent_GETX [3 4 4 5 4 6 8 8 ] 42 +M_W Persistent_GETS [5 11 11 4 7 15 15 17 ] 85 +M_W Own_Lock_or_Unlock [469 479 514 489 496 466 481 459 ] 3853 +M_W Use_TimeoutStarverX [4 4 5 6 5 7 11 10 ] 52 +M_W Use_TimeoutStarverS [5 11 12 6 8 17 17 17 ] 93 +M_W Use_TimeoutNoStarvers [50035 49666 49954 49907 49705 49940 49862 49706 ] 398775 M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [3 5 1 1 5 1 0 2 ] 18 +MM_W Load [5 1 0 2 3 5 1 1 ] 18 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [2 2 1 1 2 0 0 0 ] 8 +MM_W Store [2 0 0 0 2 2 1 1 ] 8 MM_W Atomic [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_Replacement [158304 157087 158031 155857 155942 158074 153918 152634 ] 1249847 +MM_W L1_Replacement [155942 158074 153918 152634 158304 157087 158031 155857 ] 1249847 MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETX [23 21 20 27 23 18 18 26 ] 176 +MM_W Transient_Local_GETX [23 18 18 26 23 21 20 27 ] 176 MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETS [33 40 44 43 30 45 31 43 ] 309 -MM_W Persistent_GETX [7 2 7 6 1 0 6 4 ] 33 -MM_W Persistent_GETS [6 7 7 8 1 3 3 7 ] 42 -MM_W Own_Lock_or_Unlock [270 272 278 235 292 270 253 231 ] 2101 -MM_W Use_TimeoutStarverX [8 3 7 6 1 0 7 5 ] 37 -MM_W Use_TimeoutStarverS [6 8 7 8 1 4 4 7 ] 45 -MM_W Use_TimeoutNoStarvers [26929 26986 27186 26910 26947 27305 26823 26605 ] 215691 +MM_W Transient_Local_GETS [30 45 31 43 33 40 44 43 ] 309 +MM_W Persistent_GETX [1 0 6 4 7 2 7 6 ] 33 +MM_W Persistent_GETS [1 3 3 7 6 7 7 8 ] 42 +MM_W Own_Lock_or_Unlock [292 270 253 231 270 272 278 235 ] 2101 +MM_W Use_TimeoutStarverX [1 0 7 5 8 3 7 6 ] 37 +MM_W Use_TimeoutStarverS [1 4 4 7 6 8 7 8 ] 45 +MM_W Use_TimeoutNoStarvers [26947 27305 26823 26605 26929 26986 27186 26910 ] 215691 MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Atomic [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [295320 295503 296204 292704 293340 295809 291989 287885 ] 2348754 +IM L1_Replacement [293340 295809 291989 287885 295320 295503 296204 292704 ] 2348754 IM Data_Shared [0 0 0 0 0 0 0 0 ] 0 -IM Data_Owner [0 0 0 2 1 1 0 1 ] 5 -IM Data_All_Tokens [26941 26992 27198 26921 26946 27305 26829 26615 ] 215747 -IM Ack [2 2 3 1 1 0 1 0 ] 10 +IM Data_Owner [1 1 0 1 0 0 0 2 ] 5 +IM Data_All_Tokens [26946 27305 26829 26615 26941 26992 27198 26921 ] 215747 +IM Ack [1 0 1 0 2 2 3 1 ] 10 IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETX [93 87 89 96 90 84 90 94 ] 723 +IM Transient_Local_GETX [90 84 90 94 93 87 89 96 ] 723 IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETS [146 154 150 165 147 144 177 153 ] 1236 +IM Transient_Local_GETS [147 144 177 153 146 154 150 165 ] 1236 IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Persistent_GETX [26 33 22 19 29 27 22 27 ] 205 -IM Persistent_GETS [48 53 57 63 36 39 50 42 ] 388 +IM Persistent_GETX [29 27 22 27 26 33 22 19 ] 205 +IM Persistent_GETS [36 39 50 42 48 53 57 63 ] 388 IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Own_Lock_or_Unlock [5492 5408 5402 5471 5483 5506 5529 5327 ] 43618 -IM Request_Timeout [21245 21018 20732 20087 20923 21057 21290 20719 ] 167071 +IM Own_Lock_or_Unlock [5483 5506 5529 5327 5492 5408 5402 5471 ] 43618 +IM Request_Timeout [20923 21057 21290 20719 21245 21018 20732 20087 ] 167071 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -631,11 +631,11 @@ OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 OM Atomic [0 0 0 0 0 0 0 0 ] 0 -OM L1_Replacement [0 0 0 0 0 0 0 1 ] 1 +OM L1_Replacement [0 0 0 1 0 0 0 0 ] 1 OM Data_Shared [0 0 0 0 0 0 0 0 ] 0 -OM Data_All_Tokens [0 0 0 1 0 0 0 0 ] 1 +OM Data_All_Tokens [0 0 0 0 0 0 0 1 ] 1 OM Ack [0 0 0 0 0 0 0 0 ] 0 -OM Ack_All_Tokens [0 0 0 1 1 1 0 1 ] 4 +OM Ack_All_Tokens [1 1 0 1 0 0 0 1 ] 4 OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 OM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 @@ -645,89 +645,89 @@ OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -OM Own_Lock_or_Unlock [0 0 0 0 0 0 0 1 ] 1 -OM Request_Timeout [0 0 0 0 0 0 0 1 ] 1 +OM Own_Lock_or_Unlock [0 0 0 1 0 0 0 0 ] 1 +OM Request_Timeout [0 0 0 1 0 0 0 0 ] 1 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS Atomic [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [541488 544959 546694 544234 548020 544678 548767 548504 ] 4367344 -IS Data_Shared [230 226 196 226 219 212 230 206 ] 1745 -IS Data_Owner [53 50 30 38 51 58 40 39 ] 359 -IS Data_All_Tokens [49717 49963 49887 49732 50045 49683 49970 49916 ] 398913 -IS Ack [1 0 0 0 0 0 1 0 ] 2 +IS L1_Replacement [548020 544678 548767 548504 541488 544959 546694 544234 ] 4367344 +IS Data_Shared [219 212 230 206 230 226 196 226 ] 1745 +IS Data_Owner [51 58 40 39 53 50 30 38 ] 359 +IS Data_All_Tokens [50045 49683 49970 49916 49717 49963 49887 49732 ] 398913 +IS Ack [0 0 1 0 1 0 0 0 ] 2 IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETX [153 161 153 166 152 168 140 160 ] 1253 +IS Transient_Local_GETX [152 168 140 160 153 161 153 166 ] 1253 IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETS [322 311 302 273 287 298 300 291 ] 2384 +IS Transient_Local_GETS [287 298 300 291 322 311 302 273 ] 2384 IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Persistent_GETX [49 57 59 56 36 37 47 56 ] 397 -IS Persistent_GETS [105 100 104 97 86 112 92 95 ] 791 +IS Persistent_GETX [36 37 47 56 49 57 59 56 ] 397 +IS Persistent_GETS [86 112 92 95 105 100 104 97 ] 791 IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Own_Lock_or_Unlock [9893 10088 9969 9961 9989 10016 10115 9985 ] 80016 -IS Request_Timeout [38271 39197 38932 38452 38867 38204 38667 39766 ] 310356 +IS Own_Lock_or_Unlock [9989 10016 10115 9985 9893 10088 9969 9961 ] 80016 +IS Request_Timeout [38867 38204 38667 39766 38271 39197 38932 38452 ] 310356 -I_L Load [83 66 66 88 84 77 81 64 ] 609 +I_L Load [84 77 81 64 83 66 66 88 ] 609 I_L Ifetch [0 0 0 0 0 0 0 0 ] 0 -I_L Store [37 34 41 29 41 33 56 35 ] 306 +I_L Store [41 33 56 35 37 34 41 29 ] 306 I_L Atomic [0 0 0 0 0 0 0 0 ] 0 -I_L L1_Replacement [249 203 258 317 206 148 234 329 ] 1944 +I_L L1_Replacement [206 148 234 329 249 203 258 317 ] 1944 I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -I_L Data_All_Tokens [18 8 7 4 41 45 23 18 ] 164 +I_L Data_All_Tokens [41 45 23 18 18 8 7 4 ] 164 I_L Ack [0 0 0 0 0 0 0 0 ] 0 I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETX [225 228 230 227 221 233 222 225 ] 1811 +I_L Transient_Local_GETX [221 233 222 225 225 228 230 227 ] 1811 I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETS [432 455 463 416 445 439 441 435 ] 3526 +I_L Transient_Local_GETS [445 439 441 435 432 455 463 416 ] 3526 I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Persistent_GETX [40099 40175 40167 40156 40137 40125 40121 40304 ] 321284 -I_L Persistent_GETS [73818 73632 73718 73704 73854 73741 73628 73761 ] 589856 +I_L Persistent_GETX [40137 40125 40121 40304 40099 40175 40167 40156 ] 321284 +I_L Persistent_GETS [73854 73741 73628 73761 73818 73632 73718 73704 ] 589856 I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Own_Lock_or_Unlock [60 54 66 65 57 63 57 71 ] 493 +I_L Own_Lock_or_Unlock [57 63 57 71 60 54 66 65 ] 493 S_L Load [0 0 0 0 0 0 0 0 ] 0 S_L Ifetch [0 0 0 0 0 0 0 0 ] 0 S_L Store [0 0 0 0 0 0 0 0 ] 0 S_L Atomic [0 0 0 0 0 0 0 0 ] 0 -S_L L1_Replacement [24 80 47 56 42 35 64 55 ] 403 +S_L L1_Replacement [42 35 64 55 24 80 47 56 ] 403 S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 S_L Ack [0 0 0 0 0 0 0 0 ] 0 S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -S_L Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1 +S_L Transient_Local_GETX [0 0 0 1 0 0 0 0 ] 1 S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -S_L Persistent_GETS [5 17 10 14 0 4 7 6 ] 63 +S_L Persistent_GETS [0 4 7 6 5 17 10 14 ] 63 S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S_L Own_Lock_or_Unlock [45 56 46 46 32 43 46 40 ] 354 +S_L Own_Lock_or_Unlock [32 43 46 40 45 56 46 46 ] 354 IM_L Load [0 0 0 0 0 0 0 0 ] 0 IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IM_L Store [0 0 0 0 0 0 0 0 ] 0 IM_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IM_L L1_Replacement [691 852 843 772 616 650 788 576 ] 5788 +IM_L L1_Replacement [616 650 788 576 691 852 843 772 ] 5788 IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IM_L Data_All_Tokens [1 3 0 0 1 1 5 1 ] 12 +IM_L Data_All_Tokens [1 1 5 1 1 3 0 0 ] 12 IM_L Ack [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETX [1 0 1 1 0 0 0 0 ] 3 +IM_L Transient_Local_GETX [0 0 0 0 1 0 1 1 ] 3 IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETS [0 0 0 1 0 1 1 2 ] 5 +IM_L Transient_Local_GETS [0 1 1 2 0 0 0 1 ] 5 IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM_L Persistent_GETX [10 10 10 6 0 3 2 4 ] 45 -IM_L Persistent_GETS [13 15 23 29 0 2 7 11 ] 100 -IM_L Own_Lock_or_Unlock [110 117 120 111 105 98 123 103 ] 887 -IM_L Request_Timeout [153 194 147 151 92 153 130 128 ] 1148 +IM_L Persistent_GETX [0 3 2 4 10 10 10 6 ] 45 +IM_L Persistent_GETS [0 2 7 11 13 15 23 29 ] 100 +IM_L Own_Lock_or_Unlock [105 98 123 103 110 117 120 111 ] 887 +IM_L Request_Timeout [92 153 130 128 153 194 147 151 ] 1148 SM_L Load [0 0 0 0 0 0 0 0 ] 0 SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -754,21 +754,21 @@ IS_L Load [0 0 0 0 0 0 0 0 ] 0 IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IS_L Store [0 0 0 0 0 0 0 0 ] 0 IS_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IS_L L1_Replacement [1490 1388 1535 2021 1362 1369 1430 1388 ] 11983 -IS_L Data_Shared [0 1 0 1 1 0 0 0 ] 3 +IS_L L1_Replacement [1362 1369 1430 1388 1490 1388 1535 2021 ] 11983 +IS_L Data_Shared [1 0 0 0 0 1 0 1 ] 3 IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IS_L Data_All_Tokens [2 3 5 2 1 0 2 3 ] 18 +IS_L Data_All_Tokens [1 0 2 3 2 3 5 2 ] 18 IS_L Ack [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS_L Transient_Local_GETX [0 0 0 1 0 1 1 0 ] 3 +IS_L Transient_Local_GETX [0 1 1 0 0 0 0 1 ] 3 IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_Local_GETS [0 0 0 2 0 0 0 2 ] 4 IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS_L Persistent_GETX [9 13 24 25 0 2 11 14 ] 98 -IS_L Persistent_GETS [24 24 36 41 0 11 5 18 ] 159 -IS_L Own_Lock_or_Unlock [235 219 224 238 204 226 218 212 ] 1776 -IS_L Request_Timeout [341 233 222 251 277 242 190 265 ] 2021 +IS_L Persistent_GETX [0 2 11 14 9 13 24 25 ] 98 +IS_L Persistent_GETS [0 11 5 18 24 24 36 41 ] 159 +IS_L Own_Lock_or_Unlock [204 226 218 212 235 219 224 238 ] 1776 +IS_L Request_Timeout [277 242 190 265 341 233 222 251 ] 2021 Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index a3fb5c8c8..03befb105 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -1,10 +1,10 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 system.cpu3: completed 10000 read, 5373 write accesses @610961 system.cpu5: completed 10000 read, 5365 write accesses @611018 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index b734bebaa..e78fa46c2 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 9 2012 13:32:04 -gem5 started Nov 10 2012 16:12:27 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Apr 9 2013 02:08:32 +gem5 started Apr 9 2013 02:09:19 +gem5 executing on vein command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index dd34a57f3..b069d8895 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.006151 # Nu sim_ticks 6151475 # Number of ticks simulated final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 48262 # Simulator tick rate (ticks/s) -host_mem_usage 426016 # Number of bytes of host memory used -host_seconds 127.46 # Real time elapsed on the host +host_tick_rate 38159 # Simulator tick rate (ticks/s) +host_mem_usage 250384 # Number of bytes of host memory used +host_seconds 161.21 # Real time elapsed on the host system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index b267456f4..bc0318858 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 6b441c9a6..a532ed140 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -1,24 +1,24 @@ -Real time: Feb/02/2013 08:12:46 +Real time: Apr/09/2013 02:01:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 101 -Elapsed_time_in_minutes: 1.68333 -Elapsed_time_in_hours: 0.0280556 -Elapsed_time_in_days: 0.00116898 +Elapsed_time_in_seconds: 168 +Elapsed_time_in_minutes: 2.8 +Elapsed_time_in_hours: 0.0466667 +Elapsed_time_in_days: 0.00194444 -Virtual_time_in_seconds: 101.34 -Virtual_time_in_minutes: 1.689 -Virtual_time_in_hours: 0.02815 -Virtual_time_in_days: 0.00117292 +Virtual_time_in_seconds: 167.14 +Virtual_time_in_minutes: 2.78567 +Virtual_time_in_hours: 0.0464278 +Virtual_time_in_days: 0.00193449 Ruby_current_time: 5795833 Ruby_start_time: 0 Ruby_cycles: 5795833 -mbytes_resident: 70.6875 -mbytes_total: 410.68 -resident_ratio: 0.172152 +mbytes_resident: 64.7773 +mbytes_total: 244.449 +resident_ratio: 0.264993 ruby_cycles_executed: [ 5795834 5795834 5795834 5795834 5795834 5795834 5795834 5795834 ] @@ -87,13 +87,13 @@ Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation Resource Usage -------------- page_size: 4096 -user_time: 101 +user_time: 166 system_time: 0 -page_reclaims: 10145 -page_faults: 0 +page_reclaims: 17148 +page_faults: 3 swaps: 0 -block_inputs: 16 -block_outputs: 320 +block_inputs: 776 +block_outputs: 312 Network Stats ------------- @@ -358,56 +358,56 @@ Cache Stats: system.ruby.l1_cntrl0.L2cacheMemory --- L1Cache --- - Event Counts - -Load [50263 50069 50306 49970 50266 50315 50271 50212 ] 401672 +Load [50266 50315 50271 50212 50263 50069 50306 49970 ] 401672 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27014 27080 27361 27054 26762 27215 27106 27272 ] 216864 -L2_Replacement [77135 76978 77528 76877 76877 77378 77204 77319 ] 617296 -L1_to_L2 [842565 841910 845488 839694 839684 843217 843158 840771 ] 6736487 -Trigger_L2_to_L1D [66 89 69 72 75 72 99 79 ] 621 +Store [26762 27215 27106 27272 27014 27080 27361 27054 ] 216864 +L2_Replacement [76877 77378 77204 77319 77135 76978 77528 76877 ] 617296 +L1_to_L2 [839684 843217 843158 840771 842565 841910 845488 839694 ] 6736487 +Trigger_L2_to_L1D [75 72 99 79 66 89 69 72 ] 621 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [66 89 69 72 75 72 99 79 ] 621 -Other_GETX [189522 189457 189156 189455 189761 189309 189417 189262 ] 1515339 -Other_GETS [350354 350578 350311 350671 350360 350304 350380 350430 ] 2803388 -Merged_GETS [48 51 52 58 67 47 56 60 ] 439 +Complete_L2_to_L1 [75 72 99 79 66 89 69 72 ] 621 +Other_GETX [189761 189309 189417 189262 189522 189457 189156 189455 ] 1515339 +Other_GETS [350360 350304 350380 350430 350354 350578 350311 350671 ] 2803388 +Merged_GETS [67 47 56 60 48 51 52 58 ] 439 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [537124 535993 539952 535252 535380 538939 537669 538458 ] 4298767 -Shared_Ack [51 74 50 68 61 58 61 63 ] 486 -Data [2998 3000 2981 3082 2873 3045 2960 3027 ] 23966 -Shared_Data [1045 1094 1078 1123 1060 1048 1056 1053 ] 8557 -Exclusive_Data [73100 72896 73480 72683 72953 73296 73198 73248 ] 584854 -Writeback_Ack [72792 72564 73169 72340 72619 73022 72821 72965 ] 582292 +Ack [535380 538939 537669 538458 537124 535993 539952 535252 ] 4298767 +Shared_Ack [61 58 61 63 51 74 50 68 ] 486 +Data [2873 3045 2960 3027 2998 3000 2981 3082 ] 23966 +Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557 +Exclusive_Data [72953 73296 73198 73248 73100 72896 73480 72683 ] 584854 +Writeback_Ack [72619 73022 72821 72965 72792 72564 73169 72340 ] 582292 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [1091 1156 1120 1180 1114 1096 1109 1107 ] 8973 -All_acks_no_sharers [76052 75834 76419 75708 75773 76294 76104 76221 ] 608405 +All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973 +All_acks_no_sharers [75773 76294 76104 76221 76052 75834 76419 75708 ] 608405 Flush_line [0 0 0 0 0 0 0 0 ] 0 Block_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load [50191 49971 50219 49868 50174 50224 50155 50116 ] 400918 +I Load [50174 50224 50155 50116 50191 49971 50219 49868 ] 400918 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [26955 27016 27320 27019 26713 27165 27060 27213 ] 216461 -I L2_Replacement [1437 1441 1373 1479 1339 1403 1446 1410 ] 11328 -I L1_to_L2 [292 256 261 290 263 295 253 281 ] 2191 -I Trigger_L2_to_L1D [0 4 2 3 3 0 1 2 ] 15 +I Store [26713 27165 27060 27213 26955 27016 27320 27019 ] 216461 +I L2_Replacement [1339 1403 1446 1410 1437 1441 1373 1479 ] 11328 +I L1_to_L2 [263 295 253 281 292 256 261 290 ] 2191 +I Trigger_L2_to_L1D [3 0 1 2 0 4 2 3 ] 15 I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [188572 188504 188287 188527 188850 188385 188473 188307 ] 1507905 -I Other_GETS [348712 348887 348575 348998 348728 348598 348711 348779 ] 2789988 +I Other_GETX [188850 188385 188473 188307 188572 188504 188287 188527 ] 1507905 +I Other_GETS [348728 348598 348711 348779 348712 348887 348575 348998 ] 2789988 I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 I Invalidate [0 0 0 0 0 0 0 0 ] 0 I Flush_line [0 0 0 0 0 0 0 0 ] 0 -S Load [0 0 1 1 1 1 2 0 ] 6 +S Load [1 1 2 0 0 0 1 1 ] 6 S Ifetch [0 0 0 0 0 0 0 0 ] 0 S Store [0 0 0 0 0 0 0 0 ] 0 -S L2_Replacement [2906 2973 2984 3058 2919 2953 2937 2944 ] 23674 -S L1_to_L2 [2929 2993 3006 3086 2947 2984 2973 2971 ] 23889 -S Trigger_L2_to_L1D [0 2 3 6 2 5 4 1 ] 23 +S L2_Replacement [2919 2953 2937 2944 2906 2973 2984 3058 ] 23674 +S L1_to_L2 [2947 2984 2973 2971 2929 2993 3006 3086 ] 23889 +S Trigger_L2_to_L1D [2 5 4 1 0 2 3 6 ] 23 S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [32 28 25 31 29 31 38 33 ] 247 -S Other_GETS [52 62 79 49 57 56 59 72 ] 486 +S Other_GETX [29 31 38 33 32 28 25 31 ] 247 +S Other_GETS [57 56 59 72 52 62 79 49 ] 486 S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 S Invalidate [0 0 0 0 0 0 0 0 ] 0 @@ -415,106 +415,106 @@ S Flush_line [0 0 0 0 0 0 0 0 ] 0 O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [0 0 0 0 1 0 0 0 ] 1 -O L2_Replacement [972 1001 1015 980 1037 1033 990 999 ] 8027 -O L1_to_L2 [190 218 217 198 204 188 202 199 ] 1616 -O Trigger_L2_to_L1D [0 1 0 2 0 2 0 1 ] 6 +O Store [1 0 0 0 0 0 0 0 ] 1 +O L2_Replacement [1037 1033 990 999 972 1001 1015 980 ] 8027 +O L1_to_L2 [204 188 202 199 190 218 217 198 ] 1616 +O Trigger_L2_to_L1D [0 2 0 1 0 1 0 2 ] 6 O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [3 11 9 5 7 8 8 5 ] 56 -O Other_GETS [13 9 9 13 9 14 12 12 ] 91 -O Merged_GETS [3 1 1 1 4 3 2 6 ] 21 +O Other_GETX [7 8 8 5 3 11 9 5 ] 56 +O Other_GETS [9 14 12 12 13 9 9 13 ] 91 +O Merged_GETS [4 3 2 6 3 1 1 1 ] 21 O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 O Invalidate [0 0 0 0 0 0 0 0 ] 0 O Flush_line [0 0 0 0 0 0 0 0 ] 0 -M Load [2 11 6 2 7 3 5 6 ] 42 +M Load [7 3 5 6 2 11 6 2 ] 42 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [2 9 1 2 5 5 2 5 ] 31 -M L2_Replacement [45746 45407 45688 45251 45647 45669 45641 45593 ] 364642 -M L1_to_L2 [46980 46700 46933 46507 46941 46960 46927 46865 ] 374813 -M Trigger_L2_to_L1D [41 55 37 40 49 40 60 51 ] 373 +M Store [5 5 2 5 2 9 1 2 ] 31 +M L2_Replacement [45647 45669 45641 45593 45746 45407 45688 45251 ] 364642 +M L1_to_L2 [46941 46960 46927 46865 46980 46700 46933 46507 ] 374813 +M Trigger_L2_to_L1D [49 40 60 51 41 55 37 40 ] 373 M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [520 540 502 539 529 518 538 533 ] 4219 -M Other_GETS [931 962 974 928 983 999 944 950 ] 7671 -M Merged_GETS [27 27 29 42 39 27 33 31 ] 255 +M Other_GETX [529 518 538 533 520 540 502 539 ] 4219 +M Other_GETS [983 999 944 950 931 962 974 928 ] 7671 +M Merged_GETS [39 27 33 31 27 27 29 42 ] 255 M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 M Invalidate [0 0 0 0 0 0 0 0 ] 0 M Flush_line [0 0 0 0 0 0 0 0 ] 0 -MM Load [6 4 3 7 4 8 2 6 ] 40 +MM Load [4 8 2 6 6 4 3 7 ] 40 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [4 4 1 2 0 5 1 2 ] 19 -MM L2_Replacement [26074 26156 26468 26109 25935 26320 26190 26373 ] 209625 -MM L1_to_L2 [26817 26905 27186 26874 26603 27029 26955 27088 ] 215457 -MM Trigger_L2_to_L1D [25 27 27 21 21 25 34 24 ] 204 +MM Store [0 5 1 2 4 4 1 2 ] 19 +MM L2_Replacement [25935 26320 26190 26373 26074 26156 26468 26109 ] 209625 +MM L1_to_L2 [26603 27029 26955 27088 26817 26905 27186 26874 ] 215457 +MM Trigger_L2_to_L1D [21 25 34 24 25 27 27 21 ] 204 MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [334 308 279 308 296 298 301 320 ] 2444 -MM Other_GETS [548 558 561 599 481 549 562 521 ] 4379 -MM Merged_GETS [18 23 21 15 23 16 21 23 ] 160 +MM Other_GETX [296 298 301 320 334 308 279 308 ] 2444 +MM Other_GETS [481 549 562 521 548 558 561 599 ] 4379 +MM Merged_GETS [23 16 21 23 18 23 21 15 ] 160 MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MM Invalidate [0 0 0 0 0 0 0 0 ] 0 MM Flush_line [0 0 0 0 0 0 0 0 ] 0 -IR Load [0 1 1 2 1 0 1 0 ] 6 +IR Load [1 0 1 0 0 1 1 2 ] 6 IR Ifetch [0 0 0 0 0 0 0 0 ] 0 -IR Store [0 3 1 1 2 0 0 2 ] 9 -IR L1_to_L2 [0 11 0 2 0 0 0 0 ] 13 +IR Store [2 0 0 2 0 3 1 1 ] 9 +IR L1_to_L2 [0 0 0 0 0 11 0 2 ] 13 IR Flush_line [0 0 0 0 0 0 0 0 ] 0 -SR Load [0 1 2 4 2 3 4 1 ] 17 +SR Load [2 3 4 1 0 1 2 4 ] 17 SR Ifetch [0 0 0 0 0 0 0 0 ] 0 -SR Store [0 1 1 2 0 2 0 0 ] 6 -SR L1_to_L2 [0 0 0 13 0 3 0 0 ] 16 +SR Store [0 2 0 0 0 1 1 2 ] 6 +SR L1_to_L2 [0 3 0 0 0 0 0 13 ] 16 SR Flush_line [0 0 0 0 0 0 0 0 ] 0 -OR Load [0 1 0 2 0 1 0 1 ] 5 +OR Load [0 1 0 1 0 1 0 2 ] 5 OR Ifetch [0 0 0 0 0 0 0 0 ] 0 -OR Store [0 0 0 0 0 1 0 0 ] 1 +OR Store [0 1 0 0 0 0 0 0 ] 1 OR L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MR Load [20 37 27 31 32 27 42 33 ] 249 +MR Load [32 27 42 33 20 37 27 31 ] 249 MR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MR Store [21 18 10 9 17 13 18 18 ] 124 -MR L1_to_L2 [95 89 59 56 91 56 102 86 ] 634 +MR Store [17 13 18 18 21 18 10 9 ] 124 +MR L1_to_L2 [91 56 102 86 95 89 59 56 ] 634 MR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MMR Load [16 16 18 14 14 17 26 16 ] 137 +MMR Load [14 17 26 16 16 16 18 14 ] 137 MMR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMR Store [9 11 9 7 7 8 8 8 ] 67 -MMR L1_to_L2 [49 33 49 34 59 75 46 41 ] 386 +MMR Store [7 8 8 8 9 11 9 7 ] 67 +MMR L1_to_L2 [59 75 46 41 49 33 49 34 ] 386 MMR Flush_line [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [268056 268579 269306 265306 264282 266577 267890 269848 ] 2139844 -IM Other_GETX [9 15 10 13 7 12 10 15 ] 91 -IM Other_GETS [14 14 22 16 21 19 20 24 ] 150 +IM L1_to_L2 [264282 266577 267890 269848 268056 268579 269306 265306 ] 2139844 +IM Other_GETX [7 12 10 15 9 15 10 13 ] 91 +IM Other_GETS [21 19 20 24 14 14 22 16 ] 150 IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [185299 185768 187652 185613 183448 186647 185973 187270 ] 1487670 -IM Data [1105 1091 1048 1112 985 1103 1041 1101 ] 8586 -IM Exclusive_Data [25848 25928 26272 25907 25729 26061 26018 26114 ] 207877 +IM Ack [183448 186647 185973 187270 185299 185768 187652 185613 ] 1487670 +IM Data [985 1103 1041 1101 1105 1091 1048 1112 ] 8586 +IM Exclusive_Data [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877 IM Flush_line [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [0 1 7 0 0 11 0 0 ] 19 +SM L1_to_L2 [0 11 0 0 0 1 7 0 ] 19 SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [0 7 7 14 0 14 0 0 ] 42 -SM Data [0 1 1 2 0 2 0 0 ] 6 +SM Ack [0 14 0 0 0 7 7 14 ] 42 +SM Data [0 2 0 0 0 1 1 2 ] 6 SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 SM Flush_line [0 0 0 0 0 0 0 0 ] 0 @@ -529,92 +529,92 @@ OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [0 0 0 0 7 7 0 0 ] 14 +OM Ack [7 7 0 0 0 0 0 0 ] 14 OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [0 0 0 0 1 1 0 0 ] 2 +OM All_acks_no_sharers [1 1 0 0 0 0 0 0 ] 2 OM Flush_line [0 0 0 0 0 0 0 0 ] 0 ISM Load [0 0 0 0 0 0 0 0 ] 0 ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 ISM Store [0 0 0 0 0 0 0 0 ] 0 ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM L1_to_L2 [1 0 14 1 2 0 0 0 ] 18 -ISM Ack [100 106 115 87 104 73 108 117 ] 810 -ISM All_acks_no_sharers [1105 1092 1049 1114 985 1105 1041 1101 ] 8592 +ISM L1_to_L2 [2 0 0 0 1 0 14 1 ] 18 +ISM Ack [104 73 108 117 100 106 115 87 ] 810 +ISM All_acks_no_sharers [985 1105 1041 1101 1105 1092 1049 1114 ] 8592 ISM Flush_line [0 0 0 0 0 0 0 0 ] 0 M_W Load [0 0 0 0 0 0 0 0 ] 0 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [478 492 525 425 539 550 404 533 ] 3946 -M_W Ack [1665 1631 1583 1553 1618 1714 1578 1607 ] 12949 -M_W All_acks_no_sharers [47252 46968 47208 46776 47224 47235 47179 47134 ] 376976 +M_W L1_to_L2 [539 550 404 533 478 492 525 425 ] 3946 +M_W Ack [1618 1714 1578 1607 1665 1631 1583 1553 ] 12949 +M_W All_acks_no_sharers [47224 47235 47179 47134 47252 46968 47208 46776 ] 376976 M_W Flush_line [0 0 0 0 0 0 0 0 ] 0 MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 MM_W Store [0 0 0 0 0 0 0 0 ] 0 MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [798 840 931 893 1079 875 817 808 ] 7041 -MM_W Ack [2427 2427 2583 2531 2578 2557 2465 2275 ] 19843 -MM_W All_acks_no_sharers [25848 25928 26272 25907 25729 26061 26018 26114 ] 207877 +MM_W L1_to_L2 [1079 875 817 808 798 840 931 893 ] 7041 +MM_W Ack [2578 2557 2465 2275 2427 2427 2583 2531 ] 19843 +MM_W All_acks_no_sharers [25729 26061 26018 26114 25848 25928 26272 25907 ] 207877 MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [494908 493655 495921 494562 495283 496463 495139 490703 ] 3956634 -IS Other_GETX [21 22 15 15 18 25 17 24 ] 157 -IS Other_GETS [36 40 28 38 33 30 33 29 ] 267 +IS L1_to_L2 [495283 496463 495139 490703 494908 493655 495921 494562 ] 3956634 +IS Other_GETX [18 25 17 24 21 22 15 15 ] 157 +IS Other_GETS [33 30 33 29 36 40 28 38 ] 267 IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [344619 343059 344891 342300 344673 344866 344538 344199 ] 2753145 -IS Shared_Ack [48 68 45 64 57 54 57 59 ] 452 -IS Data [1893 1908 1932 1968 1888 1940 1919 1926 ] 15374 -IS Shared_Data [1045 1094 1078 1123 1060 1048 1056 1053 ] 8557 -IS Exclusive_Data [47252 46968 47208 46776 47224 47235 47180 47134 ] 376977 +IS Ack [344673 344866 344538 344199 344619 343059 344891 342300 ] 2753145 +IS Shared_Ack [57 54 57 59 48 68 45 64 ] 452 +IS Data [1888 1940 1919 1926 1893 1908 1932 1968 ] 15374 +IS Shared_Data [1060 1048 1056 1053 1045 1094 1078 1123 ] 8557 +IS Exclusive_Data [47224 47235 47180 47134 47252 46968 47208 46776 ] 376977 IS Flush_line [0 0 0 0 0 0 0 0 ] 0 SS Load [0 0 0 0 0 0 0 0 ] 0 SS Ifetch [0 0 0 0 0 0 0 0 ] 0 SS Store [0 0 0 0 0 0 0 0 ] 0 SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [767 881 901 1161 1116 874 1194 1064 ] 7958 -SS Ack [3014 2995 3121 3154 2952 3061 3007 2990 ] 24294 -SS Shared_Ack [3 6 5 4 4 4 4 4 ] 34 -SS All_acks [1091 1156 1120 1180 1114 1096 1109 1107 ] 8973 -SS All_acks_no_sharers [1847 1846 1890 1911 1834 1892 1866 1872 ] 14958 +SS L1_to_L2 [1116 874 1194 1064 767 881 901 1161 ] 7958 +SS Ack [2952 3061 3007 2990 3014 2995 3121 3154 ] 24294 +SS Shared_Ack [4 4 4 4 3 6 5 4 ] 34 +SS All_acks [1114 1096 1109 1107 1091 1156 1120 1180 ] 8973 +SS All_acks_no_sharers [1834 1892 1866 1872 1847 1846 1890 1911 ] 14958 SS Flush_line [0 0 0 0 0 0 0 0 ] 0 -OI Load [0 0 0 0 0 1 2 0 ] 3 +OI Load [0 1 2 0 0 0 0 0 ] 3 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 OI Store [0 0 0 0 0 0 0 0 ] 0 OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OI Other_GETX [0 0 0 0 0 0 2 0 ] 2 -OI Other_GETS [0 0 0 1 1 0 0 1 ] 3 -OI Merged_GETS [0 0 1 0 0 0 0 0 ] 1 +OI Other_GETX [0 0 2 0 0 0 0 0 ] 2 +OI Other_GETS [1 0 0 1 0 0 0 1 ] 3 +OI Merged_GETS [0 0 0 0 0 0 1 0 ] 1 OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [1020 1047 1077 1009 1085 1073 1027 1041 ] 8379 +OI Writeback_Ack [1085 1073 1027 1041 1020 1047 1077 1009 ] 8379 OI Flush_line [0 0 0 0 0 0 0 0 ] 0 -MI Load [12 8 7 12 10 11 14 12 ] 86 +MI Load [10 11 14 12 12 8 7 12 ] 86 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [9 7 8 7 7 4 4 12 ] 58 +MI Store [7 4 4 12 9 7 8 7 ] 58 MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [31 29 29 17 25 32 30 25 ] 218 -MI Other_GETS [48 46 63 29 47 39 39 42 ] 353 -MI Merged_GETS [0 0 0 0 1 1 0 0 ] 2 +MI Other_GETX [25 32 30 25 31 29 29 17 ] 218 +MI Other_GETS [47 39 39 42 48 46 63 29 ] 353 +MI Merged_GETS [1 1 0 0 0 0 0 0 ] 2 MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [71741 71488 72063 71314 71509 71917 71762 71899 ] 573693 +MI Writeback_Ack [71509 71917 71762 71899 71741 71488 72063 71314 ] 573693 MI Flush_line [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -627,44 +627,44 @@ II Other_GETS [0 0 0 0 0 0 0 0 ] 0 II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [31 29 29 17 25 32 32 25 ] 220 +II Writeback_Ack [25 32 32 25 31 29 29 17 ] 220 II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Flush_line [0 0 0 0 0 0 0 0 ] 0 -IT Load [0 0 0 2 0 0 1 0 ] 3 +IT Load [0 0 1 0 0 0 0 2 ] 3 IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [0 1 0 0 0 0 0 1 ] 2 +IT Store [0 0 0 1 0 1 0 0 ] 2 IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [0 11 9 3 0 0 0 1 ] 24 -IT Complete_L2_to_L1 [0 4 2 3 3 0 1 2 ] 15 +IT L1_to_L2 [0 0 0 1 0 11 9 3 ] 24 +IT Complete_L2_to_L1 [3 0 1 2 0 4 2 3 ] 15 -ST Load [0 1 0 3 0 1 0 0 ] 5 +ST Load [0 1 0 0 0 1 0 3 ] 5 ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [0 0 0 1 0 0 0 0 ] 1 +ST Store [0 0 0 0 0 0 0 1 ] 1 ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [0 0 5 25 10 21 7 9 ] 77 -ST Complete_L2_to_L1 [0 2 3 6 2 5 4 1 ] 23 +ST L1_to_L2 [10 21 7 9 0 0 5 25 ] 77 +ST Complete_L2_to_L1 [2 5 4 1 0 2 3 6 ] 23 -OT Load [0 0 0 2 0 0 0 0 ] 2 +OT Load [0 0 0 0 0 0 0 2 ] 2 OT Ifetch [0 0 0 0 0 0 0 0 ] 0 OT Store [0 0 0 0 0 0 0 0 ] 0 OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [0 0 0 0 0 0 0 6 ] 6 -OT Complete_L2_to_L1 [0 1 0 2 0 2 0 1 ] 6 +OT L1_to_L2 [0 0 0 6 0 0 0 0 ] 6 +OT Complete_L2_to_L1 [0 2 0 1 0 1 0 2 ] 6 -MT Load [10 14 13 15 13 7 10 13 ] 95 +MT Load [13 7 10 13 10 14 13 15 ] 95 MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [9 7 5 2 6 9 9 9 ] 56 +MT Store [6 9 9 9 9 7 5 2 ] 56 MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [115 155 80 166 179 117 164 171 ] 1147 -MT Complete_L2_to_L1 [41 55 37 40 49 40 60 51 ] 373 +MT L1_to_L2 [179 117 164 171 115 155 80 166 ] 1147 +MT Complete_L2_to_L1 [49 40 60 51 41 55 37 40 ] 373 -MMT Load [6 4 9 5 8 11 7 8 ] 58 +MMT Load [8 11 7 8 6 4 9 5 ] 58 MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [5 3 5 2 4 3 4 2 ] 28 +MMT Store [4 3 4 2 5 3 5 2 ] 28 MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [90 91 78 92 86 139 85 97 ] 758 -MMT Complete_L2_to_L1 [25 27 27 21 21 25 34 24 ] 204 +MMT L1_to_L2 [86 139 85 97 90 91 78 92 ] 758 +MMT Complete_L2_to_L1 [21 25 34 24 25 27 27 21 ] 204 MI_F Load [0 0 0 0 0 0 0 0 ] 0 MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 214b383d8..a5b70c1a7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,10 +1,10 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 system.cpu5: completed 10000 read, 5516 write accesses @570851 system.cpu3: completed 10000 read, 5324 write accesses @572812 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 4d9ff64ba..899bc58f8 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 9 2012 13:19:47 -gem5 started Nov 10 2012 16:10:39 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Apr 9 2013 01:58:20 +gem5 started Apr 9 2013 01:59:05 +gem5 executing on vein command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 6ab2ef6a1..85ee95513 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.005796 # Nu sim_ticks 5795833 # Number of ticks simulated final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 46095 # Simulator tick rate (ticks/s) -host_mem_usage 425996 # Number of bytes of host memory used -host_seconds 125.74 # Real time elapsed on the host +host_tick_rate 34597 # Simulator tick rate (ticks/s) +host_mem_usage 250320 # Number of bytes of host memory used +host_seconds 167.53 # Real time elapsed on the host system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index a222111a4..c91f50916 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index b9dfd36b8..0acb649d4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Feb/02/2013 08:07:46 +Real time: Apr/09/2013 01:55:51 Profiler Stats -------------- -Elapsed_time_in_seconds: 77 -Elapsed_time_in_minutes: 1.28333 -Elapsed_time_in_hours: 0.0213889 -Elapsed_time_in_days: 0.000891204 +Elapsed_time_in_seconds: 52 +Elapsed_time_in_minutes: 0.866667 +Elapsed_time_in_hours: 0.0144444 +Elapsed_time_in_days: 0.000601852 -Virtual_time_in_seconds: 37.08 -Virtual_time_in_minutes: 0.618 -Virtual_time_in_hours: 0.0103 -Virtual_time_in_days: 0.000429167 +Virtual_time_in_seconds: 52.85 +Virtual_time_in_minutes: 0.880833 +Virtual_time_in_hours: 0.0146806 +Virtual_time_in_days: 0.00061169 Ruby_current_time: 8664886 Ruby_start_time: 0 Ruby_cycles: 8664886 -mbytes_resident: 70.5195 -mbytes_total: 410.59 -resident_ratio: 0.17178 +mbytes_resident: 64.3945 +mbytes_total: 243.918 +resident_ratio: 0.264001 ruby_cycles_executed: [ 8664887 8664887 8664887 8664887 8664887 8664887 8664887 8664887 ] @@ -81,13 +81,13 @@ Total_delay_cycles: [binsize: 1 max: 22 count: 1237687 average: 0.00723931 | sta Resource Usage -------------- page_size: 4096 -user_time: 36 +user_time: 52 system_time: 0 -page_reclaims: 10596 +page_reclaims: 17037 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 240 +block_inputs: 24 +block_outputs: 200 Network Stats ------------- @@ -251,42 +251,42 @@ Cache Stats: system.ruby.l1_cntrl0.cacheMemory --- L1Cache --- - Event Counts - -Load [50004 50305 50279 50578 50370 50258 50037 49672 ] 401503 +Load [50370 50258 50037 49672 50004 50305 50279 50578 ] 401503 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27327 27084 27075 26703 27007 26935 26787 27153 ] 216071 -Data [77329 77385 77352 77277 77375 77192 76821 76821 ] 617552 -Fwd_GETX [995 1001 998 1019 1048 1042 1040 1065 ] 8208 +Store [27007 26935 26787 27153 27327 27084 27075 26703 ] 216071 +Data [77375 77192 76821 76821 77329 77385 77352 77277 ] 617552 +Fwd_GETX [1048 1042 1040 1065 995 1001 998 1019 ] 8208 Inv [0 0 0 0 0 0 0 0 ] 0 -Replacement [77327 77385 77350 77277 77373 77189 76820 76821 ] 617542 -Writeback_Ack [76330 76378 76350 76253 76323 76144 75775 75751 ] 609304 -Writeback_Nack [327 344 310 313 342 322 324 341 ] 2623 +Replacement [77373 77189 76820 76821 77327 77385 77350 77277 ] 617542 +Writeback_Ack [76323 76144 75775 75751 76330 76378 76350 76253 ] 609304 +Writeback_Nack [342 322 324 341 327 344 310 313 ] 2623 - Transitions - -I Load [50004 50305 50279 50578 50370 50258 50037 49672 ] 401503 +I Load [50370 50258 50037 49672 50004 50305 50279 50578 ] 401503 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [27327 27084 27075 26703 27007 26935 26787 27153 ] 216071 +I Store [27007 26935 26787 27153 27327 27084 27075 26703 ] 216071 I Inv [0 0 0 0 0 0 0 0 ] 0 -I Replacement [668 657 688 706 706 720 716 724 ] 5585 +I Replacement [706 720 716 724 668 657 688 706 ] 5585 -II Writeback_Nack [327 344 310 313 342 322 324 341 ] 2623 +II Writeback_Nack [342 322 324 341 327 344 310 313 ] 2623 M Load [0 0 0 0 0 0 0 0 ] 0 M Ifetch [0 0 0 0 0 0 0 0 ] 0 M Store [0 0 0 0 0 0 0 0 ] 0 -M Fwd_GETX [668 657 688 706 706 720 716 724 ] 5585 +M Fwd_GETX [706 720 716 724 668 657 688 706 ] 5585 M Inv [0 0 0 0 0 0 0 0 ] 0 -M Replacement [76659 76728 76662 76571 76667 76469 76104 76097 ] 611957 +M Replacement [76667 76469 76104 76097 76659 76728 76662 76571 ] 611957 -MI Fwd_GETX [327 344 310 313 342 322 324 341 ] 2623 +MI Fwd_GETX [342 322 324 341 327 344 310 313 ] 2623 MI Inv [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [76330 76378 76350 76253 76323 76144 75775 75751 ] 609304 +MI Writeback_Ack [76323 76144 75775 75751 76330 76378 76350 76253 ] 609304 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Data [50002 50301 50278 50576 50370 50258 50035 49669 ] 401489 +IS Data [50370 50258 50035 49669 50002 50301 50278 50576 ] 401489 -IM Data [27327 27084 27074 26701 27005 26934 26786 27152 ] 216063 +IM Data [27005 26934 26786 27152 27327 27084 27074 26701 ] 216063 Cache Stats: system.ruby.l1_cntrl1.cacheMemory system.ruby.l1_cntrl1.cacheMemory_total_misses: 77193 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr index e99373646..082530ace 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,10 +1,10 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 system.cpu4: completed 10000 read, 5267 write accesses @855219 system.cpu7: completed 10000 read, 5381 write accesses @861031 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 2794962f3..3495746a7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:02:54 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Apr 9 2013 01:51:40 +gem5 started Apr 9 2013 01:54:58 +gem5 executing on vein command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index e20a29e2b..f571f66e4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.008665 # Nu sim_ticks 8664886 # Number of ticks simulated final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 109516 # Simulator tick rate (ticks/s) -host_mem_usage 425456 # Number of bytes of host memory used -host_seconds 79.12 # Real time elapsed on the host +host_tick_rate 164643 # Simulator tick rate (ticks/s) +host_mem_usage 249776 # Number of bytes of host memory used +host_seconds 52.63 # Real time elapsed on the host system.ruby.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads |