diff options
Diffstat (limited to 'tests/quick/se')
184 files changed, 3927 insertions, 2167 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index c1097366b..8be59c81c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=InOrderCPU children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload @@ -36,7 +42,7 @@ activity=0 branchPred=system.cpu.branchPred cachePorts=2 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 div16Latency=1 div16RepeatRate=1 @@ -66,6 +72,7 @@ multRepeatRate=1 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= stageTracing=false stageWidth=4 switched_out=false @@ -84,11 +91,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -96,10 +101,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -110,22 +115,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -136,12 +150,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -154,10 +177,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -168,16 +191,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -196,7 +227,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -207,10 +238,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -244,6 +284,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index fa2cf12dd..b50e34b75 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorde gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:17:23 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:26 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 18737000 because target called exit() +Exiting @ tick 25046000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 765a5ac14..dce50f688 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -454,10 +477,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -468,16 +491,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -496,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -507,10 +538,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -544,6 +584,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 800d8e238..ab8450b87 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 14:39:12 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:26 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 16032500 because target called exit() +Exiting @ tick 20671000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index 38823b11f..3d9687a29 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -88,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -99,11 +108,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index dc9014a9b..1fb01db1e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:33:24 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:26 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index 4a9baa29b..90c3ec168 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 49b667e6c..11de6c024 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:03:49 +Real time: Sep/22/2013 05:27:18 Profiler Stats -------------- -Elapsed_time_in_seconds: 8 -Elapsed_time_in_minutes: 0.133333 -Elapsed_time_in_hours: 0.00222222 -Elapsed_time_in_days: 9.25926e-05 +Elapsed_time_in_seconds: 6 +Elapsed_time_in_minutes: 0.1 +Elapsed_time_in_hours: 0.00166667 +Elapsed_time_in_days: 6.94444e-05 -Virtual_time_in_seconds: 0.65 -Virtual_time_in_minutes: 0.0108333 -Virtual_time_in_hours: 0.000180556 -Virtual_time_in_days: 7.52315e-06 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 Ruby_current_time: 138616 Ruby_start_time: 0 Ruby_cycles: 138616 -mbytes_resident: 76.7812 -mbytes_total: 170.938 -resident_ratio: 0.4492 +mbytes_resident: 70.7109 +mbytes_total: 125.152 +resident_ratio: 0.564999 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr index e45cd058f..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr @@ -1,2 +1,6 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 226bed9cc..5fac9bcf7 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:01:54 -gem5 started Sep 1 2012 14:02:52 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:27:02 +gem5 started Sep 22 2013 05:27:12 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index 966ab8ba5..5c3b6f3c7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 871 # Simulator instruction rate (inst/s) -host_op_rate 871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18892 # Simulator tick rate (ticks/s) -host_mem_usage 175044 # Number of bytes of host memory used -host_seconds 7.34 # Real time elapsed on the host +host_inst_rate 1056 # Simulator instruction rate (inst/s) +host_op_rate 1056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22900 # Simulator tick rate (ticks/s) +host_mem_usage 128160 # Number of bytes of host memory used +host_seconds 6.05 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits @@ -101,6 +101,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6392 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10584 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2312 +system.ruby.network.msg_count.Control 8850 +system.ruby.network.msg_count.Request_Control 3123 +system.ruby.network.msg_count.Response_Data 9681 +system.ruby.network.msg_count.Response_Control 14286 +system.ruby.network.msg_count.Writeback_Data 864 +system.ruby.network.msg_count.Writeback_Control 867 +system.ruby.network.msg_byte.Control 70800 +system.ruby.network.msg_byte.Request_Control 24984 +system.ruby.network.msg_byte.Response_Data 697032 +system.ruby.network.msg_byte.Response_Control 114288 +system.ruby.network.msg_byte.Writeback_Data 62208 +system.ruby.network.msg_byte.Writeback_Control 6936 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -272,18 +284,6 @@ system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00% system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00% -system.ruby.network.msg_count.Control 8850 -system.ruby.network.msg_count.Request_Control 3123 -system.ruby.network.msg_count.Response_Data 9681 -system.ruby.network.msg_count.Response_Control 14286 -system.ruby.network.msg_count.Writeback_Data 864 -system.ruby.network.msg_count.Writeback_Control 867 -system.ruby.network.msg_byte.Control 70800 -system.ruby.network.msg_byte.Request_Control 24984 -system.ruby.network.msg_byte.Response_Data 697032 -system.ruby.network.msg_byte.Response_Control 114288 -system.ruby.network.msg_byte.Writeback_Data 62208 -system.ruby.network.msg_byte.Writeback_Control 6936 system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index e1b2b2ccf..454f386da 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 94f281262..f796e6d64 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:04:57 +Real time: Sep/22/2013 05:36:35 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.74 -Virtual_time_in_minutes: 0.0123333 -Virtual_time_in_hours: 0.000205556 -Virtual_time_in_days: 8.56481e-06 +Virtual_time_in_seconds: 0.52 +Virtual_time_in_minutes: 0.00866667 +Virtual_time_in_hours: 0.000144444 +Virtual_time_in_days: 6.01852e-06 Ruby_current_time: 117611 Ruby_start_time: 0 Ruby_cycles: 117611 -mbytes_resident: 78.3398 -mbytes_total: 172.082 -resident_ratio: 0.45527 +mbytes_resident: 72.1758 +mbytes_total: 126.289 +resident_ratio: 0.571513 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr index e45cd058f..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -1,2 +1,6 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 0b27bcc43..7aebf91e4 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:10:16 -gem5 started Sep 1 2012 14:11:17 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:36:12 +gem5 started Sep 22 2013 05:36:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 3af3398f7..a243c0ad3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19051 # Simulator instruction rate (inst/s) -host_op_rate 19050 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 350596 # Simulator tick rate (ticks/s) -host_mem_usage 176216 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host +host_inst_rate 22489 # Simulator instruction rate (inst/s) +host_op_rate 22487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 413867 # Simulator tick rate (ticks/s) +host_mem_usage 129324 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits @@ -98,6 +98,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 17488 system.ruby.network.routers3.msg_bytes.Writeback_Control::2 7192 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 19768 +system.ruby.network.msg_count.Request_Control 7413 +system.ruby.network.msg_count.Response_Data 6654 +system.ruby.network.msg_count.ResponseL2hit_Data 759 +system.ruby.network.msg_count.Writeback_Data 4644 +system.ruby.network.msg_count.Writeback_Control 17379 +system.ruby.network.msg_count.Unblock_Control 7413 +system.ruby.network.msg_byte.Request_Control 59304 +system.ruby.network.msg_byte.Response_Data 479088 +system.ruby.network.msg_byte.ResponseL2hit_Data 54648 +system.ruby.network.msg_byte.Writeback_Data 334368 +system.ruby.network.msg_byte.Writeback_Control 139032 +system.ruby.network.msg_byte.Unblock_Control 59304 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -277,18 +289,6 @@ system.ruby.l1_cntrl0.IM.Exclusive_Data 191 0.00% 0.00% system.ruby.l1_cntrl0.OM.All_acks 191 0.00% 0.00% system.ruby.l1_cntrl0.IS.Exclusive_Data 1171 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 1354 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 7413 -system.ruby.network.msg_count.Response_Data 6654 -system.ruby.network.msg_count.ResponseL2hit_Data 759 -system.ruby.network.msg_count.Writeback_Data 4644 -system.ruby.network.msg_count.Writeback_Control 17379 -system.ruby.network.msg_count.Unblock_Control 7413 -system.ruby.network.msg_byte.Request_Control 59304 -system.ruby.network.msg_byte.Response_Data 479088 -system.ruby.network.msg_byte.ResponseL2hit_Data 54648 -system.ruby.network.msg_byte.Writeback_Data 334368 -system.ruby.network.msg_byte.Writeback_Control 139032 -system.ruby.network.msg_byte.Unblock_Control 59304 system.ruby.l2_cntrl0.L1_GETS 1171 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 191 0.00% 0.00% system.ruby.l2_cntrl0.L1_PUTX 1354 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 5bdc495d8..98cbeddd9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 442dd3499..878f29081 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:04:43 +Real time: Sep/22/2013 05:45:04 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 4 +Elapsed_time_in_minutes: 0.0666667 +Elapsed_time_in_hours: 0.00111111 +Elapsed_time_in_days: 4.62963e-05 -Virtual_time_in_seconds: 0.6 -Virtual_time_in_minutes: 0.01 -Virtual_time_in_hours: 0.000166667 -Virtual_time_in_days: 6.94444e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 113627 Ruby_start_time: 0 Ruby_cycles: 113627 -mbytes_resident: 75.7461 -mbytes_total: 170.031 -resident_ratio: 0.445506 +mbytes_resident: 69.5977 +mbytes_total: 124.223 +resident_ratio: 0.560265 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr index e45cd058f..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -1,2 +1,6 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index c5809ae71..972ce6ed2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:38:07 -gem5 started Sep 9 2012 13:38:15 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:44:48 +gem5 started Sep 22 2013 05:44:59 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index be82f1052..da21a8b1c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27885 # Simulator instruction rate (inst/s) -host_op_rate 27883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 495765 # Simulator tick rate (ticks/s) -host_mem_usage 174116 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 1471 # Simulator instruction rate (inst/s) +host_op_rate 1471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26154 # Simulator tick rate (ticks/s) +host_mem_usage 127208 # Number of bytes of host memory used +host_seconds 4.34 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 1312 # Number of cache demand hits @@ -82,6 +82,18 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 113976 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7736 +system.ruby.network.msg_count.Request_Control 7731 +system.ruby.network.msg_count.Response_Data 3534 +system.ruby.network.msg_count.ResponseL2hit_Data 612 +system.ruby.network.msg_count.Response_Control 3 +system.ruby.network.msg_count.Writeback_Data 4749 +system.ruby.network.msg_count.Writeback_Control 2901 +system.ruby.network.msg_byte.Request_Control 61848 +system.ruby.network.msg_byte.Response_Data 254448 +system.ruby.network.msg_byte.ResponseL2hit_Data 44064 +system.ruby.network.msg_byte.Response_Control 24 +system.ruby.network.msg_byte.Writeback_Data 341928 +system.ruby.network.msg_byte.Writeback_Control 23208 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -230,18 +242,6 @@ system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00% system.ruby.l1_cntrl0.SM.Data_All_Tokens 20 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_Shared 161 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_All_Tokens 1010 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 7731 -system.ruby.network.msg_count.Response_Data 3534 -system.ruby.network.msg_count.ResponseL2hit_Data 612 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 4749 -system.ruby.network.msg_count.Writeback_Control 2901 -system.ruby.network.msg_byte.Request_Control 61848 -system.ruby.network.msg_byte.Response_Data 254448 -system.ruby.network.msg_byte.ResponseL2hit_Data 44064 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 341928 -system.ruby.network.msg_byte.Writeback_Control 23208 system.ruby.l2_cntrl0.L1_GETS 1122 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETS_Last_Token 49 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 211 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 0bd814b7d..5efa528b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index 167b82c92..23062d8c8 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:02:57 +Real time: Sep/22/2013 05:18:00 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.8 -Virtual_time_in_minutes: 0.0133333 -Virtual_time_in_hours: 0.000222222 -Virtual_time_in_days: 9.25926e-06 +Virtual_time_in_seconds: 0.41 +Virtual_time_in_minutes: 0.00683333 +Virtual_time_in_hours: 0.000113889 +Virtual_time_in_days: 4.74537e-06 Ruby_current_time: 93341 Ruby_start_time: 0 Ruby_cycles: 93341 -mbytes_resident: 75.5039 -mbytes_total: 169.965 -resident_ratio: 0.444255 +mbytes_resident: 69.2852 +mbytes_total: 124.195 +resident_ratio: 0.557873 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr index e45cd058f..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -1,2 +1,6 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index d752652fe..2f946fb64 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 13:53:26 -gem5 started Sep 1 2012 13:54:22 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:17:28 +gem5 started Sep 22 2013 05:18:00 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 0558d3744..2decdb14a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19138 # Simulator instruction rate (inst/s) -host_op_rate 19136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279518 # Simulator tick rate (ticks/s) -host_mem_usage 174048 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 35131 # Simulator instruction rate (inst/s) +host_op_rate 35128 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 513083 # Simulator tick rate (ticks/s) +host_mem_usage 127180 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits @@ -83,6 +83,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.msg_count.Request_Control 3477 +system.ruby.network.msg_count.Response_Data 3477 +system.ruby.network.msg_count.Writeback_Data 660 +system.ruby.network.msg_count.Writeback_Control 9627 +system.ruby.network.msg_count.Unblock_Control 3477 +system.ruby.network.msg_byte.Request_Control 27816 +system.ruby.network.msg_byte.Response_Data 250344 +system.ruby.network.msg_byte.Writeback_Data 47520 +system.ruby.network.msg_byte.Writeback_Control 77016 +system.ruby.network.msg_byte.Unblock_Control 27816 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -227,16 +237,6 @@ system.ruby.l1_cntrl0.MI.Store 27 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 1143 0.00% 0.00% system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 70 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 3477 -system.ruby.network.msg_count.Response_Data 3477 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9627 -system.ruby.network.msg_count.Unblock_Control 3477 -system.ruby.network.msg_byte.Request_Control 27816 -system.ruby.network.msg_byte.Response_Data 250344 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77016 -system.ruby.network.msg_byte.Unblock_Control 27816 system.ruby.dir_cntrl0.GETX 186 0.00% 0.00% system.ruby.dir_cntrl0.GETS 1022 0.00% 0.00% system.ruby.dir_cntrl0.PUT 1143 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 3473bb901..5c6bf177e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index 92d7e563b..07bf20a9b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:03:31 +Real time: Sep/28/2013 03:05:29 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.61 -Virtual_time_in_minutes: 0.0101667 -Virtual_time_in_hours: 0.000169444 -Virtual_time_in_days: 7.06019e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 Ruby_current_time: 143853 Ruby_start_time: 0 Ruby_cycles: 143853 -mbytes_resident: 75.2305 -mbytes_total: 169.531 -resident_ratio: 0.443779 +mbytes_resident: 69.0312 +mbytes_total: 123.75 +resident_ratio: 0.557828 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr index 5da3f0737..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr @@ -1,6 +1,6 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 070ea92d3..cedef1822 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:45:23 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:27 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 8d6d3a37f..c8df30ebb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32139 # Simulator instruction rate (inst/s) -host_op_rate 32136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 723384 # Simulator tick rate (ticks/s) -host_mem_usage 173604 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 29196 # Simulator instruction rate (inst/s) +host_op_rate 29194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 657174 # Simulator tick rate (ticks/s) +host_mem_usage 126724 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits @@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 13840 system.ruby.network.routers2.msg_bytes.Data::2 124272 system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.msg_count.Control 5190 +system.ruby.network.msg_count.Data 5178 +system.ruby.network.msg_count.Response_Data 5190 +system.ruby.network.msg_count.Writeback_Control 5178 +system.ruby.network.msg_byte.Control 41520 +system.ruby.network.msg_byte.Data 372816 +system.ruby.network.msg_byte.Response_Data 373680 +system.ruby.network.msg_byte.Writeback_Control 41424 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -157,14 +165,6 @@ system.ruby.l1_cntrl0.M.Replacement 1726 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 1726 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 1457 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 273 0.00% 0.00% -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 system.ruby.dir_cntrl0.GETX 1730 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 1726 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 1730 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index c41a1c22b..595a8159f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -119,10 +143,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -133,17 +157,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -160,7 +193,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -171,11 +204,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index fc43aac0c..b5f87b785 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:45:47 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:26 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 5c71a7c03..c5e8a16e6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -454,10 +477,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -468,16 +491,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -496,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -507,10 +538,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -544,6 +584,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 4ea05c228..c47a79c1f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 14:39:13 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:27 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 9350000 because target called exit() +Exiting @ tick 11933500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 81a4de4d4..b66459c3a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -88,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -99,11 +108,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index d9d6fa90d..034bc5823 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:45:35 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:27 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 759014fd3..362eaad12 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 110acb8ec..1ce96a614 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:03:38 +Real time: Sep/22/2013 05:27:18 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 5 +Elapsed_time_in_minutes: 0.0833333 +Elapsed_time_in_hours: 0.00138889 +Elapsed_time_in_days: 5.78704e-05 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.38 +Virtual_time_in_minutes: 0.00633333 +Virtual_time_in_hours: 0.000105556 +Virtual_time_in_days: 4.39815e-06 Ruby_current_time: 52575 Ruby_start_time: 0 Ruby_cycles: 52575 -mbytes_resident: 74.6133 -mbytes_total: 168.652 -resident_ratio: 0.442432 +mbytes_resident: 68.4688 +mbytes_total: 122.754 +resident_ratio: 0.557772 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr index 31ae36f2e..492f3e68f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr @@ -1,3 +1,7 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index b08e9f127..5722711d2 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:01:54 -gem5 started Sep 1 2012 14:03:04 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:27:02 +gem5 started Sep 22 2013 05:27:13 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 784ed2300..5b945b27d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52575 # Number of ticks simulated final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 7067 # Simulator instruction rate (inst/s) -host_op_rate 7067 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144167 # Simulator tick rate (ticks/s) -host_mem_usage 172704 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 459 # Simulator instruction rate (inst/s) +host_op_rate 459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9361 # Simulator tick rate (ticks/s) +host_mem_usage 125832 # Number of bytes of host memory used +host_seconds 5.62 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits @@ -100,6 +100,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3384 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 616 +system.ruby.network.msg_count.Control 3357 +system.ruby.network.msg_count.Request_Control 1293 +system.ruby.network.msg_count.Response_Data 3666 +system.ruby.network.msg_count.Response_Control 5220 +system.ruby.network.msg_count.Writeback_Data 327 +system.ruby.network.msg_count.Writeback_Control 231 +system.ruby.network.msg_byte.Control 26856 +system.ruby.network.msg_byte.Request_Control 10344 +system.ruby.network.msg_byte.Response_Data 263952 +system.ruby.network.msg_byte.Response_Control 41760 +system.ruby.network.msg_byte.Writeback_Data 23544 +system.ruby.network.msg_byte.Writeback_Control 1848 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -271,18 +283,6 @@ system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00% system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00% -system.ruby.network.msg_count.Control 3357 -system.ruby.network.msg_count.Request_Control 1293 -system.ruby.network.msg_count.Response_Data 3666 -system.ruby.network.msg_count.Response_Control 5220 -system.ruby.network.msg_count.Writeback_Data 327 -system.ruby.network.msg_count.Writeback_Control 231 -system.ruby.network.msg_byte.Control 26856 -system.ruby.network.msg_byte.Request_Control 10344 -system.ruby.network.msg_byte.Response_Data 263952 -system.ruby.network.msg_byte.Response_Control 41760 -system.ruby.network.msg_byte.Writeback_Data 23544 -system.ruby.network.msg_byte.Writeback_Control 1848 system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 3660a930a..1cc47929f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index ccd8b498a..fb852a546 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:04:53 +Real time: Sep/22/2013 05:36:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 7 +Elapsed_time_in_minutes: 0.116667 +Elapsed_time_in_hours: 0.00194444 +Elapsed_time_in_days: 8.10185e-05 -Virtual_time_in_seconds: 0.55 -Virtual_time_in_minutes: 0.00916667 -Virtual_time_in_hours: 0.000152778 -Virtual_time_in_days: 6.36574e-06 +Virtual_time_in_seconds: 0.39 +Virtual_time_in_minutes: 0.0065 +Virtual_time_in_hours: 0.000108333 +Virtual_time_in_days: 4.51389e-06 Ruby_current_time: 44968 Ruby_start_time: 0 Ruby_cycles: 44968 -mbytes_resident: 75.9648 -mbytes_total: 169.809 -resident_ratio: 0.447379 +mbytes_resident: 69.9375 +mbytes_total: 124.047 +resident_ratio: 0.563799 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr index 31ae36f2e..492f3e68f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -1,3 +1,7 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 0eff99821..e2683dd74 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:10:16 -gem5 started Sep 1 2012 14:11:29 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:36:12 +gem5 started Sep 22 2013 05:36:23 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 88933afb4..811c48f82 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10546 # Simulator instruction rate (inst/s) -host_op_rate 10545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183989 # Simulator tick rate (ticks/s) -host_mem_usage 174912 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 423 # Simulator instruction rate (inst/s) +host_op_rate 423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7389 # Simulator tick rate (ticks/s) +host_mem_usage 127028 # Number of bytes of host memory used +host_seconds 6.09 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits @@ -98,6 +98,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 6512 system.ruby.network.routers3.msg_bytes.Writeback_Control::2 2648 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 7464 +system.ruby.network.msg_count.Request_Control 2799 +system.ruby.network.msg_count.Response_Data 2538 +system.ruby.network.msg_count.ResponseL2hit_Data 261 +system.ruby.network.msg_count.Writeback_Data 1734 +system.ruby.network.msg_count.Writeback_Control 6447 +system.ruby.network.msg_count.Unblock_Control 2798 +system.ruby.network.msg_byte.Request_Control 22392 +system.ruby.network.msg_byte.Response_Data 182736 +system.ruby.network.msg_byte.ResponseL2hit_Data 18792 +system.ruby.network.msg_byte.Writeback_Data 124848 +system.ruby.network.msg_byte.Writeback_Control 51576 +system.ruby.network.msg_byte.Unblock_Control 22384 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -276,18 +288,6 @@ system.ruby.l1_cntrl0.IM.Exclusive_Data 58 0.00% 0.00% system.ruby.l1_cntrl0.OM.All_acks 58 0.00% 0.00% system.ruby.l1_cntrl0.IS.Exclusive_Data 452 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 502 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 2799 -system.ruby.network.msg_count.Response_Data 2538 -system.ruby.network.msg_count.ResponseL2hit_Data 261 -system.ruby.network.msg_count.Writeback_Data 1734 -system.ruby.network.msg_count.Writeback_Control 6447 -system.ruby.network.msg_count.Unblock_Control 2798 -system.ruby.network.msg_byte.Request_Control 22392 -system.ruby.network.msg_byte.Response_Data 182736 -system.ruby.network.msg_byte.ResponseL2hit_Data 18792 -system.ruby.network.msg_byte.Writeback_Data 124848 -system.ruby.network.msg_byte.Writeback_Control 51576 -system.ruby.network.msg_byte.Unblock_Control 22384 system.ruby.l2_cntrl0.L1_GETS 454 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 58 0.00% 0.00% system.ruby.l2_cntrl0.L1_PUTX 502 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 963916828..57448e3a7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 07281999c..95ae6441f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:04:45 +Real time: Sep/22/2013 05:45:04 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 4 +Elapsed_time_in_minutes: 0.0666667 +Elapsed_time_in_hours: 0.00111111 +Elapsed_time_in_days: 4.62963e-05 -Virtual_time_in_seconds: 0.5 -Virtual_time_in_minutes: 0.00833333 -Virtual_time_in_hours: 0.000138889 -Virtual_time_in_days: 5.78704e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 43073 Ruby_start_time: 0 Ruby_cycles: 43073 -mbytes_resident: 74.1172 -mbytes_total: 168.629 -resident_ratio: 0.439552 +mbytes_resident: 67.8711 +mbytes_total: 121.816 +resident_ratio: 0.557159 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr index 31ae36f2e..492f3e68f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr @@ -1,3 +1,7 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index f8e247e3b..76c77f4a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:38:07 -gem5 started Sep 9 2012 13:38:15 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:44:48 +gem5 started Sep 22 2013 05:45:00 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 18f891852..c2d79012b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28702 # Simulator instruction rate (inst/s) -host_op_rate 28696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 479543 # Simulator tick rate (ticks/s) -host_mem_usage 172680 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 753 # Simulator instruction rate (inst/s) +host_op_rate 753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12587 # Simulator tick rate (ticks/s) +host_mem_usage 125800 # Number of bytes of host memory used +host_seconds 3.42 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits @@ -82,6 +82,18 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 +system.ruby.network.msg_count.Request_Control 2916 +system.ruby.network.msg_count.Response_Data 1344 +system.ruby.network.msg_count.ResponseL2hit_Data 210 +system.ruby.network.msg_count.Response_Control 3 +system.ruby.network.msg_count.Writeback_Data 1758 +system.ruby.network.msg_count.Writeback_Control 1095 +system.ruby.network.msg_byte.Request_Control 23328 +system.ruby.network.msg_byte.Response_Data 96768 +system.ruby.network.msg_byte.ResponseL2hit_Data 15120 +system.ruby.network.msg_byte.Response_Control 24 +system.ruby.network.msg_byte.Writeback_Data 126576 +system.ruby.network.msg_byte.Writeback_Control 8760 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -230,18 +242,6 @@ system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00% system.ruby.l1_cntrl0.SM.Data_All_Tokens 8 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_Shared 56 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_All_Tokens 396 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 2916 -system.ruby.network.msg_count.Response_Data 1344 -system.ruby.network.msg_count.ResponseL2hit_Data 210 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 1758 -system.ruby.network.msg_count.Writeback_Control 1095 -system.ruby.network.msg_byte.Request_Control 23328 -system.ruby.network.msg_byte.Response_Data 96768 -system.ruby.network.msg_byte.ResponseL2hit_Data 15120 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 126576 -system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.l2_cntrl0.L1_GETS 448 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETS_Last_Token 4 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 66 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 88d0e9108..fed15fed0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 11219bf48..fa2e0f324 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:02:56 +Real time: Sep/22/2013 05:17:49 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.71 -Virtual_time_in_minutes: 0.0118333 -Virtual_time_in_hours: 0.000197222 -Virtual_time_in_days: 8.21759e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 35432 Ruby_start_time: 0 Ruby_cycles: 35432 -mbytes_resident: 74.0898 -mbytes_total: 168.559 -resident_ratio: 0.439573 +mbytes_resident: 67.9453 +mbytes_total: 122.797 +resident_ratio: 0.553315 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index 31ae36f2e..492f3e68f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -1,3 +1,7 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 8fae8fc4c..fa7b05ab3 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 13:53:26 -gem5 started Sep 1 2012 13:54:34 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:17:28 +gem5 started Sep 22 2013 05:17:49 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index f2e316805..f43282687 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 6072 # Simulator instruction rate (inst/s) -host_op_rate 6072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83479 # Simulator tick rate (ticks/s) -host_mem_usage 172608 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_inst_rate 19167 # Simulator instruction rate (inst/s) +host_op_rate 19165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263474 # Simulator tick rate (ticks/s) +host_mem_usage 125748 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits @@ -82,6 +82,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 +system.ruby.network.msg_count.Request_Control 1323 +system.ruby.network.msg_count.Response_Data 1323 +system.ruby.network.msg_count.Writeback_Data 243 +system.ruby.network.msg_count.Writeback_Control 3582 +system.ruby.network.msg_count.Unblock_Control 1320 +system.ruby.network.msg_byte.Request_Control 10584 +system.ruby.network.msg_byte.Response_Data 95256 +system.ruby.network.msg_byte.Writeback_Data 17496 +system.ruby.network.msg_byte.Writeback_Control 28656 +system.ruby.network.msg_byte.Unblock_Control 10560 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -226,16 +236,6 @@ system.ruby.l1_cntrl0.MI.Store 4 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 425 0.00% 0.00% system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 24 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 1323 -system.ruby.network.msg_count.Response_Data 1323 -system.ruby.network.msg_count.Writeback_Data 243 -system.ruby.network.msg_count.Writeback_Control 3582 -system.ruby.network.msg_count.Unblock_Control 1320 -system.ruby.network.msg_byte.Request_Control 10584 -system.ruby.network.msg_byte.Response_Data 95256 -system.ruby.network.msg_byte.Writeback_Data 17496 -system.ruby.network.msg_byte.Writeback_Control 28656 -system.ruby.network.msg_byte.Unblock_Control 10560 system.ruby.dir_cntrl0.GETX 51 0.00% 0.00% system.ruby.dir_cntrl0.GETS 410 0.00% 0.00% system.ruby.dir_cntrl0.PUT 425 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 222831dad..56f1e35ca 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index 4a527e28b..dcfc1172a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:03:45 +Real time: Sep/28/2013 03:05:38 Profiler Stats -------------- -Elapsed_time_in_seconds: 19 -Elapsed_time_in_minutes: 0.316667 -Elapsed_time_in_hours: 0.00527778 -Elapsed_time_in_days: 0.000219907 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.33 +Virtual_time_in_minutes: 0.0055 +Virtual_time_in_hours: 9.16667e-05 +Virtual_time_in_days: 3.81944e-06 Ruby_current_time: 52498 Ruby_start_time: 0 Ruby_cycles: 52498 -mbytes_resident: 73.0898 -mbytes_total: 167.129 -resident_ratio: 0.43735 +mbytes_resident: 66.7812 +mbytes_total: 121.352 +resident_ratio: 0.550312 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr index 3bd6641db..492f3e68f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr @@ -1,6 +1,6 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 8e744dee3..980ebae91 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:25 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 892e92009..2e221d41c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 139 # Simulator instruction rate (inst/s) -host_op_rate 139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2832 # Simulator tick rate (ticks/s) -host_mem_usage 171144 # Number of bytes of host memory used -host_seconds 18.54 # Real time elapsed on the host +host_inst_rate 20624 # Simulator instruction rate (inst/s) +host_op_rate 20621 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 420021 # Simulator tick rate (ticks/s) +host_mem_usage 124268 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits @@ -55,6 +55,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 5008 system.ruby.network.routers2.msg_bytes.Data::2 44784 system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.msg_count.Control 1878 +system.ruby.network.msg_count.Data 1866 +system.ruby.network.msg_count.Response_Data 1878 +system.ruby.network.msg_count.Writeback_Control 1866 +system.ruby.network.msg_byte.Control 15024 +system.ruby.network.msg_byte.Data 134352 +system.ruby.network.msg_byte.Response_Data 135216 +system.ruby.network.msg_byte.Writeback_Control 14928 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,14 +164,6 @@ system.ruby.l1_cntrl0.M.Replacement 622 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 542 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 84 0.00% 0.00% -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.dir_cntrl0.GETX 626 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 622 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 626 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index adb7f583e..81f228137 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -119,10 +143,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -133,17 +157,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -160,7 +193,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -171,11 +204,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index d3b147605..f5b60c70f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:46:30 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 99487a7ba..a65f6cef4 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=system.cpu.checker -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -134,9 +139,8 @@ predType=tournament [system.cpu.checker] type=O3Checker children=dtb isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -155,6 +159,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.checker.tracer @@ -170,7 +175,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] @@ -200,7 +205,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] @@ -210,10 +215,10 @@ type=ExeTracer [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -224,12 +229,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=ArmTLB children=walker @@ -238,7 +252,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -508,10 +522,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -522,12 +536,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=ArmInterrupts @@ -556,17 +579,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -577,16 +600,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -605,7 +636,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -616,10 +647,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -630,19 +665,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -653,6 +693,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index d6f213d3f..ceaa08d85 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:15:23 -gem5 started Mar 26 2013 15:15:53 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 07:58:36 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13706000 because target called exit() +Exiting @ tick 16494000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index a72da393a..c7dae4bd5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=ArmTLB children=walker @@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -431,10 +445,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -445,12 +459,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=ArmInterrupts @@ -479,17 +502,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -500,16 +523,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -528,7 +559,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -539,10 +570,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -576,6 +616,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index ed98a8f73..91a377601 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:15:23 -gem5 started Mar 26 2013 15:15:53 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 09:14:18 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13706000 because target called exit() +Exiting @ tick 16494000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 8b4c27750..05132e433 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=checker dtb interrupts isa itb tracer workload -branchPred=Null checker=system.cpu.checker -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -66,14 +75,14 @@ icache_port=system.membus.slave[1] [system.cpu.checker] type=DummyChecker children=dtb isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=-1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +exitOnError=false function_trace=false function_trace_start=0 interrupts=Null @@ -86,9 +95,12 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.checker.tracer +updateOnError=false +warnOnlyOnLoadError=true workload=system.cpu.workload [system.cpu.checker.dtb] @@ -99,7 +111,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system @@ -128,7 +140,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system @@ -143,7 +155,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -176,7 +188,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -192,7 +204,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -203,11 +215,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -216,13 +233,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 891f01e6f..3a9ca0eef 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:44:07 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 08:10:56 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index b76b7c5a6..ea8fd73bf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -104,7 +113,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -120,7 +129,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -131,11 +140,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 38a423124..7cee6c9ed 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:56 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 08:14:08 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 276d0c57a..aa887d8df 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,12 +81,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=ArmTLB children=walker @@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -110,12 +125,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=ArmInterrupts @@ -144,17 +168,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=500 +clk_domain=system.cpu_clk_domain num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -165,17 +189,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -192,7 +225,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -203,11 +236,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 58b706eaf..db0e6caaf 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:44:20 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 07:58:15 +gem5 started Sep 22 2013 09:24:32 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 5f7d725ac..2a0a5918d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=InOrderCPU children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload @@ -36,7 +42,7 @@ activity=0 branchPred=system.cpu.branchPred cachePorts=2 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 div16Latency=1 div16RepeatRate=1 @@ -66,6 +72,7 @@ multRepeatRate=1 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= stageTracing=false stageWidth=4 switched_out=false @@ -84,11 +91,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -96,10 +101,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -110,22 +115,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=MipsTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -136,12 +150,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=MipsInterrupts @@ -156,10 +179,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -170,16 +193,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -198,7 +229,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -209,10 +240,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -223,19 +258,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -246,6 +286,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 146a5ec3a..0184d25db 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:56:08 -gem5 started Mar 26 2013 14:56:29 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:51:54 +gem5 started Sep 22 2013 05:52:06 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19339000 because target called exit() +Exiting @ tick 24587000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 97699de37..daf8c58a2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=MipsTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=MipsInterrupts @@ -456,10 +479,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -470,16 +493,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -498,7 +529,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -509,10 +540,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -523,19 +558,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -546,6 +586,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 33a7977e7..64f5582df 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:56:08 -gem5 started Mar 26 2013 14:56:29 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:51:54 +gem5 started Sep 22 2013 05:52:09 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 17026500 because target called exit() +Exiting @ tick 21805500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 781c5e460..917891d7e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -90,7 +99,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -101,11 +110,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -114,13 +128,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 2d983a191..b1c55ad09 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-a gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:17:17 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:51:54 +gem5 started Sep 22 2013 05:52:07 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 62d44e3cc..793123a59 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -98,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr index 5da3f0737..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -1,6 +1,6 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index bc8425f96..5beaf8240 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:17:40 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:51:54 +gem5 started Sep 22 2013 05:52:07 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 481b5bfc9..f05a7d5c9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33064 # Simulator instruction rate (inst/s) -host_op_rate 33061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 712624 # Simulator tick rate (ticks/s) -host_mem_usage 174400 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 6951 # Simulator instruction rate (inst/s) +host_op_rate 6951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149835 # Simulator tick rate (ticks/s) +host_mem_usage 127304 # Number of bytes of host memory used +host_seconds 0.84 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits @@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 11944 system.ruby.network.routers2.msg_bytes.Data::2 107208 system.ruby.network.routers2.msg_bytes.Response_Data::4 107496 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11912 +system.ruby.network.msg_count.Control 4479 +system.ruby.network.msg_count.Data 4467 +system.ruby.network.msg_count.Response_Data 4479 +system.ruby.network.msg_count.Writeback_Control 4467 +system.ruby.network.msg_byte.Control 35832 +system.ruby.network.msg_byte.Data 321624 +system.ruby.network.msg_byte.Response_Data 322488 +system.ruby.network.msg_byte.Writeback_Control 35736 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -143,14 +151,6 @@ system.ruby.l1_cntrl0.M.Replacement 1489 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 1489 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 1273 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 220 0.00% 0.00% -system.ruby.network.msg_count.Control 4479 -system.ruby.network.msg_count.Data 4467 -system.ruby.network.msg_count.Response_Data 4479 -system.ruby.network.msg_count.Writeback_Control 4467 -system.ruby.network.msg_byte.Control 35832 -system.ruby.network.msg_byte.Data 321624 -system.ruby.network.msg_byte.Response_Data 322488 -system.ruby.network.msg_byte.Writeback_Control 35736 system.ruby.dir_cntrl0.GETX 1493 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 1489 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 1493 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index 050099df0..aa6f1a156 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=MipsTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=MipsInterrupts @@ -121,10 +145,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -135,17 +159,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -162,7 +195,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -173,11 +206,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -186,13 +224,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 3cdc50c15..f65ffe2d1 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:17:28 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:51:54 +gem5 started Sep 22 2013 05:52:20 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 1aa882d35..92f5ec07b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -44,7 +50,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -93,6 +99,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -122,11 +129,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -134,10 +139,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -148,12 +153,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=PowerTLB size=64 @@ -423,10 +437,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -437,12 +451,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=PowerInterrupts @@ -455,10 +478,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -469,16 +492,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -497,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -508,10 +539,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -522,19 +557,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -545,6 +585,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index b6781a5c9..14f2d2615 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:59:37 -gem5 started Mar 26 2013 14:59:57 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:59:47 +gem5 started Sep 22 2013 05:59:59 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 14724500 because target called exit() +Exiting @ tick 18469500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index de2e34e4d..0bfe98e66 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,13 +30,17 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload UnifiedTLB=true -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -54,6 +59,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -89,7 +98,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -100,11 +109,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -113,13 +127,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index 82ad348ff..df127b542 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:33:02 -gem5 started Jan 23 2013 15:33:19 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:59:47 +gem5 started Sep 22 2013 05:59:59 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 08313d557..803d2e67f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=InOrderCPU children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload @@ -36,7 +42,7 @@ activity=0 branchPred=system.cpu.branchPred cachePorts=2 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 div16Latency=1 div16RepeatRate=1 @@ -66,6 +72,7 @@ multRepeatRate=1 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= stageTracing=false stageWidth=4 switched_out=false @@ -84,11 +91,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -96,10 +101,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -110,22 +115,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=SparcTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -136,12 +150,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=SparcInterrupts @@ -154,10 +177,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -168,16 +191,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -196,7 +227,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -207,10 +238,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -244,6 +284,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 06a0491cb..5555171c3 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorde gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:10:26 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 16783500 because target called exit() +Hello World!Exiting @ tick 20802500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index d5e3e4b20..5f0f231f3 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -88,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -99,11 +108,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 805340a73..3faafe3e1 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:12:14 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:09:49 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index b14794472..0e46b888b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -96,7 +95,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index ec0034585..417331876 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:04:06 +Real time: Sep/22/2013 06:10:01 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.38 +Virtual_time_in_minutes: 0.00633333 +Virtual_time_in_hours: 0.000105556 +Virtual_time_in_days: 4.39815e-06 Ruby_current_time: 107952 Ruby_start_time: 0 Ruby_cycles: 107952 -mbytes_resident: 76.2656 -mbytes_total: 176.473 -resident_ratio: 0.432189 +mbytes_resident: 69.6172 +mbytes_total: 130.562 +resident_ratio: 0.53321 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index 5da3f0737..bbc0c797e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -1,6 +1,6 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 34599be55..fe6ceebff 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:01:36 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:10:00 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 924fe00af..550fedd36 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23456 # Simulator instruction rate (inst/s) -host_op_rate 23454 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 475251 # Simulator tick rate (ticks/s) -host_mem_usage 180712 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 25358 # Simulator instruction rate (inst/s) +host_op_rate 25356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 513807 # Simulator tick rate (ticks/s) +host_mem_usage 133700 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits @@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.msg_count.Control 3867 +system.ruby.network.msg_count.Data 3855 +system.ruby.network.msg_count.Response_Data 3867 +system.ruby.network.msg_count.Writeback_Control 3855 +system.ruby.network.msg_byte.Control 30936 +system.ruby.network.msg_byte.Data 277560 +system.ruby.network.msg_byte.Response_Data 278424 +system.ruby.network.msg_byte.Writeback_Control 30840 system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 107952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -125,14 +133,6 @@ system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00% -system.ruby.network.msg_count.Control 3867 -system.ruby.network.msg_count.Data 3855 -system.ruby.network.msg_count.Response_Data 3867 -system.ruby.network.msg_count.Writeback_Control 3855 -system.ruby.network.msg_byte.Control 30936 -system.ruby.network.msg_byte.Data 277560 -system.ruby.network.msg_byte.Response_Data 278424 -system.ruby.network.msg_byte.Writeback_Control 30840 system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 3ba498627..794c187b4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=SparcTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=SparcInterrupts @@ -119,10 +143,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -133,17 +157,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -160,7 +193,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -171,11 +204,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 411439c6e..c2df02496 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:12:36 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:07:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index aae98d141..3ff31f398 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,9 +30,14 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -113,6 +120,11 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain + [system.cpu.branchPred] type=BranchPredictor BTBEntries=4096 @@ -121,11 +133,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +143,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +157,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=X86TLB children=walker @@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,10 +450,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -444,15 +464,24 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=X86LocalApic -clock=8000 +clk_domain=system.cpu.apic_clk_domain int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -472,16 +501,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -492,16 +522,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -520,7 +558,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -531,10 +569,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -568,6 +615,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 6136a5e78..2fb7489b2 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:13:59 -gem5 started Mar 26 2013 15:14:41 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 06:21:36 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 15474000 because target called exit() +Exiting @ tick 19639500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 7de6f390d..6906721ce 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null +children=apic_clk_domain dtb interrupts isa itb tracer workload checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -63,6 +72,11 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain + [system.cpu.dtb] type=X86TLB children=walker @@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=8000 +clk_domain=system.cpu.apic_clk_domain int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -97,7 +112,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.membus.slave[3] @@ -112,7 +128,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -123,10 +139,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 41b657a83..5c187d2d2 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:21:58 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 06:21:50 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 585043740..3bbe64bb8 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -127,7 +126,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 09ae639bb..b58867c62 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 09:58:16 +Real time: Sep/22/2013 07:07:53 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.63 -Virtual_time_in_minutes: 0.0105 -Virtual_time_in_hours: 0.000175 -Virtual_time_in_days: 7.29167e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 87.7695 -mbytes_total: 186.375 -resident_ratio: 0.470951 +mbytes_resident: 80.4375 +mbytes_total: 139.961 +resident_ratio: 0.574714 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 8c2cd3936..cb677e65b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:21:58 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 07:07:52 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 06a39e4b5..8372264a3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 9985 # Simulator instruction rate (inst/s) -host_op_rate 18087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 225916 # Simulator tick rate (ticks/s) -host_mem_usage 190852 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 28174 # Simulator instruction rate (inst/s) +host_op_rate 51034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 637400 # Simulator tick rate (ticks/s) +host_mem_usage 143324 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits @@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.msg_count.Control 4131 +system.ruby.network.msg_count.Data 4119 +system.ruby.network.msg_count.Response_Data 4131 +system.ruby.network.msg_count.Writeback_Control 4119 +system.ruby.network.msg_byte.Control 33048 +system.ruby.network.msg_byte.Data 296568 +system.ruby.network.msg_byte.Response_Data 297432 +system.ruby.network.msg_byte.Writeback_Control 32952 system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 121759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -125,14 +133,6 @@ system.ruby.l1_cntrl0.M.Replacement 1373 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 1122 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 255 0.00% 0.00% -system.ruby.network.msg_count.Control 4131 -system.ruby.network.msg_count.Data 4119 -system.ruby.network.msg_count.Response_Data 4131 -system.ruby.network.msg_count.Writeback_Control 4119 -system.ruby.network.msg_byte.Control 33048 -system.ruby.network.msg_byte.Data 296568 -system.ruby.network.msg_byte.Response_Data 297432 -system.ruby.network.msg_byte.Writeback_Control 32952 system.ruby.dir_cntrl0.GETX 1377 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 1373 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 1377 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 4f3f120ab..2a7188a36 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null +children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -59,12 +65,17 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu_clk_domain + [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,12 +86,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=X86TLB children=walker @@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -109,15 +130,24 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=X86LocalApic -clock=8000 +clk_domain=system.cpu.apic_clk_domain int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -137,16 +167,17 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=500 +clk_domain=system.cpu_clk_domain +num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -157,16 +188,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -185,7 +224,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -196,10 +235,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index e6d8615da..628ef5965 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:21:58 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:21:20 +gem5 started Sep 22 2013 06:48:05 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 934dbc782..5d2204eb4 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=2 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -457,10 +480,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -471,16 +494,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -499,7 +530,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -518,7 +549,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -529,10 +560,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -543,19 +578,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -566,6 +606,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 6461709eb..32cdff876 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 14:39:13 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 24422500 because target called exit() +Exiting @ tick 24404000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 4bb52cb94..86810fed8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=InOrderCPU children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload @@ -36,7 +42,7 @@ activity=0 branchPred=system.cpu.branchPred cachePorts=2 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 div16Latency=1 div16RepeatRate=1 @@ -66,6 +72,7 @@ multRepeatRate=1 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= stageTracing=false stageWidth=4 switched_out=false @@ -84,11 +91,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -96,10 +101,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -110,22 +115,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=SparcTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -136,12 +150,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=SparcInterrupts @@ -154,10 +177,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -168,16 +191,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -196,7 +227,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -207,10 +238,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -244,6 +284,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 637eeae2b..947073917 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/ino gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:09:42 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:11:33 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 22838500 because target called exit() +Exiting @ tick 27282000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 1c51ba20c..d46e2cc0c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=SparcTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=SparcInterrupts @@ -454,10 +477,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -468,16 +491,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -496,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -507,10 +538,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -544,6 +584,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index eeaf23c5e..f835cd945 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:07:44 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 23775500 because target called exit() +Exiting @ tick 26524500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index a6e90c248..72cf29eda 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -88,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -99,11 +108,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index b525c9dd9..24f0721ea 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 15:49:34 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:11:45 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index fd5e57b82..77bbda99d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=SparcTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=SparcInterrupts @@ -119,10 +143,10 @@ size=64 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -133,17 +157,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -160,7 +193,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -171,11 +204,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 2651935f3..de66adf5c 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 15:49:45 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:07:35 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 1686f16ad..b2863a63a 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -94,10 +99,14 @@ max_stack_size=67108864 output=cout system=system +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -108,8 +117,8 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 @@ -117,3 +126,7 @@ null=false range=0:134217727 port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout index e5b133727..a5ca10935 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 8 2013 10:00:13 -gem5 started Jun 8 2013 10:00:28 +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:39 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini index c06c84e34..d9ac6433c 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout index fa0029313..f1715e087 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 24 2013 11:53:30 -gem5 started Aug 24 2013 12:01:38 +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:39 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 85ac3f7de..dbb4c3a8f 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,14 +28,18 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -69,10 +74,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -83,22 +88,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=AlphaTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -109,12 +123,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=AlphaInterrupts @@ -141,9 +164,8 @@ system=system [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -178,10 +200,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -192,22 +214,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=AlphaTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -218,12 +249,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=AlphaInterrupts @@ -250,9 +290,8 @@ system=system [system.cpu2] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=2 do_checkpoint_insts=true do_quiesce=true @@ -287,10 +326,10 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -301,22 +340,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=AlphaTLB size=64 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -327,12 +375,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=AlphaInterrupts @@ -359,9 +416,8 @@ system=system [system.cpu3] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=3 do_checkpoint_insts=true do_quiesce=true @@ -396,10 +452,10 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -410,22 +466,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=AlphaTLB size=64 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +501,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=AlphaInterrupts @@ -465,12 +539,17 @@ max_stack_size=67108864 output=cout system=system +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -481,39 +560,46 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false -range=0:1073741823 +range=0:134217727 port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -521,3 +607,7 @@ width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index b26c03cc4..700bb6659 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -6,3 +6,4 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe +stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 6f7f12863..44418ccaa 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 8 2013 10:00:13 -gem5 started Jun 8 2013 10:00:28 +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:39 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 2e9aa5100..9ec6d0e6d 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3032804 # Simulator instruction rate (inst/s) -host_op_rate 3032728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 379104441 # Simulator tick rate (ticks/s) -host_mem_usage 1154504 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 2981071 # Simulator instruction rate (inst/s) +host_op_rate 2980990 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 372637325 # Simulator tick rate (ticks/s) +host_mem_usage 238220 # Number of bytes of host memory used +host_seconds 0.67 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory @@ -60,6 +60,167 @@ system.physmem.bw_total::total 877513594 # To system.membus.throughput 877513594 # Throughput (bytes/s) system.membus.data_through_bus 219392 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits +system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 60 # number of overall hits +system.l2c.overall_hits::cpu0.data 9 # number of overall hits +system.l2c.overall_hits::cpu1.inst 60 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits +system.l2c.overall_hits::cpu2.inst 60 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 60 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses +system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses +system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses +system.l2c.demand_misses::total 3428 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 403 # number of overall misses +system.l2c.overall_misses::cpu0.data 454 # number of overall misses +system.l2c.overall_misses::cpu1.inst 403 # number of overall misses +system.l2c.overall_misses::cpu1.data 454 # number of overall misses +system.l2c.overall_misses::cpu2.inst 403 # number of overall misses +system.l2c.overall_misses::cpu2.data 454 # number of overall misses +system.l2c.overall_misses::cpu3.inst 403 # number of overall misses +system.l2c.overall_misses::cpu3.data 454 # number of overall misses +system.l2c.overall_misses::total 3428 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 977859373 # Throughput (bytes/s) system.toL2Bus.data_through_bus 244480 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -118,15 +279,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 500032 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits @@ -160,15 +321,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -267,15 +428,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 500032 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits @@ -309,15 +470,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits @@ -416,15 +577,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 500032 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits @@ -458,15 +619,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits @@ -565,15 +726,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 500032 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits @@ -607,15 +768,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits @@ -659,166 +820,5 @@ system.cpu3.dcache.cache_copies 0 # nu system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.tags.total_refs 332 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits -system.l2c.Writeback_hits::total 116 # number of Writeback hits -system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 60 # number of overall hits -system.l2c.overall_hits::cpu0.data 9 # number of overall hits -system.l2c.overall_hits::cpu1.inst 60 # number of overall hits -system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 60 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 60 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 403 # number of overall misses -system.l2c.overall_misses::cpu0.data 454 # number of overall misses -system.l2c.overall_misses::cpu1.inst 403 # number of overall misses -system.l2c.overall_misses::cpu1.data 454 # number of overall misses -system.l2c.overall_misses::cpu2.inst 403 # number of overall misses -system.l2c.overall_misses::cpu2.data 454 # number of overall misses -system.l2c.overall_misses::cpu3.inst 403 # number of overall misses -system.l2c.overall_misses::cpu3.data 454 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 1b0504991..03af5b9e4 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -158,7 +157,6 @@ system=system [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 @@ -278,7 +276,6 @@ system=system [system.cpu2] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=2 @@ -398,7 +395,6 @@ system=system [system.cpu3] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=3 diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 8b296506e..0997e3f27 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -4,7 +4,6 @@ warn: Prefetch instructions in Alpha do not do anything hack: be nice to actually delete the event here gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe +stdout: Broken pipe gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 8dc0648e9..0e186045b 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 24 2013 11:53:30 -gem5 started Aug 24 2013 12:01:38 +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:40 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 49d73401e..717f44afc 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,7 +28,12 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu0.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -463,7 +486,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -488,7 +511,7 @@ backComSize=5 branchPred=system.cpu1.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -537,6 +560,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -566,11 +590,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -578,10 +600,10 @@ predType=tournament [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -592,12 +614,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 @@ -867,10 +898,10 @@ opLat=3 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -881,12 +912,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -914,7 +954,7 @@ backComSize=5 branchPred=system.cpu2.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -963,6 +1003,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -992,11 +1033,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -1004,10 +1043,10 @@ predType=tournament [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1018,12 +1057,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 @@ -1293,10 +1341,10 @@ opLat=3 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1307,12 +1355,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -1340,7 +1397,7 @@ backComSize=5 branchPred=system.cpu3.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -1389,6 +1446,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -1418,11 +1476,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -1430,10 +1486,10 @@ predType=tournament [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1444,12 +1500,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 @@ -1719,10 +1784,10 @@ opLat=3 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -1733,12 +1798,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -1752,12 +1826,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -1768,39 +1847,52 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -1811,13 +1903,11 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -1825,3 +1915,7 @@ width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 3c88e0e72..f522c13b1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,47 +3,47 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:07:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 Iteration 4 completed [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 @@ -52,33 +52,33 @@ Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 105945500 because target called exit() +Exiting @ tick 110804500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 606c05841..aa7fc3405 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,14 +28,18 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -65,10 +74,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -79,22 +88,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -105,12 +123,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -132,7 +159,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -146,9 +173,8 @@ uid=100 [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -167,6 +193,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -179,10 +209,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -193,22 +223,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -219,12 +258,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -241,9 +289,8 @@ type=ExeTracer [system.cpu2] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=2 do_checkpoint_insts=true do_quiesce=true @@ -262,6 +309,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -274,10 +325,10 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -288,22 +339,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -314,12 +374,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -336,9 +405,8 @@ type=ExeTracer [system.cpu3] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=3 do_checkpoint_insts=true do_quiesce=true @@ -357,6 +425,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -369,10 +441,10 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -383,22 +455,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -409,12 +490,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -428,12 +518,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -444,42 +539,54 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false -range=0:1073741823 -zero=false +range=0:134217727 port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index e013c98f2..a3bbfbbb8 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:09:53 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:09:34 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 42fbfc6a4..8179c99d9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1256528 # Simulator instruction rate (inst/s) -host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162691956 # Simulator tick rate (ticks/s) -host_mem_usage 1160656 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 170274 # Simulator instruction rate (inst/s) +host_op_rate 170274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22048637 # Simulator tick rate (ticks/s) +host_mem_usage 246052 # Number of bytes of host memory used +host_seconds 3.98 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -60,6 +60,184 @@ system.physmem.bw_total::total 407903588 # To system.membus.throughput 407903588 # Throughput (bytes/s) system.membus.data_through_bus 35776 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 356 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 423 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) system.toL2Bus.data_through_bus 166080 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -86,15 +264,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +306,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +388,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +430,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +510,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +552,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +632,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +674,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,183 +732,5 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index b4eef5d4b..51f67db18 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -27,14 +28,18 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[1] +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.dtb] type=SparcTLB size=64 [system.cpu0.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu0.interrupts] type=SparcInterrupts @@ -128,7 +152,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -142,9 +166,8 @@ uid=100 [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +185,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer @@ -171,10 +195,10 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -185,22 +209,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.dtb] type=SparcTLB size=64 [system.cpu1.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -211,12 +244,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1.interrupts] type=SparcInterrupts @@ -233,9 +275,8 @@ type=ExeTracer [system.cpu2] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=2 do_checkpoint_insts=true do_quiesce=true @@ -253,6 +294,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu2.tracer @@ -262,10 +304,10 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -276,22 +318,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] +[system.cpu2.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.dtb] type=SparcTLB size=64 [system.cpu2.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -302,12 +353,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] +[system.cpu2.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2.interrupts] type=SparcInterrupts @@ -324,9 +384,8 @@ type=ExeTracer [system.cpu3] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=3 do_checkpoint_insts=true do_quiesce=true @@ -344,6 +403,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu3.tracer @@ -353,10 +413,10 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -367,22 +427,31 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] +[system.cpu3.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.dtb] type=SparcTLB size=64 [system.cpu3.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=1 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -393,12 +462,21 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] +[system.cpu3.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3.interrupts] type=SparcInterrupts @@ -412,12 +490,17 @@ size=64 [system.cpu3.tracer] type=ExeTracer +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -428,40 +511,46 @@ prefetcher=Null response_latency=20 size=4194304 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=4194304 [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false width=8 master=system.physmem.port -slave=system.l2c.mem_side system.system_port +slave=system.system_port system.l2c.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -469,3 +558,7 @@ width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index adbb7069b..7a29b18d1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,75 +3,75 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:04:14 -gem5 started Mar 26 2013 15:04:37 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 06:07:13 +gem5 started Sep 22 2013 06:10:12 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 1] Got lock [Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 Iteration 2 completed [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 Iteration 8 completed [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 262970500 because target called exit() +Exiting @ tick 262794500 because target called exit() diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 5908a1a40..051ef25fb 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:05:26 +Real time: Sep/22/2013 05:28:42 Profiler Stats -------------- -Elapsed_time_in_seconds: 101 -Elapsed_time_in_minutes: 1.68333 -Elapsed_time_in_hours: 0.0280556 -Elapsed_time_in_days: 0.00116898 +Elapsed_time_in_seconds: 79 +Elapsed_time_in_minutes: 1.31667 +Elapsed_time_in_hours: 0.0219444 +Elapsed_time_in_days: 0.000914352 -Virtual_time_in_seconds: 100.98 -Virtual_time_in_minutes: 1.683 -Virtual_time_in_hours: 0.02805 -Virtual_time_in_days: 0.00116875 +Virtual_time_in_seconds: 79.09 +Virtual_time_in_minutes: 1.31817 +Virtual_time_in_hours: 0.0219694 +Virtual_time_in_days: 0.000915394 Ruby_current_time: 7257449 Ruby_start_time: 0 Ruby_cycles: 7257449 -mbytes_resident: 79.3281 -mbytes_total: 297.352 -resident_ratio: 0.266795 +mbytes_resident: 69.1055 +mbytes_total: 251.578 +resident_ratio: 0.275713 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 82781df07..53312cb70 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memte gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 9 2013 02:02:21 -gem5 started Apr 9 2013 02:03:11 -gem5 executing on vein +gem5 compiled Sep 22 2013 05:27:02 +gem5 started Sep 22 2013 05:27:23 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index d27642359..e71048b46 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007257 # Nu sim_ticks 7257449 # Number of ticks simulated final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 71632 # Simulator tick rate (ticks/s) -host_mem_usage 305516 # Number of bytes of host memory used -host_seconds 101.32 # Real time elapsed on the host +host_tick_rate 91873 # Simulator tick rate (ticks/s) +host_mem_usage 257620 # Number of bytes of host memory used +host_seconds 78.99 # Real time elapsed on the host system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 76641 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76643 # Number of cache demand accesses @@ -325,6 +325,18 @@ system.ruby.network.routers10.msg_bytes.Response_Control::2 4842768 system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8120304 system.ruby.network.routers10.msg_bytes.Writeback_Data::1 28664064 system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1656240 +system.ruby.network.msg_count.Control 3646183 +system.ruby.network.msg_count.Request_Control 1770458 +system.ruby.network.msg_count.Response_Data 4285974 +system.ruby.network.msg_count.Response_Control 6337828 +system.ruby.network.msg_count.Writeback_Data 1532683 +system.ruby.network.msg_count.Writeback_Control 621092 +system.ruby.network.msg_byte.Control 29169464 +system.ruby.network.msg_byte.Request_Control 14163664 +system.ruby.network.msg_byte.Response_Data 308590128 +system.ruby.network.msg_byte.Response_Control 50702624 +system.ruby.network.msg_byte.Writeback_Data 110353176 +system.ruby.network.msg_byte.Writeback_Control 4968736 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 99060 # number of read accesses completed @@ -883,18 +895,6 @@ system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 29 0.00% 0.00% system.ruby.l2_cntrl0.MT_SB.L1_PUTX 2 0.00% 0.00% system.ruby.l2_cntrl0.MT_SB.L2_Replacement 199 0.00% 0.00% system.ruby.l2_cntrl0.MT_SB.Unblock 780 0.00% 0.00% -system.ruby.network.msg_count.Control 3646183 -system.ruby.network.msg_count.Request_Control 1770458 -system.ruby.network.msg_count.Response_Data 4285974 -system.ruby.network.msg_count.Response_Control 6337828 -system.ruby.network.msg_count.Writeback_Data 1532683 -system.ruby.network.msg_count.Writeback_Control 621092 -system.ruby.network.msg_byte.Control 29169464 -system.ruby.network.msg_byte.Request_Control 14163664 -system.ruby.network.msg_byte.Response_Data 308590128 -system.ruby.network.msg_byte.Response_Control 50702624 -system.ruby.network.msg_byte.Writeback_Data 110353176 -system.ruby.network.msg_byte.Writeback_Control 4968736 system.ruby.dir_cntrl0.Fetch 604998 0.00% 0.00% system.ruby.dir_cntrl0.Data 212955 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 604995 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index cb8083e15..d118d8b60 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:07:55 +Real time: Sep/22/2013 05:38:45 Profiler Stats -------------- -Elapsed_time_in_seconds: 182 -Elapsed_time_in_minutes: 3.03333 -Elapsed_time_in_hours: 0.0505556 -Elapsed_time_in_days: 0.00210648 +Elapsed_time_in_seconds: 142 +Elapsed_time_in_minutes: 2.36667 +Elapsed_time_in_hours: 0.0394444 +Elapsed_time_in_days: 0.00164352 -Virtual_time_in_seconds: 181.59 -Virtual_time_in_minutes: 3.0265 -Virtual_time_in_hours: 0.0504417 -Virtual_time_in_days: 0.00210174 +Virtual_time_in_seconds: 142.1 +Virtual_time_in_minutes: 2.36833 +Virtual_time_in_hours: 0.0394722 +Virtual_time_in_days: 0.00164468 Ruby_current_time: 7481441 Ruby_start_time: 0 Ruby_cycles: 7481441 -mbytes_resident: 80.625 -mbytes_total: 299.508 -resident_ratio: 0.269205 +mbytes_resident: 70.6289 +mbytes_total: 253.738 +resident_ratio: 0.278353 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 30ecc5910..802dd1a62 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 9 2013 02:05:20 -gem5 started Apr 9 2013 02:06:11 -gem5 executing on vein +gem5 compiled Sep 22 2013 05:36:12 +gem5 started Sep 22 2013 05:36:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 7344fcbda..95538d9b6 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007481 # Nu sim_ticks 7481441 # Number of ticks simulated final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 41233 # Simulator tick rate (ticks/s) -host_mem_usage 306700 # Number of bytes of host memory used -host_seconds 181.44 # Real time elapsed on the host +host_tick_rate 52727 # Simulator tick rate (ticks/s) +host_mem_usage 259832 # Number of bytes of host memory used +host_seconds 141.89 # Real time elapsed on the host system.ruby.l1_cntrl4.L1Dcache.demand_hits 21 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 77428 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77449 # Number of cache demand accesses @@ -307,6 +307,26 @@ system.ruby.network.routers10.msg_bytes.Writeback_Control::2 3115216 system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 67368 system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 152 system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9858144 +system.ruby.network.msg_count.Request_Control 3673936 +system.ruby.network.msg_count.Response_Data 3630768 +system.ruby.network.msg_count.ResponseL2hit_Data 17766 +system.ruby.network.msg_count.ResponseLocal_Data 25260 +system.ruby.network.msg_count.Response_Control 9012 +system.ruby.network.msg_count.Writeback_Data 2479504 +system.ruby.network.msg_count.Writeback_Control 8511972 +system.ruby.network.msg_count.Forwarded_Control 25263 +system.ruby.network.msg_count.Invalidate_Control 57 +system.ruby.network.msg_count.Unblock_Control 3696804 +system.ruby.network.msg_byte.Request_Control 29391488 +system.ruby.network.msg_byte.Response_Data 261415296 +system.ruby.network.msg_byte.ResponseL2hit_Data 1279152 +system.ruby.network.msg_byte.ResponseLocal_Data 1818720 +system.ruby.network.msg_byte.Response_Control 72096 +system.ruby.network.msg_byte.Writeback_Data 178524288 +system.ruby.network.msg_byte.Writeback_Control 68095776 +system.ruby.network.msg_byte.Forwarded_Control 202104 +system.ruby.network.msg_byte.Invalidate_Control 456 +system.ruby.network.msg_byte.Unblock_Control 29574432 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 99553 # number of read accesses completed @@ -1105,26 +1125,6 @@ system.ruby.l2_cntrl0.MI.Writeback_Ack 604406 0.00% 0.00% system.ruby.l2_cntrl0.OLSI.L1_PUTS_only 1011 0.00% 0.00% system.ruby.l2_cntrl0.OLSI.L1_PUTS 108 0.00% 0.00% system.ruby.l2_cntrl0.OLSI.Writeback_Ack 239 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 3673936 -system.ruby.network.msg_count.Response_Data 3630768 -system.ruby.network.msg_count.ResponseL2hit_Data 17766 -system.ruby.network.msg_count.ResponseLocal_Data 25260 -system.ruby.network.msg_count.Response_Control 9012 -system.ruby.network.msg_count.Writeback_Data 2479504 -system.ruby.network.msg_count.Writeback_Control 8511972 -system.ruby.network.msg_count.Forwarded_Control 25263 -system.ruby.network.msg_count.Invalidate_Control 57 -system.ruby.network.msg_count.Unblock_Control 3696804 -system.ruby.network.msg_byte.Request_Control 29391488 -system.ruby.network.msg_byte.Response_Data 261415296 -system.ruby.network.msg_byte.ResponseL2hit_Data 1279152 -system.ruby.network.msg_byte.ResponseLocal_Data 1818720 -system.ruby.network.msg_byte.Response_Control 72096 -system.ruby.network.msg_byte.Writeback_Data 178524288 -system.ruby.network.msg_byte.Writeback_Control 68095776 -system.ruby.network.msg_byte.Forwarded_Control 202104 -system.ruby.network.msg_byte.Invalidate_Control 456 -system.ruby.network.msg_byte.Unblock_Control 29574432 system.ruby.dir_cntrl0.GETX 211949 0.00% 0.00% system.ruby.dir_cntrl0.GETS 393220 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 604433 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index 11200a202..a202baa14 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -17,7 +17,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:268435455 -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index 87304c1a3..e0121fbf8 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:06:47 +Real time: Sep/22/2013 05:46:37 Profiler Stats -------------- -Elapsed_time_in_seconds: 124 -Elapsed_time_in_minutes: 2.06667 -Elapsed_time_in_hours: 0.0344444 -Elapsed_time_in_days: 0.00143519 +Elapsed_time_in_seconds: 97 +Elapsed_time_in_minutes: 1.61667 +Elapsed_time_in_hours: 0.0269444 +Elapsed_time_in_days: 0.00112269 -Virtual_time_in_seconds: 123.4 -Virtual_time_in_minutes: 2.05667 -Virtual_time_in_hours: 0.0342778 -Virtual_time_in_days: 0.00142824 +Virtual_time_in_seconds: 97.69 +Virtual_time_in_minutes: 1.62817 +Virtual_time_in_hours: 0.0271361 +Virtual_time_in_days: 0.00113067 Ruby_current_time: 6151475 Ruby_start_time: 0 Ruby_cycles: 6151475 -mbytes_resident: 79.2969 -mbytes_total: 297.457 -resident_ratio: 0.266596 +mbytes_resident: 68.8125 +mbytes_total: 251.641 +resident_ratio: 0.273455 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index e78fa46c2..9d06307c2 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 9 2013 02:08:32 -gem5 started Apr 9 2013 02:09:19 -gem5 executing on vein +gem5 compiled Sep 22 2013 05:44:48 +gem5 started Sep 22 2013 05:44:59 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 17d7f958c..30f4ed177 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.006151 # Nu sim_ticks 6151475 # Number of ticks simulated final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 49950 # Simulator tick rate (ticks/s) -host_mem_usage 304600 # Number of bytes of host memory used -host_seconds 123.15 # Real time elapsed on the host +host_tick_rate 63154 # Simulator tick rate (ticks/s) +host_mem_usage 257684 # Number of bytes of host memory used +host_seconds 97.40 # Real time elapsed on the host system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 76947 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76967 # Number of cache demand accesses @@ -265,6 +265,24 @@ system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63441936 system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3020648 system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 34542088 system.ruby.network.routers10.msg_bytes.Persistent_Control::3 18697824 +system.ruby.network.msg_count.Request_Control 3695895 +system.ruby.network.msg_count.Response_Data 1838719 +system.ruby.network.msg_count.ResponseL2hit_Data 5073 +system.ruby.network.msg_count.ResponseLocal_Data 4698 +system.ruby.network.msg_count.Response_Control 4248 +system.ruby.network.msg_count.Writeback_Data 2643414 +system.ruby.network.msg_count.Writeback_Control 1132743 +system.ruby.network.msg_count.Broadcast_Control 9252345 +system.ruby.network.msg_count.Persistent_Control 5193840 +system.ruby.network.msg_byte.Request_Control 29567160 +system.ruby.network.msg_byte.Response_Data 132387768 +system.ruby.network.msg_byte.ResponseL2hit_Data 365256 +system.ruby.network.msg_byte.ResponseLocal_Data 338256 +system.ruby.network.msg_byte.Response_Control 33984 +system.ruby.network.msg_byte.Writeback_Data 190325808 +system.ruby.network.msg_byte.Writeback_Control 9061944 +system.ruby.network.msg_byte.Broadcast_Control 74018760 +system.ruby.network.msg_byte.Persistent_Control 41550720 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 100000 # number of read accesses completed @@ -1217,24 +1235,6 @@ system.ruby.l2_cntrl0.I_L.Persistent_GETS 83699 0.00% 0.00% system.ruby.l2_cntrl0.I_L.Own_Lock_or_Unlock 330 0.00% 0.00% system.ruby.l2_cntrl0.S_L.L2_Replacement 1 0.00% 0.00% system.ruby.l2_cntrl0.S_L.Own_Lock_or_Unlock 5 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 3695895 -system.ruby.network.msg_count.Response_Data 1838719 -system.ruby.network.msg_count.ResponseL2hit_Data 5073 -system.ruby.network.msg_count.ResponseLocal_Data 4698 -system.ruby.network.msg_count.Response_Control 4248 -system.ruby.network.msg_count.Writeback_Data 2643414 -system.ruby.network.msg_count.Writeback_Control 1132743 -system.ruby.network.msg_count.Broadcast_Control 9252345 -system.ruby.network.msg_count.Persistent_Control 5193840 -system.ruby.network.msg_byte.Request_Control 29567160 -system.ruby.network.msg_byte.Response_Data 132387768 -system.ruby.network.msg_byte.ResponseL2hit_Data 365256 -system.ruby.network.msg_byte.ResponseLocal_Data 338256 -system.ruby.network.msg_byte.Response_Control 33984 -system.ruby.network.msg_byte.Writeback_Data 190325808 -system.ruby.network.msg_byte.Writeback_Control 9061944 -system.ruby.network.msg_byte.Broadcast_Control 74018760 -system.ruby.network.msg_byte.Persistent_Control 41550720 system.ruby.dir_cntrl0.GETX 255487 0.00% 0.00% system.ruby.dir_cntrl0.GETS 476933 0.00% 0.00% system.ruby.dir_cntrl0.Lockdown 130603 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 50647016f..3e6cf4aa4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:05:07 +Real time: Sep/22/2013 05:19:16 Profiler Stats -------------- -Elapsed_time_in_seconds: 131 -Elapsed_time_in_minutes: 2.18333 -Elapsed_time_in_hours: 0.0363889 -Elapsed_time_in_days: 0.0015162 +Elapsed_time_in_seconds: 98 +Elapsed_time_in_minutes: 1.63333 +Elapsed_time_in_hours: 0.0272222 +Elapsed_time_in_days: 0.00113426 -Virtual_time_in_seconds: 131.88 -Virtual_time_in_minutes: 2.198 -Virtual_time_in_hours: 0.0366333 -Virtual_time_in_days: 0.00152639 +Virtual_time_in_seconds: 98.86 +Virtual_time_in_minutes: 1.64767 +Virtual_time_in_hours: 0.0274611 +Virtual_time_in_days: 0.00114421 Ruby_current_time: 5795833 Ruby_start_time: 0 Ruby_cycles: 5795833 -mbytes_resident: 75.793 -mbytes_total: 298.383 -resident_ratio: 0.254026 +mbytes_resident: 69.3711 +mbytes_total: 252.59 +resident_ratio: 0.274639 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 899bc58f8..5f6410683 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 9 2013 01:58:20 -gem5 started Apr 9 2013 01:59:05 -gem5 executing on vein +gem5 compiled Sep 22 2013 05:17:28 +gem5 started Sep 22 2013 05:17:37 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 98f43c561..2c76706ec 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.005796 # Nu sim_ticks 5795833 # Number of ticks simulated final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 44085 # Simulator tick rate (ticks/s) -host_mem_usage 305548 # Number of bytes of host memory used -host_seconds 131.47 # Real time elapsed on the host +host_tick_rate 58777 # Simulator tick rate (ticks/s) +host_mem_usage 258656 # Number of bytes of host memory used +host_seconds 98.61 # Real time elapsed on the host system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 77212 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77226 # Number of cache demand accesses @@ -308,6 +308,20 @@ system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4658336 system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2944376 system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 34549816 system.ruby.network.routers9.msg_bytes.Unblock_Control::5 4940768 +system.ruby.network.msg_count.Request_Control 1853520 +system.ruby.network.msg_count.Response_Data 1852131 +system.ruby.network.msg_count.Response_Control 12897795 +system.ruby.network.msg_count.Writeback_Data 642069 +system.ruby.network.msg_count.Writeback_Control 4597894 +system.ruby.network.msg_count.Broadcast_Control 9254415 +system.ruby.network.msg_count.Unblock_Control 1852789 +system.ruby.network.msg_byte.Request_Control 14828160 +system.ruby.network.msg_byte.Response_Data 133353432 +system.ruby.network.msg_byte.Response_Control 103182360 +system.ruby.network.msg_byte.Writeback_Data 46228968 +system.ruby.network.msg_byte.Writeback_Control 36783152 +system.ruby.network.msg_byte.Broadcast_Control 74035320 +system.ruby.network.msg_byte.Unblock_Control 14822312 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 99395 # number of read accesses completed @@ -1054,20 +1068,6 @@ system.ruby.l1_cntrl0.MMT.L1_to_L2::total 758 system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 | 21 10.29% 10.29% | 25 12.25% 22.55% | 34 16.67% 39.22% | 24 11.76% 50.98% | 25 12.25% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00% system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1::total 204 -system.ruby.network.msg_count.Request_Control 1853520 -system.ruby.network.msg_count.Response_Data 1852131 -system.ruby.network.msg_count.Response_Control 12897795 -system.ruby.network.msg_count.Writeback_Data 642069 -system.ruby.network.msg_count.Writeback_Control 4597894 -system.ruby.network.msg_count.Broadcast_Control 9254415 -system.ruby.network.msg_count.Unblock_Control 1852789 -system.ruby.network.msg_byte.Request_Control 14828160 -system.ruby.network.msg_byte.Response_Data 133353432 -system.ruby.network.msg_byte.Response_Control 103182360 -system.ruby.network.msg_byte.Writeback_Data 46228968 -system.ruby.network.msg_byte.Writeback_Control 36783152 -system.ruby.network.msg_byte.Broadcast_Control 74035320 -system.ruby.network.msg_byte.Unblock_Control 14822312 system.ruby.dir_cntrl0.GETX 220023 0.00% 0.00% system.ruby.dir_cntrl0.GETS 406995 0.00% 0.00% system.ruby.dir_cntrl0.PUT 585083 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index f52cdf318..cd6eb6e26 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -17,7 +17,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:268435455 -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 9ecd89c86..5e18bea6c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:05:30 +Real time: Sep/28/2013 03:06:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 48 -Elapsed_time_in_minutes: 0.8 -Elapsed_time_in_hours: 0.0133333 -Elapsed_time_in_days: 0.000555556 +Elapsed_time_in_seconds: 36 +Elapsed_time_in_minutes: 0.6 +Elapsed_time_in_hours: 0.01 +Elapsed_time_in_days: 0.000416667 -Virtual_time_in_seconds: 47.63 -Virtual_time_in_minutes: 0.793833 -Virtual_time_in_hours: 0.0132306 -Virtual_time_in_days: 0.000551273 +Virtual_time_in_seconds: 36.54 +Virtual_time_in_minutes: 0.609 +Virtual_time_in_hours: 0.01015 +Virtual_time_in_days: 0.000422917 Ruby_current_time: 8664886 Ruby_start_time: 0 Ruby_cycles: 8664886 -mbytes_resident: 75.6094 -mbytes_total: 295.949 -resident_ratio: 0.255494 +mbytes_resident: 67.1875 +mbytes_total: 250.145 +resident_ratio: 0.269579 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 3495746a7..1c746b09a 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 9 2013 01:51:40 -gem5 started Apr 9 2013 01:54:58 -gem5 executing on vein +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:49 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 10a35fe3c..74bfa5d0c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.008665 # Nu sim_ticks 8664886 # Number of ticks simulated final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 183404 # Simulator tick rate (ticks/s) -host_mem_usage 303056 # Number of bytes of host memory used -host_seconds 47.25 # Real time elapsed on the host +host_tick_rate 239244 # Simulator tick rate (ticks/s) +host_mem_usage 256152 # Number of bytes of host memory used +host_seconds 36.22 # Real time elapsed on the host system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.cacheMemory.demand_misses 77331 # Number of cache demand misses system.ruby.l1_cntrl4.cacheMemory.demand_accesses 77331 # Number of cache demand accesses @@ -139,6 +139,14 @@ system.ruby.network.routers9.msg_bytes.Control::2 4940496 system.ruby.network.routers9.msg_bytes.Data::2 44060256 system.ruby.network.routers9.msg_bytes.Response_Data::4 44463816 system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4961080 +system.ruby.network.msg_count.Control 1852692 +system.ruby.network.msg_count.Data 1835849 +system.ruby.network.msg_count.Response_Data 1852658 +system.ruby.network.msg_count.Writeback_Control 1860405 +system.ruby.network.msg_byte.Control 14821536 +system.ruby.network.msg_byte.Data 132181128 +system.ruby.network.msg_byte.Response_Data 133391376 +system.ruby.network.msg_byte.Writeback_Control 14883240 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 99885 # number of read accesses completed @@ -367,14 +375,6 @@ system.ruby.l1_cntrl0.IS.Data::total 401489 system.ruby.l1_cntrl0.IM.Data | 27005 12.50% 12.50% | 26934 12.47% 24.96% | 26786 12.40% 37.36% | 27152 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.54% 75.11% | 27074 12.53% 87.64% | 26701 12.36% 100.00% system.ruby.l1_cntrl0.IM.Data::total 216063 -system.ruby.network.msg_count.Control 1852692 -system.ruby.network.msg_count.Data 1835849 -system.ruby.network.msg_count.Response_Data 1852658 -system.ruby.network.msg_count.Writeback_Control 1860405 -system.ruby.network.msg_byte.Control 14821536 -system.ruby.network.msg_byte.Data 132181128 -system.ruby.network.msg_byte.Response_Data 133391376 -system.ruby.network.msg_byte.Writeback_Control 14883240 system.ruby.dir_cntrl0.GETX 791175 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 609324 0.00% 0.00% system.ruby.dir_cntrl0.PUTX_NotOwner 2623 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini index 1f567a1b9..0b50bed4c 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini @@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= @@ -29,11 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[1] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu0] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -51,10 +57,10 @@ test=system.cpu0.l1c.cpu_side [system.cpu0.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -65,17 +71,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu0.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.test mem_side=system.toL2Bus.slave[0] +[system.cpu0.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu1] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -93,10 +108,10 @@ test=system.cpu1.l1c.cpu_side [system.cpu1.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -107,17 +122,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu1.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.test mem_side=system.toL2Bus.slave[1] +[system.cpu1.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu2] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -135,10 +159,10 @@ test=system.cpu2.l1c.cpu_side [system.cpu2.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -149,17 +173,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu2.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.test mem_side=system.toL2Bus.slave[2] +[system.cpu2.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu3] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -177,10 +210,10 @@ test=system.cpu3.l1c.cpu_side [system.cpu3.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -191,17 +224,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu3.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.test mem_side=system.toL2Bus.slave[3] +[system.cpu3.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu4] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -219,10 +261,10 @@ test=system.cpu4.l1c.cpu_side [system.cpu4.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -233,17 +275,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu4.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu4.test mem_side=system.toL2Bus.slave[4] +[system.cpu4.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu5] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -261,10 +312,10 @@ test=system.cpu5.l1c.cpu_side [system.cpu5.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -275,17 +326,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu5.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu5.test mem_side=system.toL2Bus.slave[5] +[system.cpu5.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu6] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -303,10 +363,10 @@ test=system.cpu6.l1c.cpu_side [system.cpu6.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -317,17 +377,26 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu6.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu6.test mem_side=system.toL2Bus.slave[6] +[system.cpu6.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + [system.cpu7] type=MemTest children=l1c atomic=false -clock=500 +clk_domain=system.cpu_clk_domain issue_dmas=false max_loads=100000 memory_size=65536 @@ -345,10 +414,10 @@ test=system.cpu7.l1c.cpu_side [system.cpu7.l1c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=4 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -359,16 +428,29 @@ prefetcher=Null response_latency=2 size=32768 system=system +tags=system.cpu7.l1c.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu7.test mem_side=system.toL2Bus.slave[7] +[system.cpu7.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=32768 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.funcbus] type=NoncoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 use_default_range=false width=8 @@ -378,22 +460,21 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste [system.funcmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=false latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.funcbus.master[0] [system.l2c] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -404,16 +485,24 @@ prefetcher=Null response_latency=20 size=65536 system=system +tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=65536 + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -424,20 +513,18 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -445,3 +532,7 @@ width=16 master=system.l2c.cpu_side slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr index 014cde607..ad8539d90 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu6: completed 10000 read, 5435 write accesses @79021500 -system.cpu0: completed 10000 read, 5363 write accesses @79194500 -system.cpu7: completed 10000 read, 5392 write accesses @79770500 -system.cpu2: completed 10000 read, 5375 write accesses @80689500 -system.cpu1: completed 10000 read, 5373 write accesses @81623500 -system.cpu4: completed 10000 read, 5458 write accesses @81916000 -system.cpu5: completed 10000 read, 5507 write accesses @81975000 -system.cpu3: completed 10000 read, 5421 write accesses @82381000 -system.cpu2: completed 20000 read, 10678 write accesses @153864500 -system.cpu0: completed 20000 read, 10854 write accesses @154789000 -system.cpu7: completed 20000 read, 10817 write accesses @154953500 -system.cpu1: completed 20000 read, 10781 write accesses @155855500 -system.cpu3: completed 20000 read, 10799 write accesses @157033000 -system.cpu4: completed 20000 read, 10854 write accesses @157158000 -system.cpu6: completed 20000 read, 10878 write accesses @157795000 -system.cpu5: completed 20000 read, 10963 write accesses @159866500 -system.cpu0: completed 30000 read, 16180 write accesses @228385000 -system.cpu2: completed 30000 read, 15995 write accesses @229109500 -system.cpu7: completed 30000 read, 16232 write accesses @231170000 -system.cpu1: completed 30000 read, 16165 write accesses @231658500 -system.cpu4: completed 30000 read, 16252 write accesses @232783000 -system.cpu6: completed 30000 read, 16228 write accesses @233712000 -system.cpu3: completed 30000 read, 16226 write accesses @236523000 -system.cpu5: completed 30000 read, 16456 write accesses @239602000 -system.cpu0: completed 40000 read, 21598 write accesses @305262000 -system.cpu2: completed 40000 read, 21332 write accesses @306571000 -system.cpu1: completed 40000 read, 21599 write accesses @307778500 -system.cpu4: completed 40000 read, 21599 write accesses @307971000 -system.cpu7: completed 40000 read, 21551 write accesses @308441000 -system.cpu6: completed 40000 read, 21597 write accesses @310397000 -system.cpu3: completed 40000 read, 21704 write accesses @312891000 -system.cpu5: completed 40000 read, 21914 write accesses @315565000 -system.cpu4: completed 50000 read, 26891 write accesses @381925000 -system.cpu0: completed 50000 read, 26990 write accesses @382095500 -system.cpu2: completed 50000 read, 26686 write accesses @382917500 -system.cpu1: completed 50000 read, 26983 write accesses @384289000 -system.cpu6: completed 50000 read, 27066 write accesses @384539000 -system.cpu7: completed 50000 read, 26943 write accesses @385136500 -system.cpu3: completed 50000 read, 27037 write accesses @389922000 -system.cpu5: completed 50000 read, 27423 write accesses @393691500 -system.cpu6: completed 60000 read, 32353 write accesses @457634500 -system.cpu4: completed 60000 read, 32228 write accesses @457992000 -system.cpu1: completed 60000 read, 32457 write accesses @460714000 -system.cpu2: completed 60000 read, 32178 write accesses @461196500 -system.cpu0: completed 60000 read, 32542 write accesses @461690000 -system.cpu7: completed 60000 read, 32302 write accesses @462388500 -system.cpu3: completed 60000 read, 32488 write accesses @466103000 -system.cpu5: completed 60000 read, 32744 write accesses @469778000 -system.cpu6: completed 70000 read, 37747 write accesses @533745000 -system.cpu2: completed 70000 read, 37532 write accesses @535320500 -system.cpu4: completed 70000 read, 37773 write accesses @535591500 -system.cpu7: completed 70000 read, 37639 write accesses @538124500 -system.cpu0: completed 70000 read, 37909 write accesses @538334500 -system.cpu1: completed 70000 read, 37921 write accesses @541231500 -system.cpu3: completed 70000 read, 37871 write accesses @542226500 -system.cpu5: completed 70000 read, 38229 write accesses @548322500 -system.cpu4: completed 80000 read, 42983 write accesses @610769500 -system.cpu6: completed 80000 read, 43020 write accesses @610776000 -system.cpu2: completed 80000 read, 42982 write accesses @611661000 -system.cpu0: completed 80000 read, 43374 write accesses @615085500 -system.cpu1: completed 80000 read, 43250 write accesses @615627500 -system.cpu7: completed 80000 read, 43033 write accesses @615746000 -system.cpu3: completed 80000 read, 43154 write accesses @619760000 -system.cpu5: completed 80000 read, 43738 write accesses @625688001 -system.cpu6: completed 90000 read, 48339 write accesses @685422000 -system.cpu2: completed 90000 read, 48272 write accesses @687608500 -system.cpu4: completed 90000 read, 48507 write accesses @688615500 -system.cpu7: completed 90000 read, 48310 write accesses @688789000 -system.cpu0: completed 90000 read, 48650 write accesses @689991000 -system.cpu1: completed 90000 read, 48621 write accesses @693117500 -system.cpu3: completed 90000 read, 48493 write accesses @697608000 -system.cpu5: completed 90000 read, 49008 write accesses @701381500 -system.cpu6: completed 100000 read, 53851 write accesses @761435500 +system.cpu6: completed 10000 read, 5217 write accesses @68085999 +system.cpu4: completed 10000 read, 5435 write accesses @69661000 +system.cpu2: completed 10000 read, 5368 write accesses @70121500 +system.cpu3: completed 10000 read, 5457 write accesses @70317500 +system.cpu1: completed 10000 read, 5387 write accesses @70875500 +system.cpu7: completed 10000 read, 5470 write accesses @70949000 +system.cpu0: completed 10000 read, 5435 write accesses @71227500 +system.cpu5: completed 10000 read, 5514 write accesses @71894000 +system.cpu6: completed 20000 read, 10518 write accesses @132327500 +system.cpu4: completed 20000 read, 10839 write accesses @133525000 +system.cpu1: completed 20000 read, 10784 write accesses @134714500 +system.cpu7: completed 20000 read, 10701 write accesses @135318500 +system.cpu0: completed 20000 read, 10821 write accesses @135563500 +system.cpu2: completed 20000 read, 10843 write accesses @135684500 +system.cpu3: completed 20000 read, 10685 write accesses @135938500 +system.cpu5: completed 20000 read, 11031 write accesses @136425000 +system.cpu6: completed 30000 read, 16001 write accesses @197849500 +system.cpu4: completed 30000 read, 16254 write accesses @198725500 +system.cpu0: completed 30000 read, 16109 write accesses @199579499 +system.cpu1: completed 30000 read, 16209 write accesses @200016500 +system.cpu5: completed 30000 read, 16414 write accesses @200525000 +system.cpu3: completed 30000 read, 15978 write accesses @200724000 +system.cpu7: completed 30000 read, 16153 write accesses @201563500 +system.cpu2: completed 30000 read, 16316 write accesses @202401999 +system.cpu4: completed 40000 read, 21506 write accesses @263053500 +system.cpu6: completed 40000 read, 21338 write accesses @263431500 +system.cpu5: completed 40000 read, 21670 write accesses @263987000 +system.cpu3: completed 40000 read, 21219 write accesses @264608000 +system.cpu1: completed 40000 read, 21536 write accesses @265348500 +system.cpu0: completed 40000 read, 21604 write accesses @265426500 +system.cpu7: completed 40000 read, 21465 write accesses @265674000 +system.cpu2: completed 40000 read, 21690 write accesses @268754000 +system.cpu6: completed 50000 read, 26563 write accesses @327819000 +system.cpu4: completed 50000 read, 27066 write accesses @328101000 +system.cpu5: completed 50000 read, 26900 write accesses @328372000 +system.cpu3: completed 50000 read, 26596 write accesses @328811500 +system.cpu1: completed 50000 read, 26845 write accesses @328908500 +system.cpu7: completed 50000 read, 26873 write accesses @331316999 +system.cpu0: completed 50000 read, 26988 write accesses @331358000 +system.cpu2: completed 50000 read, 27102 write accesses @333876000 +system.cpu1: completed 60000 read, 32156 write accesses @392077000 +system.cpu6: completed 60000 read, 31998 write accesses @392784000 +system.cpu5: completed 60000 read, 32223 write accesses @393227500 +system.cpu4: completed 60000 read, 32446 write accesses @394175000 +system.cpu3: completed 60000 read, 32090 write accesses @394842000 +system.cpu0: completed 60000 read, 32282 write accesses @395716500 +system.cpu7: completed 60000 read, 32292 write accesses @397180000 +system.cpu2: completed 60000 read, 32266 write accesses @397288500 +system.cpu6: completed 70000 read, 37440 write accesses @457780500 +system.cpu1: completed 70000 read, 37577 write accesses @458242500 +system.cpu5: completed 70000 read, 37616 write accesses @458643500 +system.cpu4: completed 70000 read, 37952 write accesses @459569500 +system.cpu3: completed 70000 read, 37486 write accesses @460007500 +system.cpu0: completed 70000 read, 37804 write accesses @461418499 +system.cpu2: completed 70000 read, 37588 write accesses @461790000 +system.cpu7: completed 70000 read, 37743 write accesses @462130500 +system.cpu1: completed 80000 read, 42976 write accesses @523192500 +system.cpu5: completed 80000 read, 43028 write accesses @523895500 +system.cpu6: completed 80000 read, 42870 write accesses @524155000 +system.cpu4: completed 80000 read, 43341 write accesses @524226000 +system.cpu3: completed 80000 read, 42885 write accesses @524383000 +system.cpu2: completed 80000 read, 43005 write accesses @527239000 +system.cpu7: completed 80000 read, 43156 write accesses @528371000 +system.cpu0: completed 80000 read, 43239 write accesses @528519000 +system.cpu3: completed 90000 read, 48037 write accesses @586595000 +system.cpu1: completed 90000 read, 48299 write accesses @588010000 +system.cpu4: completed 90000 read, 48806 write accesses @589147500 +system.cpu6: completed 90000 read, 48454 write accesses @589844000 +system.cpu5: completed 90000 read, 48341 write accesses @590185000 +system.cpu2: completed 90000 read, 48395 write accesses @591584000 +system.cpu7: completed 90000 read, 48496 write accesses @592485000 +system.cpu0: completed 90000 read, 48680 write accesses @594831500 +system.cpu3: completed 100000 read, 53536 write accesses @652606500 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout index 077a1416b..de32ac2d8 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout @@ -1,12 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr +Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 14:39:12 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest +gem5 compiled Sep 22 2013 05:53:51 +gem5 started Sep 22 2013 05:53:54 +gem5 executing on zizzer +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 761435500 because maximum number of loads reached +Exiting @ tick 652606500 because maximum number of loads reached diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index 8578074a3..68f83a492 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:03:41 +Real time: Sep/22/2013 05:27:12 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.62 -Virtual_time_in_minutes: 0.0103333 -Virtual_time_in_hours: 0.000172222 -Virtual_time_in_days: 7.17593e-06 +Virtual_time_in_seconds: 0.46 +Virtual_time_in_minutes: 0.00766667 +Virtual_time_in_hours: 0.000127778 +Virtual_time_in_days: 5.32407e-06 Ruby_current_time: 318321 Ruby_start_time: 0 Ruby_cycles: 318321 -mbytes_resident: 71.5117 -mbytes_total: 166.234 -resident_ratio: 0.43021 +mbytes_resident: 65.1133 +mbytes_total: 120.422 +resident_ratio: 0.54071 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr index cfdf73ce9..f5d2abbce 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr @@ -1 +1,5 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index fddb193cf..95d13e969 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubyt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:01:54 -gem5 started Sep 1 2012 14:05:06 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:27:02 +gem5 started Sep 22 2013 05:27:12 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 8785bdf38..6ce8e4111 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000318 # Nu sim_ticks 318321 # Number of ticks simulated final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1543352 # Simulator tick rate (ticks/s) -host_mem_usage 170228 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 1986485 # Simulator tick rate (ticks/s) +host_mem_usage 123316 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host system.ruby.l1_cntrl0.L1Dcache.demand_hits 81 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 861 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 942 # Number of cache demand accesses @@ -100,6 +100,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6864 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 51984 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 36936 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 272 +system.ruby.network.msg_count.Control 5373 +system.ruby.network.msg_count.Request_Control 1689 +system.ruby.network.msg_count.Response_Data 7724 +system.ruby.network.msg_count.Response_Control 7854 +system.ruby.network.msg_count.Writeback_Data 3705 +system.ruby.network.msg_count.Writeback_Control 102 +system.ruby.network.msg_byte.Control 42984 +system.ruby.network.msg_byte.Request_Control 13512 +system.ruby.network.msg_byte.Response_Data 556128 +system.ruby.network.msg_byte.Response_Control 62832 +system.ruby.network.msg_byte.Writeback_Data 266760 +system.ruby.network.msg_byte.Writeback_Control 816 system.ruby.network.routers0.throttle0.link_utilization 1.500686 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 563 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 915 @@ -222,18 +234,6 @@ system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00% system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00% system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00% system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00% -system.ruby.network.msg_count.Control 5373 -system.ruby.network.msg_count.Request_Control 1689 -system.ruby.network.msg_count.Response_Data 7724 -system.ruby.network.msg_count.Response_Control 7854 -system.ruby.network.msg_count.Writeback_Data 3705 -system.ruby.network.msg_count.Writeback_Control 102 -system.ruby.network.msg_byte.Control 42984 -system.ruby.network.msg_byte.Request_Control 13512 -system.ruby.network.msg_byte.Response_Data 556128 -system.ruby.network.msg_byte.Response_Control 62832 -system.ruby.network.msg_byte.Writeback_Data 266760 -system.ruby.network.msg_byte.Writeback_Control 816 system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 85c7a39c3..f29b9c43a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:04:54 +Real time: Sep/22/2013 05:36:23 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 1.04 -Virtual_time_in_minutes: 0.0173333 -Virtual_time_in_hours: 0.000288889 -Virtual_time_in_days: 1.2037e-05 +Virtual_time_in_seconds: 0.76 +Virtual_time_in_minutes: 0.0126667 +Virtual_time_in_hours: 0.000211111 +Virtual_time_in_days: 8.7963e-06 Ruby_current_time: 327361 Ruby_start_time: 0 Ruby_cycles: 327361 -mbytes_resident: 72.9453 -mbytes_total: 167.379 -resident_ratio: 0.435833 +mbytes_resident: 66.6211 +mbytes_total: 121.586 +resident_ratio: 0.547934 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr index cfdf73ce9..f5d2abbce 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr @@ -1 +1,5 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index c5a30e355..2167c1256 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.ruby gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 14:10:16 -gem5 started Sep 1 2012 14:14:49 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:36:12 +gem5 started Sep 22 2013 05:36:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 316521 because Ruby Tester completed +Exiting @ tick 327361 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 0d32f30e3..95db32b76 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000327 # Nu sim_ticks 327361 # Number of ticks simulated final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 545722 # Simulator tick rate (ticks/s) -host_mem_usage 171400 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host +host_tick_rate 746920 # Simulator tick rate (ticks/s) +host_mem_usage 124508 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host system.ruby.l1_cntrl0.L1Dcache.demand_hits 78 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 930 # Number of cache demand accesses @@ -96,6 +96,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14448 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 13520 system.ruby.network.routers3.msg_bytes.Writeback_Control::2 640 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14064 +system.ruby.network.msg_count.Request_Control 5287 +system.ruby.network.msg_count.Response_Data 5124 +system.ruby.network.msg_count.ResponseL2hit_Data 159 +system.ruby.network.msg_count.Writeback_Data 5004 +system.ruby.network.msg_count.Writeback_Control 10730 +system.ruby.network.msg_count.Unblock_Control 5275 +system.ruby.network.msg_byte.Request_Control 42296 +system.ruby.network.msg_byte.Response_Data 368928 +system.ruby.network.msg_byte.ResponseL2hit_Data 11448 +system.ruby.network.msg_byte.Writeback_Data 360288 +system.ruby.network.msg_byte.Writeback_Control 85840 +system.ruby.network.msg_byte.Unblock_Control 42200 system.ruby.network.routers0.throttle0.link_utilization 1.384710 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 854 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 53 @@ -218,18 +230,6 @@ system.ruby.l1_cntrl0.IS.Exclusive_Data 94 0.00% 0.00% system.ruby.l1_cntrl0.MI.Ifetch 136 0.00% 0.00% system.ruby.l1_cntrl0.MI.Store 115 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 903 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 5287 -system.ruby.network.msg_count.Response_Data 5124 -system.ruby.network.msg_count.ResponseL2hit_Data 159 -system.ruby.network.msg_count.Writeback_Data 5004 -system.ruby.network.msg_count.Writeback_Control 10730 -system.ruby.network.msg_count.Unblock_Control 5275 -system.ruby.network.msg_byte.Request_Control 42296 -system.ruby.network.msg_byte.Response_Data 368928 -system.ruby.network.msg_byte.ResponseL2hit_Data 11448 -system.ruby.network.msg_byte.Writeback_Data 360288 -system.ruby.network.msg_byte.Writeback_Control 85840 -system.ruby.network.msg_byte.Unblock_Control 42200 system.ruby.l2_cntrl0.L1_GETS 127 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 895 0.00% 0.00% system.ruby.l2_cntrl0.L1_PUTX 2308 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index d0fd81067..930f19cc4 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -1,24 +1,24 @@ -Real time: Aug/29/2013 10:04:46 +Real time: Sep/22/2013 05:45:00 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.6 -Virtual_time_in_minutes: 0.01 -Virtual_time_in_hours: 0.000166667 -Virtual_time_in_days: 6.94444e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 Ruby_current_time: 225141 Ruby_start_time: 0 Ruby_cycles: 225141 -mbytes_resident: 71.8008 -mbytes_total: 166.332 -resident_ratio: 0.431695 +mbytes_resident: 65.2617 +mbytes_total: 120.52 +resident_ratio: 0.543642 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr index cfdf73ce9..f5d2abbce 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr @@ -1 +1,5 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 6439642a6..733c0eefd 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:38:07 -gem5 started Sep 9 2012 13:38:15 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 22 2013 05:44:48 +gem5 started Sep 22 2013 05:44:59 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 637fd9943..c64681350 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000225 # Nu sim_ticks 225141 # Number of ticks simulated final_tick 225141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1294442 # Simulator tick rate (ticks/s) -host_mem_usage 170328 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 1688456 # Simulator tick rate (ticks/s) +host_mem_usage 123416 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host system.ruby.l1_cntrl0.L1Dcache.demand_hits 82 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 864 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 946 # Number of cache demand accesses @@ -90,6 +90,20 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 125136 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 576 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 5968 +system.ruby.network.msg_count.Request_Control 5349 +system.ruby.network.msg_count.Response_Data 2775 +system.ruby.network.msg_count.ResponseL2hit_Data 120 +system.ruby.network.msg_count.Response_Control 3 +system.ruby.network.msg_count.Writeback_Data 5214 +system.ruby.network.msg_count.Writeback_Control 216 +system.ruby.network.msg_count.Persistent_Control 2238 +system.ruby.network.msg_byte.Request_Control 42792 +system.ruby.network.msg_byte.Response_Data 199800 +system.ruby.network.msg_byte.ResponseL2hit_Data 8640 +system.ruby.network.msg_byte.Response_Control 24 +system.ruby.network.msg_byte.Writeback_Data 375408 +system.ruby.network.msg_byte.Writeback_Control 1728 +system.ruby.network.msg_byte.Persistent_Control 17904 system.ruby.network.routers0.throttle0.link_utilization 2.077809 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 898 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 40 @@ -216,20 +230,6 @@ system.ruby.l1_cntrl0.IS.Data_Shared 3 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data_All_Tokens 92 0.00% 0.00% system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock 19 0.00% 0.00% system.ruby.l1_cntrl0.IS.Request_Timeout 60 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 5349 -system.ruby.network.msg_count.Response_Data 2775 -system.ruby.network.msg_count.ResponseL2hit_Data 120 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 5214 -system.ruby.network.msg_count.Writeback_Control 216 -system.ruby.network.msg_count.Persistent_Control 2238 -system.ruby.network.msg_byte.Request_Control 42792 -system.ruby.network.msg_byte.Response_Data 199800 -system.ruby.network.msg_byte.ResponseL2hit_Data 8640 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 375408 -system.ruby.network.msg_byte.Writeback_Control 1728 -system.ruby.network.msg_byte.Persistent_Control 17904 system.ruby.l2_cntrl0.L1_GETS 95 0.00% 0.00% system.ruby.l2_cntrl0.L1_GETX 816 0.00% 0.00% system.ruby.l2_cntrl0.L2_Replacement 817 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index 4a6d034a2..2be80bfa3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:02:56 +Real time: Sep/22/2013 05:17:38 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.78 -Virtual_time_in_minutes: 0.013 -Virtual_time_in_hours: 0.000216667 -Virtual_time_in_days: 9.02778e-06 +Virtual_time_in_seconds: 0.38 +Virtual_time_in_minutes: 0.00633333 +Virtual_time_in_hours: 0.000105556 +Virtual_time_in_days: 4.39815e-06 Ruby_current_time: 172201 Ruby_start_time: 0 Ruby_cycles: 172201 -mbytes_resident: 72.0898 -mbytes_total: 166.262 -resident_ratio: 0.433616 +mbytes_resident: 65.8359 +mbytes_total: 120.496 +resident_ratio: 0.546374 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr index cfdf73ce9..f5d2abbce 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr @@ -1 +1,5 @@ +warn: rounding error > tolerance + 0.072760 rounded to 0 +warn: rounding error > tolerance + 0.072760 rounded to 0 hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 4f22200bf..980451a66 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/al gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 1 2012 13:53:26 -gem5 started Sep 1 2012 13:57:00 -gem5 executing on doudou.cs.wisc.edu +gem5 compiled Sep 22 2013 05:17:28 +gem5 started Sep 22 2013 05:17:38 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index e3dfac986..6281a101a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000172 # Nu sim_ticks 172201 # Number of ticks simulated final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 356372 # Simulator tick rate (ticks/s) -host_mem_usage 171280 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_tick_rate 1698559 # Simulator tick rate (ticks/s) +host_mem_usage 123392 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.ruby.l1_cntrl0.L1Dcache.demand_hits 70 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 848 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses @@ -81,6 +81,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6744 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6752 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 600 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6760 +system.ruby.network.msg_count.Request_Control 2554 +system.ruby.network.msg_count.Response_Data 2550 +system.ruby.network.msg_count.Writeback_Data 2303 +system.ruby.network.msg_count.Writeback_Control 5288 +system.ruby.network.msg_count.Unblock_Control 2535 +system.ruby.network.msg_byte.Request_Control 20432 +system.ruby.network.msg_byte.Response_Data 183600 +system.ruby.network.msg_byte.Writeback_Data 165816 +system.ruby.network.msg_byte.Writeback_Control 42304 +system.ruby.network.msg_byte.Unblock_Control 20280 system.ruby.network.routers0.throttle0.link_utilization 2.466304 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 850 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 844 @@ -185,16 +195,6 @@ system.ruby.l1_cntrl0.MI_F.Writeback_Ack 5 0.00% 0.00% system.ruby.l1_cntrl0.MM_F.Block_Ack 1 0.00% 0.00% system.ruby.l1_cntrl0.IM_F.Exclusive_Data 4 0.00% 0.00% system.ruby.l1_cntrl0.MM_WF.All_acks_no_sharers 4 0.00% 0.00% -system.ruby.network.msg_count.Request_Control 2554 -system.ruby.network.msg_count.Response_Data 2550 -system.ruby.network.msg_count.Writeback_Data 2303 -system.ruby.network.msg_count.Writeback_Control 5288 -system.ruby.network.msg_count.Unblock_Control 2535 -system.ruby.network.msg_byte.Request_Control 20432 -system.ruby.network.msg_byte.Response_Data 183600 -system.ruby.network.msg_byte.Writeback_Data 165816 -system.ruby.network.msg_byte.Writeback_Control 42304 -system.ruby.network.msg_byte.Unblock_Control 20280 system.ruby.dir_cntrl0.GETX 761 0.00% 0.00% system.ruby.dir_cntrl0.GETS 87 0.00% 0.00% system.ruby.dir_cntrl0.PUT 913 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index cd80434d6..0797fe00b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Aug/29/2013 10:04:34 +Real time: Sep/28/2013 03:05:49 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.48 -Virtual_time_in_minutes: 0.008 -Virtual_time_in_hours: 0.000133333 -Virtual_time_in_days: 5.55556e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 221941 Ruby_start_time: 0 Ruby_cycles: 221941 -mbytes_resident: 70.1602 -mbytes_total: 164.824 -resident_ratio: 0.42569 +mbytes_resident: 63.7617 +mbytes_total: 118.02 +resident_ratio: 0.540264 Busy Controller Counts: L1Cache-0:0 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr index 8308e8186..f5d2abbce 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr @@ -1,5 +1,5 @@ -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 -Warning: rounding error > tolerance +warn: rounding error > tolerance 0.072760 rounded to 0 hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 5f78b5f64..6606669ac 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rub gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:07:36 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 03:05:49 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index c503a22e4..34979640b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000222 # Nu sim_ticks 221941 # Number of ticks simulated final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2220183 # Simulator tick rate (ticks/s) -host_mem_usage 168784 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 2784815 # Simulator tick rate (ticks/s) +host_mem_usage 121880 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host system.ruby.l1_cntrl0.cacheMemory.demand_hits 38 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 917 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 955 # Number of cache demand accesses @@ -54,6 +54,14 @@ system.ruby.network.routers2.msg_bytes.Control::2 7328 system.ruby.network.routers2.msg_bytes.Data::2 65808 system.ruby.network.routers2.msg_bytes.Response_Data::4 65952 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7304 +system.ruby.network.msg_count.Control 2748 +system.ruby.network.msg_count.Data 2742 +system.ruby.network.msg_count.Response_Data 2748 +system.ruby.network.msg_count.Writeback_Control 2739 +system.ruby.network.msg_byte.Control 21984 +system.ruby.network.msg_byte.Data 197424 +system.ruby.network.msg_byte.Response_Data 197856 +system.ruby.network.msg_byte.Writeback_Control 21912 system.ruby.network.routers0.throttle0.link_utilization 2.062936 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 916 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 913 @@ -99,14 +107,6 @@ system.ruby.l1_cntrl0.M.Replacement 914 0.00% 0.00% system.ruby.l1_cntrl0.MI.Writeback_Ack 912 0.00% 0.00% system.ruby.l1_cntrl0.IS.Data 98 0.00% 0.00% system.ruby.l1_cntrl0.IM.Data 818 0.00% 0.00% -system.ruby.network.msg_count.Control 2748 -system.ruby.network.msg_count.Data 2742 -system.ruby.network.msg_count.Response_Data 2748 -system.ruby.network.msg_count.Writeback_Control 2739 -system.ruby.network.msg_byte.Control 21984 -system.ruby.network.msg_byte.Data 197424 -system.ruby.network.msg_byte.Response_Data 197856 -system.ruby.network.msg_byte.Writeback_Control 21912 system.ruby.dir_cntrl0.GETX 916 0.00% 0.00% system.ruby.dir_cntrl0.PUTX 914 0.00% 0.00% system.ruby.dir_cntrl0.Memory_Data 916 0.00% 0.00% diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini new file mode 100644 index 000000000..61b6eb32e --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini @@ -0,0 +1,116 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu membus monitor physmem +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +voltage=1.000000 + +[system.cpu] +type=TrafficGen +clk_domain=system.clk_domain +config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg +elastic_req=false +system=system +port=system.monitor.slave + +[system.membus] +type=NoncoherentBus +clk_domain=system.clk_domain +header_cycles=1 +use_default_range=false +width=16 +master=system.physmem.port +slave=system.monitor.master system.system_port + +[system.monitor] +type=CommMonitor +bandwidth_bins=20 +burst_length_bins=20 +clk_domain=system.clk_domain +disable_addr_dists=true +disable_bandwidth_hists=false +disable_burst_length_hists=false +disable_itt_dists=false +disable_latency_hists=false +disable_outstanding_hists=false +disable_transaction_hists=false +itt_bins=20 +itt_max_bin=100000 +latency_bins=20 +outstanding_bins=20 +read_addr_mask=18446744073709551615 +sample_period=1000000000 +trace_file= +transaction_bins=20 +write_addr_mask=18446744073709551615 +master=system.membus.slave[0] +slave=system.cpu.port + +[system.physmem] +type=SimpleDRAM +activation_limit=4 +addr_mapping=RaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +in_addr_map=true +mem_sched_policy=frfcfs +null=false +page_policy=open +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tWTR=7500 +tXAW=40000 +write_buffer_size=32 +write_thresh_perc=70 +port=system.membus.master[0] + diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr index cfdf73ce9..e69de29bb 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr @@ -1 +0,0 @@ -hack: be nice to actually delete the event here diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout index d1faa751a..2426a6cee 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 6 2012 15:52:45 -gem5 started Aug 6 2012 15:56:03 -gem5 executing on 61f1f4j -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram +gem5 compiled Sep 22 2013 05:53:51 +gem5 started Sep 22 2013 05:53:54 +gem5 executing on zizzer +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 300940000 because Done +Exiting @ tick 100000000000 because simulate() limit reached diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini new file mode 100644 index 000000000..27a6fb9af --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu membus monitor physmem +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +voltage=1.000000 + +[system.cpu] +type=TrafficGen +clk_domain=system.clk_domain +config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg +elastic_req=false +system=system +port=system.monitor.slave + +[system.membus] +type=NoncoherentBus +clk_domain=system.clk_domain +header_cycles=1 +use_default_range=false +width=16 +master=system.physmem.port +slave=system.monitor.master system.system_port + +[system.monitor] +type=CommMonitor +bandwidth_bins=20 +burst_length_bins=20 +clk_domain=system.clk_domain +disable_addr_dists=true +disable_bandwidth_hists=false +disable_burst_length_hists=false +disable_itt_dists=false +disable_latency_hists=false +disable_outstanding_hists=false +disable_transaction_hists=false +itt_bins=20 +itt_max_bin=100000 +latency_bins=20 +outstanding_bins=20 +read_addr_mask=18446744073709551615 +sample_period=1000000000 +trace_file=monitor.ptrc.gz +transaction_bins=20 +write_addr_mask=18446744073709551615 +master=system.membus.slave[0] +slave=system.cpu.port + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index 727a89c99..efa3fa542 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 25 2012 13:56:00 -gem5 started Aug 25 2012 13:58:17 -gem5 executing on Andreas-MacBook-Pro.local -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem +gem5 compiled Sep 22 2013 05:53:51 +gem5 started Sep 22 2013 05:53:54 +gem5 executing on zizzer +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 100000000000 because simulate() limit reached |