diff options
Diffstat (limited to 'tests/quick/se')
228 files changed, 3519 insertions, 942 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 8be59c81c..38d5b70ef 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -113,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -127,11 +135,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -148,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -162,17 +175,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +200,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -189,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -203,12 +224,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +242,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +252,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -241,11 +267,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +293,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +305,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index b50e34b75..b1e32f7df 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:26 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:08 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 25046000 because target called exit() +Exiting @ tick 25485000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 3b67933ac..116ba4c72 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000025 # Nu sim_ticks 25485000 # Number of ticks simulated final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27492 # Simulator instruction rate (inst/s) -host_op_rate 27490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109632626 # Simulator tick rate (ticks/s) -host_mem_usage 225100 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 24806 # Simulator instruction rate (inst/s) +host_op_rate 24805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98922905 # Simulator tick rate (ticks/s) +host_mem_usage 229760 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 29952 # Number of bytes read from this memory @@ -214,6 +216,7 @@ system.membus.reqLayer0.occupancy 560000 # La system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -325,6 +328,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.146973 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2131 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2131 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -430,6 +439,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012054 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4228 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -553,6 +568,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 07eaff0f1..6e7555e80 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 589b57e2d..5b34c9429 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:08 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 20671000 because target called exit() +Exiting @ tick 21065000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index cfed15046..7833baea6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000021 # Nu sim_ticks 21065000 # Number of ticks simulated final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36663 # Simulator instruction rate (inst/s) -host_op_rate 36659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121177991 # Simulator tick rate (ticks/s) -host_mem_usage 273132 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 40027 # Simulator instruction rate (inst/s) +host_op_rate 40023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132300521 # Simulator tick rate (ticks/s) +host_mem_usage 230780 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory system.physmem.bytes_read::total 31168 # Number of bytes read from this memory @@ -214,6 +216,7 @@ system.membus.reqLayer0.occupancy 619000 # La system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2883 # Number of BP lookups system.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect @@ -544,6 +547,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 5078 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5078 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits @@ -630,6 +639,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -753,6 +768,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index 3d9687a29..06ea19107 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index 1fb01db1e..1ccb73543 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:26 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:08 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 469297f21..26873a78e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2502 # Simulator instruction rate (inst/s) -host_op_rate 2502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1255935 # Simulator tick rate (ticks/s) -host_mem_usage 215792 # Number of bytes of host memory used -host_seconds 2.55 # Real time elapsed on the host +host_inst_rate 44230 # Simulator instruction rate (inst/s) +host_op_rate 44225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22200446 # Simulator tick rate (ticks/s) +host_mem_usage 220024 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory system.physmem.bytes_read::total 34388 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 12806733167 # To system.membus.throughput 12806733167 # Throughput (bytes/s) system.membus.data_through_bus 41084 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini index 0a3882bba..1d40a69d9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini @@ -88,6 +88,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -107,7 +108,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout index 5fac9bcf7..703a818a3 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:27:02 -gem5 started Sep 22 2013 05:27:12 -gem5 executing on zizzer -command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Jan 22 2014 16:37:52 +gem5 started Jan 22 2014 17:25:49 +gem5 executing on u200540-lin +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index dd7fe91b8..9dc55b67c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20823 # Simulator instruction rate (inst/s) -host_op_rate 20821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 451640 # Simulator tick rate (ticks/s) -host_mem_usage 170972 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host +host_inst_rate 26295 # Simulator instruction rate (inst/s) +host_op_rate 26294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570348 # Simulator tick rate (ticks/s) +host_mem_usage 126360 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 9645 # delay histogram for all message @@ -100,6 +103,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6392 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes @@ -149,6 +153,7 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 454f386da..055a078bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,9 +156,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=6 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -151,6 +170,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -167,6 +187,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -186,7 +207,8 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -204,6 +226,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -218,6 +241,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -233,6 +257,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -250,7 +275,8 @@ children=L2cache L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 number_of_TBEs=256 peer=Null recycle_latency=10 @@ -265,6 +291,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=15 replacement_policy=PSEUDO_LRU @@ -278,6 +305,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -287,6 +315,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -297,6 +326,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -306,6 +336,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -315,6 +346,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -324,6 +356,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -333,6 +366,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -342,6 +376,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -351,38 +386,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -394,5 +427,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 7aebf91e4..e44640397 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:36:12 -gem5 started Sep 22 2013 05:36:34 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:42:56 +gem5 started Jan 22 2014 17:26:22 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 6769cc2eb..97b9e8b98 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18637 # Simulator instruction rate (inst/s) -host_op_rate 18636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 342978 # Simulator tick rate (ticks/s) -host_mem_usage 174220 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host +host_inst_rate 23182 # Simulator instruction rate (inst/s) +host_op_rate 23181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 426626 # Simulator tick rate (ticks/s) +host_mem_usage 130676 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 8449 @@ -82,6 +85,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 17488 system.ruby.network.routers1.msg_bytes.Writeback_Control::2 7192 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 19768 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1303 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 1109 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 194 # Number of memory writes @@ -139,6 +143,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 54648 system.ruby.network.msg_byte.Writeback_Data 334368 system.ruby.network.msg_byte.Writeback_Control 139032 system.ruby.network.msg_byte.Unblock_Control 59304 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 98cbeddd9..c83923549 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,10 +156,11 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true +eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 memBuffer=system.ruby.dir_cntrl0.memBuffer @@ -155,6 +174,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -171,6 +191,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -191,8 +212,9 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -215,6 +237,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -229,6 +252,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -244,6 +268,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -262,7 +287,8 @@ L2cache=system.ruby.l2_cntrl0.L2cache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 @@ -278,6 +304,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -291,6 +318,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -300,6 +328,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -310,6 +339,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -319,6 +349,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -328,6 +359,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -337,6 +369,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -346,6 +379,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -355,6 +389,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -364,38 +399,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -407,5 +440,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 972ce6ed2..05cd140ea 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:44:48 -gem5 started Sep 22 2013 05:44:59 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:47:59 +gem5 started Jan 22 2014 17:27:26 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 5443611c7..47e7c5bb6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 15419 # Simulator instruction rate (inst/s) -host_op_rate 15419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274163 # Simulator tick rate (ticks/s) -host_mem_usage 171088 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host +host_inst_rate 25426 # Simulator instruction rate (inst/s) +host_op_rate 25424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 452072 # Simulator tick rate (ticks/s) +host_mem_usage 127540 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 8449 @@ -76,6 +79,7 @@ system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113976 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7736 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1407 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 1178 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 229 # Number of memory writes @@ -125,6 +129,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 44064 system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341928 system.ruby.network.msg_byte.Writeback_Control 23208 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 5efa528b0..bbaaafb7c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,8 +156,9 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory +eventq_index=0 full_bit_dir_enabled=false memBuffer=system.ruby.dir_cntrl0.memBuffer memory_controller_latency=2 @@ -154,6 +173,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -170,6 +190,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -187,6 +208,7 @@ type=RubyCache assoc=4 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=1 replacement_policy=PSEUDO_LRU @@ -205,7 +227,8 @@ L2cache=system.ruby.l1_cntrl0.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -223,6 +246,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -237,6 +261,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -251,6 +276,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -266,6 +292,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -281,6 +308,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -290,6 +318,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -300,6 +329,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -309,6 +339,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -318,6 +349,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -327,6 +359,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -336,32 +369,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -373,5 +403,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 2f946fb64..74d9e5871 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:17:28 -gem5 started Sep 22 2013 05:18:00 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:32:54 +gem5 started Jan 22 2014 17:25:16 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index da745542b..afdd49aff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30230 # Simulator instruction rate (inst/s) -host_op_rate 30227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 441501 # Simulator tick rate (ticks/s) -host_mem_usage 171020 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 34391 # Simulator instruction rate (inst/s) +host_op_rate 34389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 502293 # Simulator tick rate (ticks/s) +host_mem_usage 127476 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 8449 @@ -43,6 +46,7 @@ system.ruby.miss_latency_hist::stdev 10.823033 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1098 94.74% 94.74% | 9 0.78% 95.51% | 24 2.07% 97.58% | 0 0.00% 97.58% | 27 2.33% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1159 system.ruby.Directory.incomplete_times 1158 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses @@ -124,6 +128,7 @@ system.ruby.network.msg_byte.Response_Data 250344 system.ruby.network.msg_byte.Writeback_Data 47520 system.ruby.network.msg_byte.Writeback_Control 77016 system.ruby.network.msg_byte.Unblock_Control 27816 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 5c6bf177e..080d250b7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,9 +156,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -151,6 +170,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -167,6 +187,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -186,7 +207,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -202,6 +224,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -217,6 +240,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -232,6 +256,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -241,6 +266,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -251,6 +277,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -260,6 +287,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -269,6 +297,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -278,6 +307,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -287,32 +317,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -324,5 +351,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index cedef1822..e7d414efc 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:20 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 6d4e698a8..19e4fff41 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26416 # Simulator instruction rate (inst/s) -host_op_rate 26414 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 594577 # Simulator tick rate (ticks/s) -host_mem_usage 170576 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 41580 # Simulator instruction rate (inst/s) +host_op_rate 41576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 935887 # Simulator tick rate (ticks/s) +host_mem_usage 126996 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3456 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 7.725779 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 336 19.42% 19.42% | 1251 72.31% 91.73% | 136 7.86% 99.60% | 5 0.29% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1730 system.ruby.Directory.incomplete_times 1729 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses @@ -99,6 +103,7 @@ system.ruby.network.msg_byte.Control 41520 system.ruby.network.msg_byte.Data 372816 system.ruby.network.msg_byte.Response_Data 373680 system.ruby.network.msg_byte.Writeback_Control 41424 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 595a8159f..b0e615a7c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index b5f87b785..03ecf7225 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:26 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:16 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 6038d0a3c..84f056acc 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27670 # Simulator instruction rate (inst/s) -host_op_rate 27667 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140894748 # Simulator tick rate (ticks/s) -host_mem_usage 224272 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 61527 # Simulator instruction rate (inst/s) +host_op_rate 61510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 313188739 # Simulator tick rate (ticks/s) +host_mem_usage 228704 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 446000 # La system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -106,6 +109,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13081 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -186,6 +195,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -309,6 +324,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index b9dbe7d51..15208c06e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -151,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -165,26 +174,32 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +208,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +229,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +257,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +285,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +299,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +446,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +460,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +481,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +497,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -449,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -463,17 +521,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +546,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -490,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -504,12 +570,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +588,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +598,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -542,11 +613,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +639,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +651,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr index 27f858d8f..62976a831 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 4cf5ca9ef..da1484dec 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:20 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11933500 because target called exit() +Exiting @ tick 11990500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 5e19e4b84..baea5f5eb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000012 # Nu sim_ticks 11990500 # Number of ticks simulated final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47015 # Simulator instruction rate (inst/s) -host_op_rate 46988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 235942636 # Simulator tick rate (ticks/s) -host_mem_usage 225832 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 21306 # Simulator instruction rate (inst/s) +host_op_rate 21301 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106974940 # Simulator tick rate (ticks/s) +host_mem_usage 229436 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17472 # Number of bytes read from this memory @@ -211,6 +213,7 @@ system.membus.reqLayer0.occupancy 344000 # La system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1176 # Number of BP lookups system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect @@ -541,6 +544,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2318 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2318 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits @@ -627,6 +636,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007599 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2457 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2457 # Number of data accesses system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -744,6 +759,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1989 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1989 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index b66459c3a..aca9f495e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr index bcbfa5445..32998f270 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,4 +1,2 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index 034bc5823..33ba2e738 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:20 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index aec79b975..04acc5c7e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388869 # Simulator instruction rate (inst/s) -host_op_rate 388153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 195100518 # Simulator tick rate (ticks/s) -host_mem_usage 215488 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 31206 # Simulator instruction rate (inst/s) +host_op_rate 31196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15701703 # Simulator tick rate (ticks/s) +host_mem_usage 219708 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory system.physmem.bytes_read::total 13356 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 11879768786 # To system.membus.throughput 11879768786 # Throughput (bytes/s) system.membus.data_through_bus 15414 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index f2dc4f3e0..8168c285c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -88,6 +88,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -107,7 +108,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr index 492f3e68f..a30a2a95c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr @@ -4,4 +4,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout index 5722711d2..f35dc8674 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:27:02 -gem5 started Sep 22 2013 05:27:13 -gem5 executing on zizzer -command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Jan 22 2014 16:37:52 +gem5 started Jan 22 2014 17:26:00 +gem5 executing on u200540-lin +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 52575 because target called exit() +Exiting @ tick 52548 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 1d9a45506..96547c7d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16682 # Simulator instruction rate (inst/s) -host_op_rate 16680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 340078 # Simulator tick rate (ticks/s) -host_mem_usage 169540 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 25744 # Simulator instruction rate (inst/s) +host_op_rate 25740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 524809 # Simulator tick rate (ticks/s) +host_mem_usage 124924 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3612 # delay histogram for all message @@ -100,6 +103,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes @@ -148,6 +152,7 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 1cc47929f..647bb1e23 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,9 +156,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=6 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -151,6 +170,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -167,6 +187,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -186,7 +207,8 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -204,6 +226,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -218,6 +241,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -233,6 +257,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -250,7 +275,8 @@ children=L2cache L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 number_of_TBEs=256 peer=Null recycle_latency=10 @@ -265,6 +291,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=15 replacement_policy=PSEUDO_LRU @@ -278,6 +305,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -287,6 +315,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -297,6 +326,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -306,6 +336,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -315,6 +346,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -324,6 +356,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -333,6 +366,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -342,6 +376,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -351,38 +386,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -394,5 +427,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr index 492f3e68f..a30a2a95c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -4,4 +4,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index e2683dd74..c37233c6d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:36:12 -gem5 started Sep 22 2013 05:36:23 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:42:56 +gem5 started Jan 22 2014 17:26:33 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 5ece97b1b..b3553454d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16150 # Simulator instruction rate (inst/s) -host_op_rate 16148 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 281738 # Simulator tick rate (ticks/s) -host_mem_usage 171884 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 17948 # Simulator instruction rate (inst/s) +host_op_rate 17946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 313128 # Simulator tick rate (ticks/s) +host_mem_usage 128348 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 3295 @@ -82,6 +85,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 6512 system.ruby.network.routers1.msg_bytes.Writeback_Control::2 2648 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 7464 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 499 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 423 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 76 # Number of memory writes @@ -139,6 +143,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 18792 system.ruby.network.msg_byte.Writeback_Data 124848 system.ruby.network.msg_byte.Writeback_Control 51576 system.ruby.network.msg_byte.Unblock_Control 22384 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 57448e3a7..2bf0001da 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,10 +156,11 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true +eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 memBuffer=system.ruby.dir_cntrl0.memBuffer @@ -155,6 +174,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -171,6 +191,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -191,8 +212,9 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -215,6 +237,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -229,6 +252,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -244,6 +268,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -262,7 +287,8 @@ L2cache=system.ruby.l2_cntrl0.L2cache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 @@ -278,6 +304,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -291,6 +318,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -300,6 +328,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -310,6 +339,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -319,6 +349,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -328,6 +359,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -337,6 +369,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -346,6 +379,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -355,6 +389,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -364,38 +399,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -407,5 +440,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr index 492f3e68f..a30a2a95c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr @@ -4,4 +4,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 76c77f4a5..b3289a2c7 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:44:48 -gem5 started Sep 22 2013 05:45:00 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:47:59 +gem5 started Jan 22 2014 17:27:30 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 17ea98764..0c82e32e7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 7100 # Simulator instruction rate (inst/s) -host_op_rate 7100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118667 # Simulator tick rate (ticks/s) -host_mem_usage 169652 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 26553 # Simulator instruction rate (inst/s) +host_op_rate 26550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 443703 # Simulator tick rate (ticks/s) +host_mem_usage 126100 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 3295 @@ -76,6 +79,7 @@ system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 532 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 448 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 84 # Number of memory writes @@ -125,6 +129,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 15120 system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index fed15fed0..1829ec00a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,8 +156,9 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory +eventq_index=0 full_bit_dir_enabled=false memBuffer=system.ruby.dir_cntrl0.memBuffer memory_controller_latency=2 @@ -154,6 +173,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -170,6 +190,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -187,6 +208,7 @@ type=RubyCache assoc=4 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=1 replacement_policy=PSEUDO_LRU @@ -205,7 +227,8 @@ L2cache=system.ruby.l1_cntrl0.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -223,6 +246,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -237,6 +261,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -251,6 +276,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -266,6 +292,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -281,6 +308,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -290,6 +318,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -300,6 +329,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -309,6 +339,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -318,6 +349,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -327,6 +359,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -336,32 +369,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -373,5 +403,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index 492f3e68f..a30a2a95c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -4,4 +4,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index fa7b05ab3..74d6c0f17 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:17:28 -gem5 started Sep 22 2013 05:17:49 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:32:54 +gem5 started Jan 22 2014 17:25:27 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index fc4b80ac1..fe7ac0efa 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20063 # Simulator instruction rate (inst/s) -host_op_rate 20060 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275767 # Simulator tick rate (ticks/s) -host_mem_usage 169584 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 28350 # Simulator instruction rate (inst/s) +host_op_rate 28346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 389675 # Simulator tick rate (ticks/s) +host_mem_usage 126044 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 3295 @@ -43,6 +46,7 @@ system.ruby.miss_latency_hist::stdev 8.819211 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 421 95.46% 95.46% | 2 0.45% 95.92% | 12 2.72% 98.64% | 0 0.00% 98.64% | 6 1.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 441 system.ruby.Directory.incomplete_times 440 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -123,6 +127,7 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 56f1e35ca..360da34a5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +124,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +133,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,9 +156,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -151,6 +170,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -167,6 +187,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -186,7 +207,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -202,6 +224,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -217,6 +240,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -232,6 +256,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -241,6 +266,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -251,6 +277,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -260,6 +287,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -269,6 +297,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -278,6 +307,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -287,32 +317,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -324,5 +351,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr index 492f3e68f..a30a2a95c 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr @@ -4,4 +4,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 980ebae91..11cc12ff4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:30 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index a74ef311a..845b4481e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27660 # Simulator instruction rate (inst/s) -host_op_rate 27654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 563232 # Simulator tick rate (ticks/s) -host_mem_usage 168112 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 24935 # Simulator instruction rate (inst/s) +host_op_rate 24932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 507835 # Simulator tick rate (ticks/s) +host_mem_usage 124536 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1248 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.377524 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 626 system.ruby.Directory.incomplete_times 625 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses @@ -98,6 +102,7 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 81f228137..7ab4d5c2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr index 31ae36f2e..32998f270 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index f5b60c70f..cd7b05e76 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:26 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 0eefef01d..3fc7cd393 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70 # Simulator instruction rate (inst/s) -host_op_rate 70 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 446596 # Simulator tick rate (ticks/s) -host_mem_usage 222964 # Number of bytes of host memory used -host_seconds 37.00 # Real time elapsed on the host +host_inst_rate 33204 # Simulator instruction rate (inst/s) +host_op_rate 33192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 212757424 # Simulator tick rate (ticks/s) +host_mem_usage 228444 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory system.physmem.bytes_read::total 15680 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 245000 # La system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -106,6 +109,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5335 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -186,6 +195,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -303,6 +318,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 91966eab0..5c3361f47 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -147,6 +154,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +eventq_index=0 exitOnError=false function_trace=false function_trace_start=0 @@ -171,18 +179,21 @@ workload=system.cpu.workload [system.cpu.checker.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -201,18 +212,21 @@ midr=890224640 [system.cpu.checker.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -220,6 +234,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -228,6 +243,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -242,18 +258,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -262,15 +282,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -279,16 +302,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -297,22 +323,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -321,22 +351,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -345,10 +379,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -357,124 +393,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -483,10 +540,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -495,16 +554,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -513,10 +575,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -527,6 +591,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -535,6 +600,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -549,14 +615,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -575,12 +645,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -591,6 +663,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -599,6 +672,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -613,12 +687,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -628,6 +705,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -637,7 +715,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -651,11 +730,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -675,6 +756,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -686,17 +768,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 47104f06c..dc275e0b8 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 01:55:20 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:22 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 16494000 because target called exit() +Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 6f535bcb9..8e11038e3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41552 # Simulator instruction rate (inst/s) -host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153628168 # Simulator tick rate (ticks/s) -host_mem_usage 240508 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 35724 # Simulator instruction rate (inst/s) +host_op_rate 44574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132106037 # Simulator tick rate (ticks/s) +host_mem_usage 247896 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory system.physmem.bytes_read::total 25088 # Number of bytes read from this memory @@ -215,6 +217,7 @@ system.membus.reqLayer0.occupancy 483500 # La system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect @@ -597,6 +600,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4184 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits @@ -683,6 +692,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -815,6 +830,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 507cb5799..9b066fde0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -151,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -165,18 +174,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +198,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +218,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +239,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +267,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +295,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +309,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +456,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +470,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +491,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +507,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -458,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -472,14 +531,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +561,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +579,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -522,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -536,12 +603,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +621,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +631,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -574,11 +646,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +672,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +684,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index d3be13c32..5df86194c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 01:55:13 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:21 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 16494000 because target called exit() +Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 1007daea2..3ffee0645 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59313 # Simulator instruction rate (inst/s) -host_op_rate 73997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 219275591 # Simulator tick rate (ticks/s) -host_mem_usage 240508 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 34743 # Simulator instruction rate (inst/s) +host_op_rate 43351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 128481440 # Simulator tick rate (ticks/s) +host_mem_usage 246872 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory system.physmem.bytes_read::total 25088 # Number of bytes read from this memory @@ -215,6 +217,7 @@ system.membus.reqLayer0.occupancy 483500 # La system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect @@ -552,6 +555,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4184 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits @@ -638,6 +647,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -770,6 +785,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 05132e433..1158c75dc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -82,6 +87,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +eventq_index=0 exitOnError=false function_trace=false function_trace_start=0 @@ -106,17 +112,20 @@ workload=system.cpu.workload [system.cpu.checker.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu.checker.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -135,36 +144,43 @@ midr=890224640 [system.cpu.checker.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu.checker.tracer] type=ExeTracer +eventq_index=0 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -183,18 +199,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -204,7 +223,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -218,11 +238,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -235,6 +257,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -244,5 +267,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 3a9ca0eef..7509c2dae 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:10:56 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:32 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 05df8bae0..4b1e74a91 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 686137 # Simulator instruction rate (inst/s) -host_op_rate 854515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 427336749 # Simulator tick rate (ticks/s) -host_mem_usage 232512 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 61907 # Simulator instruction rate (inst/s) +host_op_rate 77238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38693079 # Simulator tick rate (ticks/s) +host_mem_usage 237008 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::total 22907 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9251001568 # To system.membus.throughput 9251001568 # Throughput (bytes/s) system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index ea8fd73bf..8e0b67b72 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 7cee6c9ed..618f6d613 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:14:08 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:32 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index ea8a36796..ea0a0e09c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 723203 # Simulator instruction rate (inst/s) -host_op_rate 900650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 450384934 # Simulator tick rate (ticks/s) -host_mem_usage 232532 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 81917 # Simulator instruction rate (inst/s) +host_op_rate 102184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51187301 # Simulator tick rate (ticks/s) +host_mem_usage 236980 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::total 22907 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9251001568 # To system.membus.throughput 9251001568 # Throughput (bytes/s) system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index aa887d8df..bae9efedf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index db0e6caaf..6834abec2 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:24:32 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 13e2763d6..a3962cb85 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229244 # Simulator instruction rate (inst/s) -host_op_rate 284503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1301168988 # Simulator tick rate (ticks/s) -host_mem_usage 238660 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 84539 # Simulator instruction rate (inst/s) +host_op_rate 105013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 480681007 # Simulator tick rate (ticks/s) +host_mem_usage 245716 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 350000 # La system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -116,6 +119,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9451 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -196,6 +205,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits @@ -322,6 +337,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4303 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4303 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 2a0a5918d..734275a58 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -113,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -127,11 +135,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -148,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -162,19 +175,25 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -183,6 +202,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -191,6 +211,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -205,12 +226,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -220,6 +244,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -229,7 +254,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -243,11 +269,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -267,6 +295,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -278,17 +307,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 0184d25db..5a8e6736f 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:06 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:27:52 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 24587000 because target called exit() +Exiting @ tick 24975000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 3c2a96518..3e4b6f41c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000025 # Nu sim_ticks 24975000 # Number of ticks simulated final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84511 # Simulator instruction rate (inst/s) -host_op_rate 84494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 362882134 # Simulator tick rate (ticks/s) -host_mem_usage 254488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 42229 # Simulator instruction rate (inst/s) +host_op_rate 42225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181364329 # Simulator tick rate (ticks/s) +host_mem_usage 230516 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 29120 # Number of bytes read from this memory @@ -212,6 +214,7 @@ system.membus.reqLayer0.occupancy 552000 # La system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect @@ -309,6 +312,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.149414 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1875 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1875 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -414,6 +423,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012329 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4111 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4111 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -537,6 +552,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4314 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4314 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 90b395123..df84ba05d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -531,6 +535,7 @@ type=MipsISA eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB @@ -552,6 +557,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -568,6 +574,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -594,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index a390bccf8..3925c4814 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:28:28 -gem5 started Oct 16 2013 01:35:02 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:28:02 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 21805500 because target called exit() +Exiting @ tick 21898500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 3589948bc..b4a732973 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000022 # Nu sim_ticks 21898500 # Number of ticks simulated final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34889 # Simulator instruction rate (inst/s) -host_op_rate 34885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148144968 # Simulator tick rate (ticks/s) -host_mem_usage 274956 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 38049 # Simulator instruction rate (inst/s) +host_op_rate 38045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 161516903 # Simulator tick rate (ticks/s) +host_mem_usage 231544 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory system.physmem.bytes_read::total 30528 # Number of bytes read from this memory @@ -212,6 +214,7 @@ system.membus.reqLayer0.occupancy 605000 # La system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect @@ -526,6 +529,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4268 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits @@ -612,6 +621,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -735,6 +750,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 917891d7e..cb74c0ee3 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,22 +79,28 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -99,7 +110,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -113,11 +125,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -130,6 +144,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -139,5 +154,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index b1c55ad09..4635935c5 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:07 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:28:13 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index e850cb6a0..fb6eb7154 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 727521 # Simulator instruction rate (inst/s) -host_op_rate 725084 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 361375060 # Simulator tick rate (ticks/s) -host_mem_usage 216568 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 88855 # Simulator instruction rate (inst/s) +host_op_rate 88837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44409305 # Simulator tick rate (ticks/s) +host_mem_usage 220784 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4374 # Number of bytes read from this memory system.physmem.bytes_read::total 27634 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 10764361885 # To system.membus.throughput 10764361885 # Throughput (bytes/s) system.membus.data_through_bus 31292 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 793123a59..d40656fb3 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,26 +73,33 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +109,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -113,6 +126,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -121,18 +135,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -140,9 +158,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -153,6 +172,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -169,6 +189,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -188,7 +209,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -204,6 +226,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -219,6 +242,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -234,6 +258,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -243,6 +268,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -253,6 +279,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -262,6 +289,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -271,6 +299,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -280,6 +309,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -289,32 +319,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -326,5 +353,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 5beaf8240..3e5d01afe 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:07 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:28:34 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index eabbcdd0e..f6e1459a7 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30165 # Simulator instruction rate (inst/s) -host_op_rate 30162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 650140 # Simulator tick rate (ticks/s) -host_mem_usage 172408 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 38153 # Simulator instruction rate (inst/s) +host_op_rate 38149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 822314 # Simulator tick rate (ticks/s) +host_mem_usage 127760 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2982 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.088981 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 328 21.97% 21.97% | 1088 72.87% 94.84% | 74 4.96% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1493 system.ruby.Directory.incomplete_times 1492 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses @@ -99,6 +103,7 @@ system.ruby.network.msg_byte.Control 35832 system.ruby.network.msg_byte.Data 321624 system.ruby.network.msg_byte.Response_Data 322488 system.ruby.network.msg_byte.Writeback_Control 35736 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index aa6f1a156..943508ee9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,19 +140,25 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 +system=system [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -149,6 +167,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -157,6 +176,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -171,12 +191,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -186,6 +209,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -195,7 +219,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -209,11 +234,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -226,6 +253,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -235,5 +263,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index f65ffe2d1..fe019aadb 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:20 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:53:01 +gem5 started Jan 22 2014 17:28:24 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d3256ea4d..bed740225 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304637 # Simulator instruction rate (inst/s) -host_op_rate 304230 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1653175117 # Simulator tick rate (ticks/s) -host_mem_usage 224940 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 65946 # Simulator instruction rate (inst/s) +host_op_rate 65935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 358688094 # Simulator tick rate (ticks/s) +host_mem_usage 230484 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 28096 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 439000 # La system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -92,6 +95,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.141602 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11935 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11935 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -172,6 +181,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011841 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3967 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3967 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -295,6 +310,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4314 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4314 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 3e13ce8e1..31323532b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -65,6 +69,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -129,6 +135,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -144,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -152,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -166,26 +175,32 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=PowerTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -194,16 +209,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -212,22 +230,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -236,22 +258,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -260,10 +286,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -272,124 +300,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -398,10 +447,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -410,16 +461,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -428,10 +482,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -442,6 +498,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -450,6 +507,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -464,17 +522,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=PowerInterrupts +eventq_index=0 [system.cpu.isa] type=PowerISA +eventq_index=0 [system.cpu.itb] type=PowerTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -483,6 +546,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -491,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -505,12 +570,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -520,6 +588,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -529,7 +598,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -543,11 +613,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -567,6 +639,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -578,17 +651,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 92c45258c..bf0b02582 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:29:56 -gem5 started Oct 16 2013 01:35:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:58:44 +gem5 started Jan 22 2014 17:29:11 +gem5 executing on u200540-lin command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18469500 because target called exit() +Exiting @ tick 18905500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 800440e86..66a92381f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000019 # Nu sim_ticks 18905500 # Number of ticks simulated final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83485 # Simulator instruction rate (inst/s) -host_op_rate 83467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272386071 # Simulator tick rate (ticks/s) -host_mem_usage 250488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44009 # Simulator instruction rate (inst/s) +host_op_rate 44004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143620144 # Simulator tick rate (ticks/s) +host_mem_usage 227496 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -215,6 +217,7 @@ system.membus.reqLayer0.occupancy 566000 # La system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -526,6 +529,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3979 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3979 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -612,6 +621,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -738,6 +753,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index 0bfe98e66..ab39b14ed 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -46,6 +50,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,20 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=PowerTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=PowerInterrupts +eventq_index=0 [system.cpu.isa] type=PowerISA +eventq_index=0 [system.cpu.itb] type=PowerTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -98,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -112,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -129,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -138,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index df127b542..b419f1ee5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout -Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:59:47 -gem5 started Sep 22 2013 05:59:59 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:58:44 +gem5 started Jan 22 2014 17:29:13 +gem5 executing on u200540-lin command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 759fbed05..a91187fc2 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671850 # Simulator instruction rate (inst/s) -host_op_rate 669870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 333940022 # Simulator tick rate (ticks/s) -host_mem_usage 212612 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 80864 # Simulator instruction rate (inst/s) +host_op_rate 80849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40410591 # Simulator tick rate (ticks/s) +host_mem_usage 216708 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory system.physmem.bytes_read::total 26892 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 10739295580 # To system.membus.throughput 10739295580 # Throughput (bytes/s) system.membus.data_through_bus 31101 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 803d2e67f..74f6fdcd8 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -113,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -127,11 +135,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -148,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -162,17 +175,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -181,6 +199,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -189,6 +208,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -203,12 +223,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +241,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +251,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -241,11 +266,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +292,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +304,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 5555171c3..bce99f509 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:26 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:22 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 20802500 because target called exit() +Hello World!Exiting @ tick 20892500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index b34a38ab7..005c21949 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000021 # Nu sim_ticks 20892500 # Number of ticks simulated final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70791 # Simulator instruction rate (inst/s) -host_op_rate 70777 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 277537926 # Simulator tick rate (ticks/s) -host_mem_usage 260788 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 24019 # Simulator instruction rate (inst/s) +host_op_rate 24017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94189663 # Simulator tick rate (ticks/s) +host_mem_usage 236900 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 27072 # Number of bytes read from this memory @@ -213,6 +215,7 @@ system.membus.reqLayer0.occupancy 502000 # La system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 18.8 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -292,6 +295,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2807 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -397,6 +406,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -523,6 +538,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 5f0f231f3..ea4a95481 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 3faafe3e1..c85cb4f07 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:09:49 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:22 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index b27d1e6f6..a26cb7265 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 565055 # Simulator instruction rate (inst/s) -host_op_rate 563581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 284338324 # Simulator tick rate (ticks/s) -host_mem_usage 222908 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 53422 # Simulator instruction rate (inst/s) +host_op_rate 53415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27014162 # Simulator tick rate (ticks/s) +host_mem_usage 227132 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory system.physmem.bytes_read::total 26082 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 11559473001 # To system.membus.throughput 11559473001 # Throughput (bytes/s) system.membus.data_through_bus 31147 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 0e46b888b..cb65490fc 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -68,24 +73,30 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -95,7 +106,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,6 +123,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -119,18 +132,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -138,9 +155,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -151,6 +169,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -167,6 +186,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -186,7 +206,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -202,6 +223,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -217,6 +239,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -232,6 +255,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -241,6 +265,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -251,6 +276,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -260,6 +286,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -269,6 +296,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -278,6 +306,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -287,32 +316,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -324,5 +350,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index fe6ceebff..a7fbcbb0c 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:00 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:33 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index d8d5f48fa..ff67fbecb 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 352 # Simulator instruction rate (inst/s) -host_op_rate 352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7141 # Simulator tick rate (ticks/s) -host_mem_usage 177732 # Number of bytes of host memory used -host_seconds 15.12 # Real time elapsed on the host +host_inst_rate 32230 # Simulator instruction rate (inst/s) +host_op_rate 32227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 653032 # Simulator tick rate (ticks/s) +host_mem_usage 134144 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2574 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.536157 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses @@ -99,6 +103,7 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 +system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 107952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 794c187b4..32f16be8d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +216,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index c2df02496..73a8d6161 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:31 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:24 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index b76f909df..b7dc82e89 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 441877 # Simulator instruction rate (inst/s) -host_op_rate 441389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2300957264 # Simulator tick rate (ticks/s) -host_mem_usage 230904 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 44522 # Simulator instruction rate (inst/s) +host_op_rate 44517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232295322 # Simulator tick rate (ticks/s) +host_mem_usage 236896 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 24896 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 389000 # La system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 55600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -74,6 +77,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10999 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -154,6 +163,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -280,6 +295,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 12dff19e9..b8e6ab850 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -156,6 +165,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -170,18 +180,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +204,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +224,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +245,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +273,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +301,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +315,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +462,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +476,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +497,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +513,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -477,12 +537,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +556,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +579,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -521,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -535,12 +603,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +621,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,7 +631,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -573,11 +646,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +672,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +684,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 6fd808106..7bb858e94 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:54:57 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:29:56 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 19639500 because target called exit() +Exiting @ tick 19970500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b42a03bbb..d0b8bca45 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000020 # Nu sim_ticks 19970500 # Number of ticks simulated final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37809 # Simulator instruction rate (inst/s) -host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140319695 # Simulator tick rate (ticks/s) -host_mem_usage 243588 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 4162 # Simulator instruction rate (inst/s) +host_op_rate 7540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15448311 # Simulator tick rate (ticks/s) +host_mem_usage 248568 # Number of bytes of host memory used +host_seconds 1.29 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory system.physmem.bytes_read::total 26496 # Number of bytes read from this memory @@ -212,6 +214,7 @@ system.membus.reqLayer0.occupancy 500500 # La system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 3084 # Number of BP lookups system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect @@ -221,6 +224,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -509,6 +513,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4234 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits @@ -595,6 +605,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 32.750233 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -721,6 +737,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 83.239431 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020322 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020322 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 6906721ce..eb1883caa 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 551fc8a46..6330d042a 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:45:55 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:30:08 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 34f6daec3..f285016ae 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57992 # Simulator instruction rate (inst/s) -host_op_rate 105036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60491180 # Simulator tick rate (ticks/s) -host_mem_usage 236648 # Number of bytes of host memory used +host_inst_rate 57117 # Simulator instruction rate (inst/s) +host_op_rate 103440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59566456 # Simulator tick rate (ticks/s) +host_mem_usage 237684 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory system.physmem.bytes_read::total 61978 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 12304541407 # To system.membus.throughput 12304541407 # Throughput (bytes/s) system.membus.data_through_bus 69090 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11231 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 3bbe64bb8..d7786b69e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,21 +74,25 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu.clk_domain +eventq_index=0 [system.cpu.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu.clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl0.sequencer.slave[3] @@ -91,6 +100,7 @@ port=system.ruby.l1_cntrl0.sequencer.slave[3] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1 pio_addr=2305843009213693952 pio_latency=100 @@ -101,22 +111,26 @@ pio=system.ruby.l1_cntrl0.sequencer.master[0] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu.clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl0.sequencer.slave[2] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -126,7 +140,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -142,6 +157,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -150,18 +166,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -169,9 +189,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -182,6 +203,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -198,6 +220,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -217,7 +240,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -233,6 +257,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -248,6 +273,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -264,6 +290,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port s type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -273,6 +300,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -283,6 +311,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -292,6 +321,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -301,6 +331,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -310,6 +341,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -319,32 +351,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -356,5 +385,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index bbc0c797e..86244d4bf 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -3,4 +3,3 @@ warn: rounding error > tolerance warn: rounding error > tolerance 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 78a38ee4d..53e9ad058 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:54:46 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:30:11 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 1b1365419..9b8cf8013 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,13 +4,16 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 9034 # Simulator instruction rate (inst/s) -host_op_rate 16364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204397 # Simulator tick rate (ticks/s) -host_mem_usage 189696 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host +host_inst_rate 33614 # Simulator instruction rate (inst/s) +host_op_rate 60888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 760469 # Simulator tick rate (ticks/s) +host_mem_usage 144688 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2750 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.315805 system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses @@ -99,6 +103,8 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 121759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 2a7188a36..b6193f8c7 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +eventq_index=0 +executable=/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index c59dbb17e..bb364e541 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:41:56 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:30:10 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index ff37d4bfb..017ee7525 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41834 # Simulator instruction rate (inst/s) -host_op_rate 75775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 220409714 # Simulator tick rate (ticks/s) -host_mem_usage 245252 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 44998 # Simulator instruction rate (inst/s) +host_op_rate 81497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237030591 # Simulator tick rate (ticks/s) +host_mem_usage 247544 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -44,6 +46,8 @@ system.membus.reqLayer0.occupancy 361000 # La system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 56716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,6 +82,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13958 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -158,6 +168,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -281,6 +297,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 708085ca5..39d7de978 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,10 +533,12 @@ eventq_index=0 [system.cpu.isa0] type=AlphaISA eventq_index=0 +system=system [system.cpu.isa1] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -554,6 +560,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -570,6 +577,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -596,7 +604,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -616,7 +624,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index d74926aee..262de0632 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:31 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 24404000 because target called exit() +Exiting @ tick 24229500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index b48213381..941a3afbf 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000024 # Nu sim_ticks 24229500 # Number of ticks simulated final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38113 # Simulator instruction rate (inst/s) -host_op_rate 38111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72448291 # Simulator tick rate (ticks/s) -host_mem_usage 273720 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 46987 # Simulator instruction rate (inst/s) +host_op_rate 46985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89318295 # Simulator tick rate (ticks/s) +host_mem_usage 231368 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory system.physmem.bytes_read::total 62400 # Number of bytes read from this memory @@ -218,6 +220,7 @@ system.membus.reqLayer0.occupancy 1237000 # La system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 37.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 6676 # Number of BP lookups system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect @@ -656,6 +659,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11364 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits @@ -744,6 +753,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 829 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025299 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -869,6 +884,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11365 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11365 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 86810fed8..a5a69d897 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -113,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -127,11 +135,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -148,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -162,17 +175,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -181,6 +199,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -189,6 +208,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -203,12 +223,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +241,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +251,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +eventq_index=0 +executable=/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -241,11 +266,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +292,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +304,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 947073917..8b0aca80b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:11:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:33 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 27282000 because target called exit() +Exiting @ tick 27705000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 9f174a09c..4c8817e23 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000028 # Nu sim_ticks 27705000 # Number of ticks simulated final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72386 # Simulator instruction rate (inst/s) -host_op_rate 72381 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132251643 # Simulator tick rate (ticks/s) -host_mem_usage 260736 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 23200 # Simulator instruction rate (inst/s) +host_op_rate 23199 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42390050 # Simulator tick rate (ticks/s) +host_mem_usage 236824 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 27904 # Number of bytes read from this memory @@ -215,6 +217,7 @@ system.membus.reqLayer0.occupancy 519000 # La system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -294,6 +297,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.145996 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 7069 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7069 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -399,6 +408,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3947 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3947 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -522,6 +537,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index e50ecc67e..48563010b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -151,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -165,26 +174,32 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +208,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +229,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +257,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +285,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +299,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +446,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +460,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +481,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +497,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -449,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -463,17 +521,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -482,6 +545,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -490,6 +554,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -504,12 +569,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +587,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +597,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +eventq_index=0 +executable=/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -542,11 +612,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +638,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +650,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 3384dd19c..9f4e08c11 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:31:26 -gem5 started Oct 16 2013 01:35:23 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:34 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 26524500 because target called exit() +Exiting @ tick 26616500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index dcf709c59..7bcabaaf6 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000027 # Nu sim_ticks 26616500 # Number of ticks simulated final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75478 # Simulator instruction rate (inst/s) -host_op_rate 75473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139143595 # Simulator tick rate (ticks/s) -host_mem_usage 260732 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 19079 # Simulator instruction rate (inst/s) +host_op_rate 19079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35176168 # Simulator tick rate (ticks/s) +host_mem_usage 237844 # Number of bytes of host memory used +host_seconds 0.76 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory system.physmem.bytes_read::total 30848 # Number of bytes read from this memory @@ -215,6 +217,7 @@ system.membus.reqLayer0.occupancy 610000 # La system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 6713 # Number of BP lookups system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect @@ -506,6 +509,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11095 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits @@ -592,6 +601,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4354 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4354 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -715,6 +730,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 9219 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9219 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 72cf29eda..4f177ecd0 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +eventq_index=0 +executable=/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index 24f0721ea..13e87da70 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:11:45 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:44 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 082962efb..9bfbb56dc 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 451796 # Simulator instruction rate (inst/s) -host_op_rate 451441 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 226479305 # Simulator tick rate (ticks/s) -host_mem_usage 222832 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 25833 # Simulator instruction rate (inst/s) +host_op_rate 25832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12968653 # Simulator tick rate (ticks/s) +host_mem_usage 227056 # Number of bytes of host memory used +host_seconds 0.59 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory system.physmem.bytes_read::total 72170 # Number of bytes read from this memory @@ -38,6 +40,7 @@ system.physmem.bw_total::total 10668943773 # To system.membus.throughput 10676563321 # Throughput (bytes/s) system.membus.data_through_bus 81270 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15225 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 77bbda99d..f1f91f6d4 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +216,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +eventq_index=0 +executable=/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index de66adf5c..543b5de56 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:35 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:44 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 45bd7d946..6f76b1103 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 554996 # Simulator instruction rate (inst/s) -host_op_rate 554737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1512828488 # Simulator tick rate (ticks/s) -host_mem_usage 230824 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 30355 # Simulator instruction rate (inst/s) +host_op_rate 30353 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82811452 # Simulator tick rate (ticks/s) +host_mem_usage 236788 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 416000 # La system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 82736 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -74,6 +77,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30696 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -154,6 +163,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -277,6 +292,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index de3e77970..1b54fd806 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -548,7 +552,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -679,6 +683,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -695,6 +700,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -1024,6 +1030,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -1040,6 +1047,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -1179,6 +1187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.dcache.tags @@ -1195,6 +1204,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.dtb] @@ -1524,6 +1534,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.icache.tags @@ -1540,6 +1551,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.interrupts] @@ -1679,6 +1691,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.dcache.tags @@ -1695,6 +1708,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.dtb] @@ -2024,6 +2038,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.icache.tags @@ -2040,6 +2055,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.interrupts] @@ -2080,6 +2096,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -2096,6 +2113,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 0b0b9c7cf..26a87e082 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,26 +1,26 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:31:26 -gem5 started Oct 16 2013 01:35:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:46 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 Iteration 2 completed [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 @@ -29,47 +29,47 @@ Iteration 2 completed [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 Iteration 5 completed +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed [Iteration 10, Thread 3] Got lock [Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 @@ -79,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 110804500 because target called exit() +Exiting @ tick 111025500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 34d426284..db4434e5e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000111 # Nu sim_ticks 111025500 # Number of ticks simulated final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77886 # Simulator instruction rate (inst/s) -host_op_rate 77886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8289137 # Simulator tick rate (ticks/s) -host_mem_usage 295244 # Number of bytes of host memory used -host_seconds 13.39 # Real time elapsed on the host +host_inst_rate 93081 # Simulator instruction rate (inst/s) +host_op_rate 93081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9906240 # Simulator tick rate (ticks/s) +host_mem_usage 253180 # Number of bytes of host memory used +host_seconds 11.21 # Real time elapsed on the host sim_insts 1043212 # Number of instructions simulated sim_ops 1043212 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -246,6 +248,7 @@ system.membus.reqLayer0.occupancy 932000 # La system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. @@ -271,6 +274,13 @@ system.l2c.tags.occ_percent::cpu2.data 0.000083 # Av system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 182 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18228 # Number of tag accesses +system.l2c.tags.data_accesses 18228 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits @@ -970,6 +980,13 @@ system.cpu0.icache.tags.warmup_cycle 0 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 6456 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 6456 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits @@ -1054,6 +1071,13 @@ system.cpu0.dcache.tags.warmup_cycle 0 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 627950 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 627950 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits @@ -1447,6 +1471,12 @@ system.cpu1.icache.tags.warmup_cycle 0 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 23807 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 23807 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits @@ -1531,6 +1561,12 @@ system.cpu1.dcache.tags.warmup_cycle 0 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 290684 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 290684 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits @@ -1921,6 +1957,12 @@ system.cpu2.icache.tags.warmup_cycle 0 # Cy system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 20176 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 20176 # Number of data accesses system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits @@ -2005,6 +2047,11 @@ system.cpu2.dcache.tags.warmup_cycle 0 # Cy system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 328789 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 328789 # Number of data accesses system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits @@ -2396,6 +2443,12 @@ system.cpu3.icache.tags.warmup_cycle 0 # Cy system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 20994 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 20994 # Number of data accesses system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits @@ -2480,6 +2533,11 @@ system.cpu3.dcache.tags.warmup_cycle 0 # Cy system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 335202 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 335202 # Number of data accesses system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index aa7fc3405..aa003cad3 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -78,6 +83,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -86,6 +92,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -100,11 +107,14 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -113,6 +123,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -121,6 +132,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -135,21 +147,27 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu0.isa] type=SparcISA +eventq_index=0 [system.cpu0.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu0.workload] type=LiveProcess @@ -159,7 +177,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +eventq_index=0 +executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -180,6 +199,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -213,6 +233,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -221,6 +242,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -235,11 +257,14 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -248,6 +273,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,6 +282,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -270,21 +297,27 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu1.isa] type=SparcISA +eventq_index=0 [system.cpu1.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=AtomicSimpleCPU @@ -296,6 +329,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -329,6 +363,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -337,6 +372,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.dcache.tags @@ -351,11 +387,14 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.icache] @@ -364,6 +403,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -372,6 +412,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.icache.tags @@ -386,21 +427,27 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu2.isa] type=SparcISA +eventq_index=0 [system.cpu2.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu3] type=AtomicSimpleCPU @@ -412,6 +459,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -445,6 +493,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -453,6 +502,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.dcache.tags @@ -467,11 +517,14 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.icache] @@ -480,6 +533,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -488,6 +542,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.icache.tags @@ -502,25 +557,32 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu3.isa] type=SparcISA +eventq_index=0 [system.cpu3.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.l2c] @@ -529,6 +591,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -537,6 +600,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -551,12 +615,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -569,6 +636,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -579,6 +647,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -588,5 +657,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index a3bbfbbb8..79edf9761 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:09:34 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 8179c99d9..6a51ab3a8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170274 # Simulator instruction rate (inst/s) -host_op_rate 170274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22048637 # Simulator tick rate (ticks/s) -host_mem_usage 246052 # Number of bytes of host memory used -host_seconds 3.98 # Real time elapsed on the host +host_inst_rate 84570 # Simulator instruction rate (inst/s) +host_op_rate 84570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10950892 # Simulator tick rate (ticks/s) +host_mem_usage 249088 # Number of bytes of host memory used +host_seconds 8.01 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory @@ -60,6 +62,7 @@ system.physmem.bw_total::total 407903588 # To system.membus.throughput 407903588 # Throughput (bytes/s) system.membus.data_through_bus 35776 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. @@ -85,6 +88,12 @@ system.l2c.tags.occ_percent::cpu2.data 0.000014 # Av system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 15488 # Number of tag accesses +system.l2c.tags.data_accesses 15488 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits @@ -273,6 +282,12 @@ system.cpu0.icache.tags.warmup_cycle 0 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -315,6 +330,12 @@ system.cpu0.dcache.tags.warmup_cycle 0 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -397,6 +418,12 @@ system.cpu1.icache.tags.warmup_cycle 0 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -439,6 +466,11 @@ system.cpu1.dcache.tags.warmup_cycle 0 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -519,6 +551,12 @@ system.cpu2.icache.tags.warmup_cycle 0 # Cy system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -561,6 +599,11 @@ system.cpu2.dcache.tags.warmup_cycle 0 # Cy system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -641,6 +684,12 @@ system.cpu3.icache.tags.warmup_cycle 0 # Cy system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -683,6 +732,12 @@ system.cpu3.dcache.tags.warmup_cycle 0 # Cy system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index fc54ba8f2..f42d1a52f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -85,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -101,6 +102,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -123,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -139,6 +142,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -167,7 +171,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -224,6 +228,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -240,6 +245,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -262,6 +268,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -278,6 +285,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -343,6 +351,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.dcache.tags @@ -359,6 +368,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.dtb] @@ -381,6 +391,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.icache.tags @@ -397,6 +408,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2.interrupts] @@ -462,6 +474,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.dcache.tags @@ -478,6 +491,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.dtb] @@ -500,6 +514,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.icache.tags @@ -516,6 +531,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3.interrupts] @@ -556,6 +572,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -572,6 +589,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 7a29b18d1..f70079816 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:12 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 17:29:55 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 8d5cb3498..bea653a5a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200508 # Simulator instruction rate (inst/s) -host_op_rate 200507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79406810 # Simulator tick rate (ticks/s) -host_mem_usage 291148 # Number of bytes of host memory used -host_seconds 3.31 # Real time elapsed on the host +host_inst_rate 87015 # Simulator instruction rate (inst/s) +host_op_rate 87015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34460789 # Simulator tick rate (ticks/s) +host_mem_usage 249056 # Number of bytes of host memory used +host_seconds 7.63 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -74,6 +76,7 @@ system.membus.reqLayer0.occupancy 852296 # La system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. @@ -99,6 +102,12 @@ system.l2c.tags.occ_percent::cpu2.data 0.000013 # Av system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 15709 # Number of tag accesses +system.l2c.tags.data_accesses 15709 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits @@ -560,6 +569,12 @@ system.cpu0.icache.tags.warmup_cycle 0 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -638,6 +653,12 @@ system.cpu0.dcache.tags.warmup_cycle 0 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -780,6 +801,13 @@ system.cpu1.icache.tags.warmup_cycle 0 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits @@ -858,6 +886,12 @@ system.cpu1.dcache.tags.warmup_cycle 0 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits @@ -998,6 +1032,13 @@ system.cpu2.icache.tags.warmup_cycle 0 # Cy system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits @@ -1076,6 +1117,12 @@ system.cpu2.dcache.tags.warmup_cycle 0 # Cy system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits @@ -1216,6 +1263,13 @@ system.cpu3.icache.tags.warmup_cycle 0 # Cy system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits @@ -1294,6 +1348,12 @@ system.cpu3.dcache.tags.warmup_cycle 0 # Cy system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr index d0c477d0e..6c3b6657b 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr @@ -79,4 +79,3 @@ system.cpu4: completed 90000 read, 48685 write accesses @6602186 system.cpu5: completed 90000 read, 48384 write accesses @6637212 system.cpu3: completed 90000 read, 48869 write accesses @6654178 system.cpu6: completed 100000 read, 53414 write accesses @7257449 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout index 53312cb70..d0305734f 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:27:02 -gem5 started Sep 22 2013 05:27:23 -gem5 executing on zizzer -command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory +gem5 compiled Jan 22 2014 16:37:52 +gem5 started Jan 22 2014 17:26:10 +gem5 executing on u200540-lin +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 7257449 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 173706474..6ebaf5618 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.007257 # Nu sim_ticks 7257449 # Number of ticks simulated final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 68193 # Simulator tick rate (ticks/s) -host_mem_usage 302480 # Number of bytes of host memory used -host_seconds 106.43 # Real time elapsed on the host +host_tick_rate 104409 # Simulator tick rate (ticks/s) +host_mem_usage 258924 # Number of bytes of host memory used +host_seconds 69.51 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 128 # delay histogram for all message system.ruby.delayHist::max_bucket 1279 # delay histogram for all message system.ruby.delayHist::samples 4856797 # delay histogram for all message @@ -322,6 +325,7 @@ system.ruby.network.routers08.msg_bytes.Response_Control::2 4842768 system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8120304 system.ruby.network.routers08.msg_bytes.Writeback_Data::1 28664064 system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1656240 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 817953 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 604997 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 212953 # Number of memory writes @@ -377,6 +381,7 @@ system.ruby.network.msg_byte.Writeback_Data 110353176 system.ruby.network.msg_byte.Writeback_Control 4968736 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) +system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99060 # number of read accesses completed system.cpu0.num_writes 53442 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index ba91b18e2..53be052ed 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,12 +14,13 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcb boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:268435455 -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= @@ -33,12 +36,14 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -58,6 +63,7 @@ test=system.ruby.l1_cntrl0.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -77,6 +83,7 @@ test=system.ruby.l1_cntrl1.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -96,6 +103,7 @@ test=system.ruby.l1_cntrl2.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -115,6 +123,7 @@ test=system.ruby.l1_cntrl3.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -134,6 +143,7 @@ test=system.ruby.l1_cntrl4.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -153,6 +163,7 @@ test=system.ruby.l1_cntrl5.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -172,6 +183,7 @@ test=system.ruby.l1_cntrl6.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -190,11 +202,13 @@ test=system.ruby.l1_cntrl7.sequencer.slave[0] [system.cpu_clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.funcbus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -206,6 +220,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=false latency=30 latency_var=0 @@ -218,6 +233,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -226,18 +242,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=8 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -245,9 +265,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=9 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=6 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -258,6 +279,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -274,6 +296,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -293,7 +316,8 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -311,6 +335,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -325,6 +350,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -340,6 +366,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -358,7 +385,8 @@ L1Dcache=system.ruby.l1_cntrl1.L1Dcache L1Icache=system.ruby.l1_cntrl1.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -376,6 +404,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -390,6 +419,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -405,6 +435,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl1.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -423,7 +454,8 @@ L1Dcache=system.ruby.l1_cntrl2.L1Dcache L1Icache=system.ruby.l1_cntrl2.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -441,6 +473,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -455,6 +488,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -470,6 +504,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl2.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -488,7 +523,8 @@ L1Dcache=system.ruby.l1_cntrl3.L1Dcache L1Icache=system.ruby.l1_cntrl3.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=3 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -506,6 +542,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -520,6 +557,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -535,6 +573,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl3.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -553,7 +592,8 @@ L1Dcache=system.ruby.l1_cntrl4.L1Dcache L1Icache=system.ruby.l1_cntrl4.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=4 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -571,6 +611,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -585,6 +626,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -600,6 +642,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl4.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -618,7 +661,8 @@ L1Dcache=system.ruby.l1_cntrl5.L1Dcache L1Icache=system.ruby.l1_cntrl5.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=5 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -636,6 +680,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -650,6 +695,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -665,6 +711,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl5.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -683,7 +730,8 @@ L1Dcache=system.ruby.l1_cntrl6.L1Dcache L1Icache=system.ruby.l1_cntrl6.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=6 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -701,6 +749,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -715,6 +764,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -730,6 +780,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl6.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -748,7 +799,8 @@ L1Dcache=system.ruby.l1_cntrl7.L1Dcache L1Icache=system.ruby.l1_cntrl7.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=7 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -766,6 +818,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -780,6 +833,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -795,6 +849,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl7.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -812,7 +867,8 @@ children=L2cache L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=8 +cluster_id=0 +eventq_index=0 number_of_TBEs=256 peer=Null recycle_latency=10 @@ -827,6 +883,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=15 replacement_policy=PSEUDO_LRU @@ -840,6 +897,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -849,6 +907,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9 number_of_virtual_networks=10 @@ -859,6 +918,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers00 latency=1 @@ -868,6 +928,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl1 int_node=system.ruby.network.routers01 latency=1 @@ -877,6 +938,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl2 int_node=system.ruby.network.routers02 latency=1 @@ -886,6 +948,7 @@ weight=1 [system.ruby.network.ext_links3] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl3 int_node=system.ruby.network.routers03 latency=1 @@ -895,6 +958,7 @@ weight=1 [system.ruby.network.ext_links4] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl4 int_node=system.ruby.network.routers04 latency=1 @@ -904,6 +968,7 @@ weight=1 [system.ruby.network.ext_links5] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl5 int_node=system.ruby.network.routers05 latency=1 @@ -913,6 +978,7 @@ weight=1 [system.ruby.network.ext_links6] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl6 int_node=system.ruby.network.routers06 latency=1 @@ -922,6 +988,7 @@ weight=1 [system.ruby.network.ext_links7] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl7 int_node=system.ruby.network.routers07 latency=1 @@ -931,6 +998,7 @@ weight=1 [system.ruby.network.ext_links8] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers08 latency=1 @@ -940,6 +1008,7 @@ weight=1 [system.ruby.network.ext_links9] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers09 latency=1 @@ -949,6 +1018,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=10 node_a=system.ruby.network.routers00 @@ -958,6 +1028,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=11 node_a=system.ruby.network.routers01 @@ -967,6 +1038,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=12 node_a=system.ruby.network.routers02 @@ -976,6 +1048,7 @@ weight=1 [system.ruby.network.int_links3] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=13 node_a=system.ruby.network.routers03 @@ -985,6 +1058,7 @@ weight=1 [system.ruby.network.int_links4] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=14 node_a=system.ruby.network.routers04 @@ -994,6 +1068,7 @@ weight=1 [system.ruby.network.int_links5] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=15 node_a=system.ruby.network.routers05 @@ -1003,6 +1078,7 @@ weight=1 [system.ruby.network.int_links6] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=16 node_a=system.ruby.network.routers06 @@ -1012,6 +1088,7 @@ weight=1 [system.ruby.network.int_links7] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=17 node_a=system.ruby.network.routers07 @@ -1021,6 +1098,7 @@ weight=1 [system.ruby.network.int_links8] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=18 node_a=system.ruby.network.routers08 @@ -1030,6 +1108,7 @@ weight=1 [system.ruby.network.int_links9] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=19 node_a=system.ruby.network.routers09 @@ -1039,80 +1118,85 @@ weight=1 [system.ruby.network.routers00] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers01] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers02] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers03] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 [system.ruby.network.routers04] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=4 virt_nets=10 [system.ruby.network.routers05] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=5 virt_nets=10 [system.ruby.network.routers06] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=6 virt_nets=10 [system.ruby.network.routers07] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=7 virt_nets=10 [system.ruby.network.routers08] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=8 virt_nets=10 [system.ruby.network.routers09] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=9 virt_nets=10 [system.ruby.network.routers10] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=10 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=8 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -1124,5 +1208,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr index d888f2c0a..96061ea38 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr @@ -79,4 +79,3 @@ system.cpu3: completed 90000 read, 49090 write accesses @6783540 system.cpu7: completed 90000 read, 48766 write accesses @6785808 system.cpu2: completed 90000 read, 49113 write accesses @6821790 system.cpu6: completed 100000 read, 54332 write accesses @7481441 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 802dd1a62..45c67b8ac 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:36:12 -gem5 started Sep 22 2013 05:36:22 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:42:56 +gem5 started Jan 22 2014 17:26:44 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index a1c353735..9ceb39be3 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.007481 # Nu sim_ticks 7481441 # Number of ticks simulated final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 40706 # Simulator tick rate (ticks/s) -host_mem_usage 305724 # Number of bytes of host memory used -host_seconds 183.79 # Real time elapsed on the host +host_tick_rate 57492 # Simulator tick rate (ticks/s) +host_mem_usage 261156 # Number of bytes of host memory used +host_seconds 130.13 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 619788 @@ -280,6 +283,7 @@ system.ruby.network.routers08.msg_bytes.Writeback_Control::2 3115216 system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 67368 system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 152 system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9858144 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 820394 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 605143 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 215243 # Number of memory writes @@ -359,6 +363,7 @@ system.ruby.network.msg_byte.Invalidate_Control 456 system.ruby.network.msg_byte.Unblock_Control 29574432 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) +system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99553 # number of read accesses completed system.cpu0.num_writes 54274 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index a202baa14..4e078b123 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcb boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,12 +36,14 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -58,6 +63,7 @@ test=system.ruby.l1_cntrl0.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -77,6 +83,7 @@ test=system.ruby.l1_cntrl1.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -96,6 +103,7 @@ test=system.ruby.l1_cntrl2.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -115,6 +123,7 @@ test=system.ruby.l1_cntrl3.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -134,6 +143,7 @@ test=system.ruby.l1_cntrl4.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -153,6 +163,7 @@ test=system.ruby.l1_cntrl5.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -172,6 +183,7 @@ test=system.ruby.l1_cntrl6.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -190,11 +202,13 @@ test=system.ruby.l1_cntrl7.sequencer.slave[0] [system.cpu_clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.funcbus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -206,6 +220,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=false latency=30 latency_var=0 @@ -218,6 +233,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -226,18 +242,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=8 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -245,10 +265,11 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=9 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true +eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 memBuffer=system.ruby.dir_cntrl0.memBuffer @@ -262,6 +283,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -278,6 +300,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -298,8 +321,9 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -322,6 +346,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -336,6 +361,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -351,6 +377,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -370,8 +397,9 @@ L1Icache=system.ruby.l1_cntrl1.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -394,6 +422,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -408,6 +437,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -423,6 +453,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl1.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -442,8 +473,9 @@ L1Icache=system.ruby.l1_cntrl2.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -466,6 +498,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -480,6 +513,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -495,6 +529,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl2.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -514,8 +549,9 @@ L1Icache=system.ruby.l1_cntrl3.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=3 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -538,6 +574,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -552,6 +589,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -567,6 +605,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl3.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -586,8 +625,9 @@ L1Icache=system.ruby.l1_cntrl4.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=4 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -610,6 +650,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -624,6 +665,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -639,6 +681,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl4.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -658,8 +701,9 @@ L1Icache=system.ruby.l1_cntrl5.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=5 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -682,6 +726,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -696,6 +741,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -711,6 +757,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl5.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -730,8 +777,9 @@ L1Icache=system.ruby.l1_cntrl6.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=6 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -754,6 +802,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -768,6 +817,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -783,6 +833,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl6.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -802,8 +853,9 @@ L1Icache=system.ruby.l1_cntrl7.L1Icache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=7 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -826,6 +878,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -840,6 +893,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -855,6 +909,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl7.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -873,7 +928,8 @@ L2cache=system.ruby.l2_cntrl0.L2cache N_tokens=9 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=8 +cluster_id=0 +eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 @@ -889,6 +945,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -902,6 +959,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -911,6 +969,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9 number_of_virtual_networks=10 @@ -921,6 +980,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers00 latency=1 @@ -930,6 +990,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl1 int_node=system.ruby.network.routers01 latency=1 @@ -939,6 +1000,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl2 int_node=system.ruby.network.routers02 latency=1 @@ -948,6 +1010,7 @@ weight=1 [system.ruby.network.ext_links3] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl3 int_node=system.ruby.network.routers03 latency=1 @@ -957,6 +1020,7 @@ weight=1 [system.ruby.network.ext_links4] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl4 int_node=system.ruby.network.routers04 latency=1 @@ -966,6 +1030,7 @@ weight=1 [system.ruby.network.ext_links5] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl5 int_node=system.ruby.network.routers05 latency=1 @@ -975,6 +1040,7 @@ weight=1 [system.ruby.network.ext_links6] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl6 int_node=system.ruby.network.routers06 latency=1 @@ -984,6 +1050,7 @@ weight=1 [system.ruby.network.ext_links7] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl7 int_node=system.ruby.network.routers07 latency=1 @@ -993,6 +1060,7 @@ weight=1 [system.ruby.network.ext_links8] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers08 latency=1 @@ -1002,6 +1070,7 @@ weight=1 [system.ruby.network.ext_links9] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers09 latency=1 @@ -1011,6 +1080,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=10 node_a=system.ruby.network.routers00 @@ -1020,6 +1090,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=11 node_a=system.ruby.network.routers01 @@ -1029,6 +1100,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=12 node_a=system.ruby.network.routers02 @@ -1038,6 +1110,7 @@ weight=1 [system.ruby.network.int_links3] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=13 node_a=system.ruby.network.routers03 @@ -1047,6 +1120,7 @@ weight=1 [system.ruby.network.int_links4] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=14 node_a=system.ruby.network.routers04 @@ -1056,6 +1130,7 @@ weight=1 [system.ruby.network.int_links5] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=15 node_a=system.ruby.network.routers05 @@ -1065,6 +1140,7 @@ weight=1 [system.ruby.network.int_links6] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=16 node_a=system.ruby.network.routers06 @@ -1074,6 +1150,7 @@ weight=1 [system.ruby.network.int_links7] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=17 node_a=system.ruby.network.routers07 @@ -1083,6 +1160,7 @@ weight=1 [system.ruby.network.int_links8] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=18 node_a=system.ruby.network.routers08 @@ -1092,6 +1170,7 @@ weight=1 [system.ruby.network.int_links9] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=19 node_a=system.ruby.network.routers09 @@ -1101,80 +1180,85 @@ weight=1 [system.ruby.network.routers00] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers01] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers02] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers03] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 [system.ruby.network.routers04] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=4 virt_nets=10 [system.ruby.network.routers05] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=5 virt_nets=10 [system.ruby.network.routers06] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=6 virt_nets=10 [system.ruby.network.routers07] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=7 virt_nets=10 [system.ruby.network.routers08] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=8 virt_nets=10 [system.ruby.network.routers09] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=9 virt_nets=10 [system.ruby.network.routers10] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=10 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=8 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -1186,5 +1270,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index 03befb105..78259ab68 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -79,4 +79,3 @@ system.cpu7: completed 90000 read, 48273 write accesses @5561660 system.cpu4: completed 90000 read, 48720 write accesses @5589754 system.cpu6: completed 90000 read, 49134 write accesses @5592253 system.cpu0: completed 100000 read, 54250 write accesses @6151475 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 9d06307c2..b764ed210 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:44:48 -gem5 started Sep 22 2013 05:44:59 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:47:59 +gem5 started Jan 22 2014 17:27:37 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 83fd02236..7d7ea198b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.006151 # Nu sim_ticks 6151475 # Number of ticks simulated final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 45886 # Simulator tick rate (ticks/s) -host_mem_usage 303616 # Number of bytes of host memory used -host_seconds 134.06 # Real time elapsed on the host +host_tick_rate 74061 # Simulator tick rate (ticks/s) +host_mem_usage 259044 # Number of bytes of host memory used +host_seconds 83.06 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 617095 @@ -245,6 +248,7 @@ system.ruby.network.routers08.msg_bytes.Response_Control::4 11184 system.ruby.network.routers08.msg_bytes.Writeback_Data::4 61234056 system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3020648 system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2077536 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 844944 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 610587 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 234338 # Number of memory writes @@ -318,6 +322,7 @@ system.ruby.network.msg_byte.Broadcast_Control 74018760 system.ruby.network.msg_byte.Persistent_Control 41550720 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) +system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 54250 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 490bbc6b4..bb19b17fd 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,12 +14,13 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcb boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:268435455 -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= @@ -33,12 +36,14 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -58,6 +63,7 @@ test=system.ruby.l1_cntrl0.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -77,6 +83,7 @@ test=system.ruby.l1_cntrl1.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -96,6 +103,7 @@ test=system.ruby.l1_cntrl2.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -115,6 +123,7 @@ test=system.ruby.l1_cntrl3.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -134,6 +143,7 @@ test=system.ruby.l1_cntrl4.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -153,6 +163,7 @@ test=system.ruby.l1_cntrl5.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -172,6 +183,7 @@ test=system.ruby.l1_cntrl6.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -190,11 +202,13 @@ test=system.ruby.l1_cntrl7.sequencer.slave[0] [system.cpu_clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.funcbus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -206,6 +220,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=false latency=30 latency_var=0 @@ -218,6 +233,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -226,18 +242,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=8 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -245,8 +265,9 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=8 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory +eventq_index=0 full_bit_dir_enabled=false memBuffer=system.ruby.dir_cntrl0.memBuffer memory_controller_latency=2 @@ -261,6 +282,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -277,6 +299,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -294,6 +317,7 @@ type=RubyCache assoc=4 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=1 replacement_policy=PSEUDO_LRU @@ -312,7 +336,8 @@ L2cache=system.ruby.l1_cntrl0.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -330,6 +355,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -344,6 +370,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -358,6 +385,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -373,6 +401,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -393,7 +422,8 @@ L2cache=system.ruby.l1_cntrl1.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -411,6 +441,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -425,6 +456,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -439,6 +471,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -454,6 +487,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl1.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -474,7 +508,8 @@ L2cache=system.ruby.l1_cntrl2.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -492,6 +527,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -506,6 +542,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -520,6 +557,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -535,6 +573,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl2.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -555,7 +594,8 @@ L2cache=system.ruby.l1_cntrl3.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=3 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -573,6 +613,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -587,6 +628,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -601,6 +643,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -616,6 +659,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl3.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -636,7 +680,8 @@ L2cache=system.ruby.l1_cntrl4.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=4 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -654,6 +699,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -668,6 +714,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -682,6 +729,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -697,6 +745,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl4.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -717,7 +766,8 @@ L2cache=system.ruby.l1_cntrl5.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=5 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -735,6 +785,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -749,6 +800,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -763,6 +815,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -778,6 +831,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl5.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -798,7 +852,8 @@ L2cache=system.ruby.l1_cntrl6.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=6 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -816,6 +871,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -830,6 +886,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -844,6 +901,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -859,6 +917,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl6.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -879,7 +938,8 @@ L2cache=system.ruby.l1_cntrl7.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=7 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -897,6 +957,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -911,6 +972,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -925,6 +987,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -940,6 +1003,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl7.L1Dcache deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -955,6 +1019,7 @@ slave=system.cpu7.test type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -964,6 +1029,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 number_of_virtual_networks=10 @@ -974,6 +1040,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -983,6 +1050,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl1 int_node=system.ruby.network.routers1 latency=1 @@ -992,6 +1060,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl2 int_node=system.ruby.network.routers2 latency=1 @@ -1001,6 +1070,7 @@ weight=1 [system.ruby.network.ext_links3] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl3 int_node=system.ruby.network.routers3 latency=1 @@ -1010,6 +1080,7 @@ weight=1 [system.ruby.network.ext_links4] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl4 int_node=system.ruby.network.routers4 latency=1 @@ -1019,6 +1090,7 @@ weight=1 [system.ruby.network.ext_links5] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl5 int_node=system.ruby.network.routers5 latency=1 @@ -1028,6 +1100,7 @@ weight=1 [system.ruby.network.ext_links6] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl6 int_node=system.ruby.network.routers6 latency=1 @@ -1037,6 +1110,7 @@ weight=1 [system.ruby.network.ext_links7] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl7 int_node=system.ruby.network.routers7 latency=1 @@ -1046,6 +1120,7 @@ weight=1 [system.ruby.network.ext_links8] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers8 latency=1 @@ -1055,6 +1130,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=9 node_a=system.ruby.network.routers0 @@ -1064,6 +1140,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=10 node_a=system.ruby.network.routers1 @@ -1073,6 +1150,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=11 node_a=system.ruby.network.routers2 @@ -1082,6 +1160,7 @@ weight=1 [system.ruby.network.int_links3] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=12 node_a=system.ruby.network.routers3 @@ -1091,6 +1170,7 @@ weight=1 [system.ruby.network.int_links4] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=13 node_a=system.ruby.network.routers4 @@ -1100,6 +1180,7 @@ weight=1 [system.ruby.network.int_links5] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=14 node_a=system.ruby.network.routers5 @@ -1109,6 +1190,7 @@ weight=1 [system.ruby.network.int_links6] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=15 node_a=system.ruby.network.routers6 @@ -1118,6 +1200,7 @@ weight=1 [system.ruby.network.int_links7] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=16 node_a=system.ruby.network.routers7 @@ -1127,6 +1210,7 @@ weight=1 [system.ruby.network.int_links8] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=17 node_a=system.ruby.network.routers8 @@ -1136,74 +1220,78 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 [system.ruby.network.routers4] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=4 virt_nets=10 [system.ruby.network.routers5] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=5 virt_nets=10 [system.ruby.network.routers6] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=6 virt_nets=10 [system.ruby.network.routers7] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=7 virt_nets=10 [system.ruby.network.routers8] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=8 virt_nets=10 [system.ruby.network.routers9] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=9 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=8 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -1215,5 +1303,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index a5b70c1a7..f2f8ae71c 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -79,4 +79,3 @@ system.cpu0: completed 90000 read, 48602 write accesses @5246963 system.cpu4: completed 90000 read, 48456 write accesses @5248509 system.cpu7: completed 90000 read, 48936 write accesses @5260982 system.cpu2: completed 100000 read, 54294 write accesses @5795833 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 5f6410683..4c8b54d81 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:17:28 -gem5 started Sep 22 2013 05:17:37 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:32:54 +gem5 started Jan 22 2014 17:25:37 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index dccaff688..c7c9aeb58 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.005796 # Nu sim_ticks 5795833 # Number of ticks simulated final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 40133 # Simulator tick rate (ticks/s) -host_mem_usage 303548 # Number of bytes of host memory used -host_seconds 144.41 # Real time elapsed on the host +host_tick_rate 66984 # Simulator tick rate (ticks/s) +host_mem_usage 260008 # Number of bytes of host memory used +host_seconds 86.53 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 618244 @@ -280,6 +283,7 @@ system.ruby.network.routers7.msg_bytes.Writeback_Control::3 578720 system.ruby.network.routers7.msg_bytes.Writeback_Control::5 365344 system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4321008 system.ruby.network.routers7.msg_bytes.Unblock_Control::5 615240 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 811546 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 597507 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 214013 # Number of memory writes @@ -356,6 +360,7 @@ system.ruby.network.msg_byte.Broadcast_Control 74035320 system.ruby.network.msg_byte.Unblock_Control 14822312 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) +system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99395 # number of read accesses completed system.cpu0.num_writes 53721 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index cd6eb6e26..717e12af4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,12 +14,13 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcb boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:268435455 -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= @@ -33,12 +36,14 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -58,6 +63,7 @@ test=system.ruby.l1_cntrl0.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -77,6 +83,7 @@ test=system.ruby.l1_cntrl1.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -96,6 +103,7 @@ test=system.ruby.l1_cntrl2.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -115,6 +123,7 @@ test=system.ruby.l1_cntrl3.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -134,6 +143,7 @@ test=system.ruby.l1_cntrl4.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -153,6 +163,7 @@ test=system.ruby.l1_cntrl5.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -172,6 +183,7 @@ test=system.ruby.l1_cntrl6.sequencer.slave[0] type=MemTest atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -190,11 +202,13 @@ test=system.ruby.l1_cntrl7.sequencer.slave[0] [system.cpu_clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.funcbus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -206,6 +220,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=false latency=30 latency_var=0 @@ -218,6 +233,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -226,18 +242,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=8 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -245,9 +265,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=8 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -258,6 +279,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -274,6 +296,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -293,7 +316,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -309,6 +333,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -324,6 +349,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -342,7 +368,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl1.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -358,6 +385,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -373,6 +401,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl1.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl1.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -391,7 +420,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl2.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -407,6 +437,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -422,6 +453,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl2.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl2.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -440,7 +472,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl3.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=3 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -456,6 +489,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -471,6 +505,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl3.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl3.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -489,7 +524,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl4.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=4 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -505,6 +541,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -520,6 +557,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl4.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl4.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -538,7 +576,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl5.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=5 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -554,6 +593,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -569,6 +609,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl5.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl5.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -587,7 +628,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl6.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=6 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -603,6 +645,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -618,6 +661,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl6.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl6.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -636,7 +680,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl7.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=7 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -652,6 +697,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -667,6 +713,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl7.cacheMemory deadlock_threshold=1000000 +eventq_index=0 icache=system.ruby.l1_cntrl7.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -682,6 +729,7 @@ slave=system.cpu7.test type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -691,6 +739,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 number_of_virtual_networks=10 @@ -701,6 +750,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -710,6 +760,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl1 int_node=system.ruby.network.routers1 latency=1 @@ -719,6 +770,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl2 int_node=system.ruby.network.routers2 latency=1 @@ -728,6 +780,7 @@ weight=1 [system.ruby.network.ext_links3] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl3 int_node=system.ruby.network.routers3 latency=1 @@ -737,6 +790,7 @@ weight=1 [system.ruby.network.ext_links4] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl4 int_node=system.ruby.network.routers4 latency=1 @@ -746,6 +800,7 @@ weight=1 [system.ruby.network.ext_links5] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl5 int_node=system.ruby.network.routers5 latency=1 @@ -755,6 +810,7 @@ weight=1 [system.ruby.network.ext_links6] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl6 int_node=system.ruby.network.routers6 latency=1 @@ -764,6 +820,7 @@ weight=1 [system.ruby.network.ext_links7] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl7 int_node=system.ruby.network.routers7 latency=1 @@ -773,6 +830,7 @@ weight=1 [system.ruby.network.ext_links8] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers8 latency=1 @@ -782,6 +840,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=9 node_a=system.ruby.network.routers0 @@ -791,6 +850,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=10 node_a=system.ruby.network.routers1 @@ -800,6 +860,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=11 node_a=system.ruby.network.routers2 @@ -809,6 +870,7 @@ weight=1 [system.ruby.network.int_links3] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=12 node_a=system.ruby.network.routers3 @@ -818,6 +880,7 @@ weight=1 [system.ruby.network.int_links4] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=13 node_a=system.ruby.network.routers4 @@ -827,6 +890,7 @@ weight=1 [system.ruby.network.int_links5] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=14 node_a=system.ruby.network.routers5 @@ -836,6 +900,7 @@ weight=1 [system.ruby.network.int_links6] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=15 node_a=system.ruby.network.routers6 @@ -845,6 +910,7 @@ weight=1 [system.ruby.network.int_links7] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=16 node_a=system.ruby.network.routers7 @@ -854,6 +920,7 @@ weight=1 [system.ruby.network.int_links8] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=17 node_a=system.ruby.network.routers8 @@ -863,74 +930,78 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 [system.ruby.network.routers4] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=4 virt_nets=10 [system.ruby.network.routers5] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=5 virt_nets=10 [system.ruby.network.routers6] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=6 virt_nets=10 [system.ruby.network.routers7] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=7 virt_nets=10 [system.ruby.network.routers8] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=8 virt_nets=10 [system.ruby.network.routers9] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=9 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=8 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -942,5 +1013,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr index 082530ace..5a7e36bf9 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -79,4 +79,3 @@ system.cpu3: completed 90000 read, 49017 write accesses @7850422 system.cpu5: completed 90000 read, 49075 write accesses @7851926 system.cpu4: completed 90000 read, 49432 write accesses @7874435 system.cpu7: completed 100000 read, 53796 write accesses @8664886 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 1c746b09a..1137a773d 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:49 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:32 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index d75cefcef..ab5af9666 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.008665 # Nu sim_ticks 8664886 # Number of ticks simulated final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 151755 # Simulator tick rate (ticks/s) -host_mem_usage 301056 # Number of bytes of host memory used -host_seconds 57.10 # Real time elapsed on the host +host_tick_rate 261960 # Simulator tick rate (ticks/s) +host_mem_usage 257512 # Number of bytes of host memory used +host_seconds 33.08 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message system.ruby.delayHist::samples 1237687 # delay histogram for all message @@ -136,6 +139,7 @@ system.ruby.network.routers7.msg_bytes.Control::2 618216 system.ruby.network.routers7.msg_bytes.Data::2 5512896 system.ruby.network.routers7.msg_bytes.Response_Data::4 5637312 system.ruby.network.routers7.msg_bytes.Writeback_Control::3 620680 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1218678 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 609346 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 609308 # Number of memory writes @@ -181,6 +185,7 @@ system.ruby.network.msg_byte.Response_Data 133391376 system.ruby.network.msg_byte.Writeback_Control 14883240 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) +system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99885 # number of read accesses completed system.cpu0.num_writes 54375 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini index 0b50bed4c..dd37e6b1e 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,12 +14,13 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcb boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= @@ -33,6 +36,7 @@ system_port=system.membus.slave[1] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -40,6 +44,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -61,6 +66,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -69,6 +75,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.l1c.tags @@ -83,7 +90,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1] @@ -91,6 +100,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -112,6 +122,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -120,6 +131,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.l1c.tags @@ -134,7 +146,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu2] @@ -142,6 +156,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -163,6 +178,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -171,6 +187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu2.l1c.tags @@ -185,7 +202,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu3] @@ -193,6 +212,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -214,6 +234,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -222,6 +243,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu3.l1c.tags @@ -236,7 +258,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu4] @@ -244,6 +268,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -265,6 +290,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -273,6 +299,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu4.l1c.tags @@ -287,7 +314,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu5] @@ -295,6 +324,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -316,6 +346,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -324,6 +355,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu5.l1c.tags @@ -338,7 +370,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu6] @@ -346,6 +380,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -367,6 +402,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -375,6 +411,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu6.l1c.tags @@ -389,7 +426,9 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu7] @@ -397,6 +436,7 @@ type=MemTest children=l1c atomic=false clk_domain=system.cpu_clk_domain +eventq_index=0 issue_dmas=false max_loads=100000 memory_size=65536 @@ -418,6 +458,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -426,6 +467,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu7.l1c.tags @@ -440,17 +482,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.funcbus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -462,6 +508,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=false latency=30000 latency_var=0 @@ -475,6 +522,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -483,6 +531,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=65536 system=system tags=system.l2c.tags @@ -497,12 +546,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=65536 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -515,6 +567,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -525,6 +578,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -534,5 +588,6 @@ slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr index ad8539d90..084f6f6ab 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr @@ -71,4 +71,3 @@ system.cpu2: completed 90000 read, 48395 write accesses @591584000 system.cpu7: completed 90000 read, 48496 write accesses @592485000 system.cpu0: completed 90000 read, 48680 write accesses @594831500 system.cpu3: completed 100000 read, 53536 write accesses @652606500 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout index de32ac2d8..831211e6c 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:53:51 -gem5 started Sep 22 2013 05:53:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:54:17 +gem5 started Jan 22 2014 17:28:45 +gem5 executing on u200540-lin command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 6f84c5ba1..d30a7aa16 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.000653 # Nu sim_ticks 652606500 # Number of ticks simulated final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 158104978 # Simulator tick rate (ticks/s) -host_mem_usage 355504 # Number of bytes of host memory used -host_seconds 4.13 # Real time elapsed on the host +host_tick_rate 148113487 # Simulator tick rate (ticks/s) +host_mem_usage 336812 # Number of bytes of host memory used +host_seconds 4.41 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory @@ -94,6 +96,7 @@ system.membus.reqLayer0.occupancy 286485584 # La system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 47.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 13254 # number of replacements system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. @@ -119,6 +122,12 @@ system.l2c.tags.occ_percent::cpu5 0.006825 # Av system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 811 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 611 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.791992 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1942968 # Number of tag accesses +system.l2c.tags.data_accesses 1942968 # Number of data accesses system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits @@ -740,6 +749,12 @@ system.cpu0.l1c.tags.warmup_cycle 0 # Cy system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 330568 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 330568 # Number of data accesses system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits @@ -855,6 +870,12 @@ system.cpu1.l1c.tags.warmup_cycle 0 # Cy system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 332439 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 332439 # Number of data accesses system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits @@ -970,6 +991,12 @@ system.cpu2.l1c.tags.warmup_cycle 0 # Cy system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 331261 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 331261 # Number of data accesses system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits @@ -1085,6 +1112,12 @@ system.cpu3.l1c.tags.warmup_cycle 0 # Cy system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 331508 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 331508 # Number of data accesses system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits @@ -1200,6 +1233,12 @@ system.cpu4.l1c.tags.warmup_cycle 0 # Cy system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 331555 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 331555 # Number of data accesses system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits @@ -1315,6 +1354,12 @@ system.cpu5.l1c.tags.warmup_cycle 0 # Cy system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 332072 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 332072 # Number of data accesses system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits @@ -1430,6 +1475,12 @@ system.cpu6.l1c.tags.warmup_cycle 0 # Cy system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 332017 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 332017 # Number of data accesses system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits @@ -1545,6 +1596,12 @@ system.cpu7.l1c.tags.warmup_cycle 0 # Cy system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 331300 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 331300 # Number of data accesses system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr index f5d2abbce..2b5c3b11d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr @@ -2,4 +2,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: rounding error > tolerance 0.072760 rounded to 0 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout index 95d13e969..941dddfc7 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:27:02 -gem5 started Sep 22 2013 05:27:12 -gem5 executing on zizzer -command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory +gem5 compiled Jan 22 2014 16:37:52 +gem5 started Jan 22 2014 17:26:11 +gem5 executing on u200540-lin +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 318321 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 07c10314c..c90fc8b43 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.000318 # Nu sim_ticks 318321 # Number of ticks simulated final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1524477 # Simulator tick rate (ticks/s) -host_mem_usage 167184 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 2101304 # Simulator tick rate (ticks/s) +host_mem_usage 123592 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 256 # delay histogram for all message system.ruby.delayHist::max_bucket 2559 # delay histogram for all message system.ruby.delayHist::samples 7069 # delay histogram for all message @@ -102,6 +105,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6864 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 51984 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 36936 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 272 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index 7b4a4a030..683949732 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain physmem ruby sys_port_proxy tester voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.physmem] @@ -40,6 +44,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -48,18 +53,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=true -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -67,9 +76,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=6 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -80,6 +90,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -96,6 +107,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -115,7 +127,8 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 l2_select_num_bits=0 number_of_TBEs=256 peer=Null @@ -133,6 +146,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -147,6 +161,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -162,6 +177,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -179,7 +195,8 @@ children=L2cache L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 number_of_TBEs=256 peer=Null recycle_latency=10 @@ -194,6 +211,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=15 replacement_policy=PSEUDO_LRU @@ -207,6 +225,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -216,6 +235,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -226,6 +246,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -235,6 +256,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -244,6 +266,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -253,6 +276,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -262,6 +286,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -271,6 +296,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -280,38 +306,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -327,6 +351,7 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +eventq_index=0 num_cpus=1 system=system wakeup_frequency=10 @@ -335,5 +360,6 @@ cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr index f5d2abbce..2b5c3b11d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr @@ -2,4 +2,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: rounding error > tolerance 0.072760 rounded to 0 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 2167c1256..b4257bd2c 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:36:12 -gem5 started Sep 22 2013 05:36:22 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:42:56 +gem5 started Jan 22 2014 17:27:15 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 6245a45ed..aefa03a40 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.000327 # Nu sim_ticks 327361 # Number of ticks simulated final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 557303 # Simulator tick rate (ticks/s) -host_mem_usage 169404 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_tick_rate 771883 # Simulator tick rate (ticks/s) +host_mem_usage 124808 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 1000 @@ -84,6 +87,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14448 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 13536 system.ruby.network.routers1.msg_bytes.Writeback_Control::2 640 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14064 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1619 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 854 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 765 # Number of memory writes diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index 7d3b90ce9..323ed5f61 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain physmem ruby sys_port_proxy tester voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.physmem] @@ -40,6 +44,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -48,18 +53,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=true -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -67,10 +76,11 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true +eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 memBuffer=system.ruby.dir_cntrl0.memBuffer @@ -84,6 +94,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -100,6 +111,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -120,8 +132,9 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 dynamic_timeout_enabled=true +eventq_index=0 fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 @@ -144,6 +157,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -158,6 +172,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -173,6 +188,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -191,7 +207,8 @@ L2cache=system.ruby.l2_cntrl0.L2cache N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 +eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 @@ -207,6 +224,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -220,6 +238,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -229,6 +248,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 number_of_virtual_networks=10 @@ -239,6 +259,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -248,6 +269,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -257,6 +279,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -266,6 +289,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers0 @@ -275,6 +299,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=4 node_a=system.ruby.network.routers1 @@ -284,6 +309,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers2 @@ -293,38 +319,36 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -340,6 +364,7 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +eventq_index=0 num_cpus=1 system=system wakeup_frequency=10 @@ -348,5 +373,6 @@ cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr index f5d2abbce..2b5c3b11d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr @@ -2,4 +2,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: rounding error > tolerance 0.072760 rounded to 0 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 733c0eefd..a6637bc84 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:44:48 -gem5 started Sep 22 2013 05:44:59 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:47:59 +gem5 started Jan 22 2014 17:27:41 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 5c157abec..389c45695 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.000225 # Nu sim_ticks 225141 # Number of ticks simulated final_tick 225141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1264878 # Simulator tick rate (ticks/s) -host_mem_usage 168320 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 1830870 # Simulator tick rate (ticks/s) +host_mem_usage 123716 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 1007 @@ -83,6 +86,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 120168 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 576 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 2984 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 1655 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 868 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 787 # Number of memory writes diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 3ff520581..e4c814100 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain physmem ruby sys_port_proxy tester voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.physmem] @@ -40,6 +44,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -48,18 +53,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=true -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -67,8 +76,9 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory +eventq_index=0 full_bit_dir_enabled=false memBuffer=system.ruby.dir_cntrl0.memBuffer memory_controller_latency=2 @@ -83,6 +93,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -99,6 +110,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -116,6 +128,7 @@ type=RubyCache assoc=4 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=1 replacement_policy=PSEUDO_LRU @@ -134,7 +147,8 @@ L2cache=system.ruby.l1_cntrl0.L2cache buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 l2_cache_hit_latency=10 no_mig_atomic=true @@ -152,6 +166,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=2 replacement_policy=PSEUDO_LRU @@ -166,6 +181,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=2 replacement_policy=PSEUDO_LRU @@ -180,6 +196,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=10 replacement_policy=PSEUDO_LRU @@ -195,6 +212,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -210,6 +228,7 @@ slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0] type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -219,6 +238,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -229,6 +249,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -238,6 +259,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -247,6 +269,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -256,6 +279,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -265,32 +289,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -306,6 +327,7 @@ check_flush=true checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +eventq_index=0 num_cpus=1 system=system wakeup_frequency=10 @@ -314,5 +336,6 @@ cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr index f5d2abbce..2b5c3b11d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr @@ -2,4 +2,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: rounding error > tolerance 0.072760 rounded to 0 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 980451a66..8f18036b7 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:17:28 -gem5 started Sep 22 2013 05:17:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:32:54 +gem5 started Jan 22 2014 17:25:38 +gem5 executing on u200540-lin command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index ca2b008f4..618345d21 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.000172 # Nu sim_ticks 172201 # Number of ticks simulated final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1338362 # Simulator tick rate (ticks/s) -host_mem_usage 168248 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 1805084 # Simulator tick rate (ticks/s) +host_mem_usage 124680 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 system.ruby.outstanding_req_hist::samples 986 @@ -40,6 +43,7 @@ system.ruby.miss_latency_hist::stdev 1015.184360 system.ruby.miss_latency_hist | 60 7.09% 7.09% | 28 3.31% 10.40% | 1 0.12% 10.52% | 3 0.35% 10.87% | 14 1.65% 12.53% | 145 17.14% 29.67% | 352 41.61% 71.28% | 192 22.70% 93.97% | 40 4.73% 98.70% | 11 1.30% 100.00% system.ruby.miss_latency_hist::total 846 system.ruby.Directory.incomplete_times 846 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.L1Dcache.demand_hits 70 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 848 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini index 5aaa9746f..25bd77a4f 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -12,6 +14,7 @@ children=clk_domain physmem ruby sys_port_proxy tester voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.physmem] @@ -40,6 +44,7 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30 latency_var=0 @@ -48,18 +53,22 @@ range=0:134217727 [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=268435456 no_mem_vec=false +num_of_sequencers=1 random_seed=1234 randomization=true -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=1 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -67,9 +76,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -80,6 +90,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=268435456 @@ -96,6 +107,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -115,7 +127,8 @@ buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 +eventq_index=0 issue_latency=2 number_of_TBEs=256 peer=Null @@ -131,6 +144,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -146,6 +160,7 @@ access_phys_mem=false clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory max_outstanding_requests=16 ruby_system=system.ruby @@ -161,6 +176,7 @@ slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0] type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -170,6 +186,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 number_of_virtual_networks=10 @@ -180,6 +197,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -189,6 +207,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers1 latency=1 @@ -198,6 +217,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=2 node_a=system.ruby.network.routers0 @@ -207,6 +227,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=3 node_a=system.ruby.network.routers1 @@ -216,32 +237,29 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=1 -ruby_system=system.ruby - [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -257,6 +275,7 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +eventq_index=0 num_cpus=1 system=system wakeup_frequency=10 @@ -265,5 +284,6 @@ cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr index f5d2abbce..2b5c3b11d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr @@ -2,4 +2,3 @@ warn: rounding error > tolerance 0.072760 rounded to 0 warn: rounding error > tolerance 0.072760 rounded to 0 -hack: be nice to actually delete the event here diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 6606669ac..f268d31d9 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:49 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:37 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 9c41d3d2f..67ca7d426 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,12 @@ sim_seconds 0.000222 # Nu sim_ticks 221941 # Number of ticks simulated final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2165156 # Simulator tick rate (ticks/s) -host_mem_usage 165760 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 3307860 # Simulator tick rate (ticks/s) +host_mem_usage 122180 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message system.ruby.delayHist::samples 1828 # delay histogram for all message @@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 573.775637 system.ruby.miss_latency_hist | 6 0.66% 0.66% | 4 0.44% 1.09% | 82 8.95% 10.04% | 594 64.85% 74.89% | 229 25.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 916 system.ruby.Directory.incomplete_times 916 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 38 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 917 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 955 # Number of cache demand accesses diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini index 61b6eb32e..b3c13e1c2 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu membus monitor physmem boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -34,10 +37,12 @@ system_port=system.membus.slave[1] type=SrcClockDomain children=voltage_domain clock=1000 +eventq_index=0 voltage_domain=system.clk_domain.voltage_domain [system.clk_domain.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 [system.cpu] @@ -45,12 +50,14 @@ type=TrafficGen clk_domain=system.clk_domain config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg elastic_req=false +eventq_index=0 system=system port=system.monitor.slave [system.membus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=16 @@ -69,6 +76,7 @@ disable_itt_dists=false disable_latency_hists=false disable_outstanding_hists=false disable_transaction_hists=false +eventq_index=0 itt_bins=20 itt_max_bin=100000 latency_bins=20 @@ -93,6 +101,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -104,13 +113,16 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout index 2426a6cee..cffe93183 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:53:51 -gem5 started Sep 22 2013 05:53:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:54:17 +gem5 started Jan 22 2014 17:29:00 +gem5 executing on u200540-lin command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt index 9c1ab67e5..9a5e1cab0 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 20181472495 # Simulator tick rate (ticks/s) -host_mem_usage 192916 # Number of bytes of host memory used -host_seconds 4.96 # Real time elapsed on the host +host_tick_rate 33856013702 # Simulator tick rate (ticks/s) +host_mem_usage 195468 # Number of bytes of host memory used +host_seconds 2.95 # Real time elapsed on the host +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini index 27a6fb9af..1932695fb 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu membus monitor physmem boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -34,10 +37,12 @@ system_port=system.membus.slave[1] type=SrcClockDomain children=voltage_domain clock=1000 +eventq_index=0 voltage_domain=system.clk_domain.voltage_domain [system.clk_domain.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 [system.cpu] @@ -45,12 +50,14 @@ type=TrafficGen clk_domain=system.clk_domain config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg elastic_req=false +eventq_index=0 system=system port=system.monitor.slave [system.membus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=16 @@ -69,6 +76,7 @@ disable_itt_dists=false disable_latency_hists=false disable_outstanding_hists=false disable_transaction_hists=false +eventq_index=0 itt_bins=20 itt_max_bin=100000 latency_bins=20 @@ -86,6 +94,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index efa3fa542..ccbd2154c 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:53:51 -gem5 started Sep 22 2013 05:53:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:54:17 +gem5 started Jan 22 2014 17:29:05 +gem5 executing on u200540-lin command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index 14b3c1d80..ead00396f 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,11 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8032030639 # Simulator tick rate (ticks/s) -host_mem_usage 228596 # Number of bytes of host memory used -host_seconds 12.45 # Real time elapsed on the host +host_tick_rate 14364594493 # Simulator tick rate (ticks/s) +host_mem_usage 195500 # Number of bytes of host memory used +host_seconds 6.96 # Real time elapsed on the host +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory |