diff options
Diffstat (limited to 'tests/quick')
67 files changed, 4930 insertions, 5018 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 0966923f5..c90d08af7 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:10 -M5 revision 93b1ca421839 7482 default qtip tip update_regr -M5 started Jun 25 2010 15:39:11 -M5 executing on zooks -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:02 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31194000 because target called exit() +Exiting @ tick 30538000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index baac829f6..9ad72b38e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 22440 # Simulator instruction rate (inst/s) -host_mem_usage 153392 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -host_tick_rate 109185606 # Simulator tick rate (ticks/s) +host_inst_rate 4413 # Simulator instruction rate (inst/s) +host_mem_usage 204480 # Number of bytes of host memory used +host_seconds 1.45 # Real time elapsed on the host +host_tick_rate 21040041 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31194000 # Number of ticks simulated +sim_ticks 30538000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 12573 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7990 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 21.904502 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 311 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 22.376672 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,8 +42,8 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.742192 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.742192 # CPI: Total CPI of All Threads +system.cpu.cpi 9.537320 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.537320 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency @@ -55,15 +55,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 5071500 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4093000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10234500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9449500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9688500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8945500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025297 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.617621 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025183 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.151125 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10234500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9449500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9688500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8945500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.617621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.151125 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -126,14 +126,14 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55706.484642 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52877.192982 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55703.071672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16322000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16321000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15070000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15069000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -145,31 +145,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16321000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses system.cpu.icache.demand_misses 293 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15070000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15069000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063594 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.240724 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.063218 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 129.469682 # Average occupied blocks per context system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6876 # number of overall hits -system.cpu.icache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16321000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses system.cpu.icache.overall_misses 293 # number of overall misses system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15070000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15069000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.240724 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.469682 # Cycle average of tags in use system.cpu.icache.total_refs 6876 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 48723 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102646 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102646 # IPC: Total IPC of All Threads +system.cpu.idleCycles 47410 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.104851 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.104851 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,36 +201,27 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52085.751979 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19741000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52035.714286 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002646 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +241,8 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.374052 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005668 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 185.735123 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency @@ -267,34 +258,34 @@ system.cpu.l2cache.overall_mshr_misses 452 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.374052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.735123 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62389 # number of cpu cycles simulated -system.cpu.runCycles 13666 # Number of cycles cpu stages are processed. +system.cpu.numCycles 61077 # number of cpu cycles simulated +system.cpu.runCycles 13667 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55203 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 53891 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.518056 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55836 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6553 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.503454 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55919 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 11.765476 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 54525 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6552 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.727442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 54607 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.370418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60336 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.593186 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 59024 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.290644 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 55985 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.361331 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 54673 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.264630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62389 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.485125 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 61077 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 4261d2ba3..63bbf8869 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:09:06 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:04 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12497500 because target called exit() +Exiting @ tick 12412500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index fd2b0ddaf..a57aece07 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80384 # Simulator instruction rate (inst/s) -host_mem_usage 204420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 156814646 # Simulator tick rate (ticks/s) +host_inst_rate 44712 # Simulator instruction rate (inst/s) +host_mem_usage 204968 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 86758837 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12497500 # Number of ticks simulated +sim_ticks 12412500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2245 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2222 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9528 76.65% 76.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1629 13.10% 89.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 491 3.95% 93.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 259 2.08% 95.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 156 1.25% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 104 0.84% 97.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 49 0.39% 99.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,295 +44,295 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses -system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2103 # number of overall hits -system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses -system.cpu.dcache.overall_misses 544 # number of overall misses -system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2119 # number of overall hits +system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use -system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use +system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2948 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2921 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2887 # DTB hits +system.cpu.dtb.data_hits 2860 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1865 # DTB read accesses +system.cpu.dtb.read_accesses 1845 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1829 # DTB read hits +system.cpu.dtb.read_hits 1809 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1083 # DTB write accesses +system.cpu.dtb.write_accesses 1076 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1058 # DTB write hits +system.cpu.dtb.write_hits 1051 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched -system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched +system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses system.cpu.icache.demand_misses 426 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1366 # number of overall hits -system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_hits 1348 # number of overall hits +system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses system.cpu.icache.overall_misses 426 # number of overall misses system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use -system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use +system.cpu.icache.total_refs 1348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1448 # Number of branches executed -system.cpu.iew.EXEC:nop 83 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate -system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1085 # Number of stores executed +system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1435 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate +system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1078 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6049 # num instructions consuming a value -system.cpu.iew.WB:count 8759 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back +system.cpu.iew.WB:consumers 6007 # num instructions consuming a value +system.cpu.iew.WB:count 8682 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4508 # num instructions producing a value -system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle -system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.WB:producers 4474 # num instructions producing a value +system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle +system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads +system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 9142 68.58% 68.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1697 12.73% 81.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1062 7.97% 89.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 730 5.48% 94.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 359 2.69% 97.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 188 1.41% 98.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 105 0.79% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate -system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate +system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1827 # ITB accesses +system.cpu.itb.fetch_accesses 1808 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1792 # ITB hits -system.cpu.itb.fetch_misses 35 # ITB misses +system.cpu.itb.fetch_hits 1774 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,100 +342,91 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24996 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24826 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index b9c9ec747..17f796bc5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 7ee1b22c1..2df06d2e2 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:02 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:59:22 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 33777000 because target called exit() +Exiting @ tick 33007000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 998b710c1..0a6e1d861 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 605866 # Simulator instruction rate (inst/s) -host_mem_usage 190120 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 3109075847 # Simulator tick rate (ticks/s) +host_inst_rate 332796 # Simulator instruction rate (inst/s) +host_mem_usage 204128 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1691799077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33777000 # Number of ticks simulated +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33007000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 95 # nu system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -180,18 +180,9 @@ system.cpu.l2cache.ReadReq_misses 373 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -211,8 +202,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,14 +219,14 @@ system.cpu.l2cache.overall_mshr_misses 446 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.numCycles 66014 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index a969330c7..621a02c83 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:04:41 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7285000 because target called exit() +Exiting @ tick 7300000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7aa7cb16b..a87f9a576 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8638 # Simulator instruction rate (inst/s) -host_mem_usage 203416 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 26335958 # Simulator tick rate (ticks/s) +host_inst_rate 34398 # Simulator instruction rate (inst/s) +host_mem_usage 203876 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 104794717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7285000 # Number of ticks simulated +sim_ticks 7300000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 916 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 926 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5366 84.86% 84.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 262 4.14% 89.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 338 5.35% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 131 2.07% 96.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 32 0.51% 99.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,248 +44,248 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses -system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses +system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 692 # number of overall hits -system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses -system.cpu.dcache.overall_misses 197 # number of overall misses -system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses +system.cpu.dcache.overall_hits 721 # number of overall hits +system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses +system.cpu.dcache.overall_misses 172 # number of overall misses +system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use -system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use +system.cpu.dcache.total_refs 721 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1016 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 979 # DTB hits -system.cpu.dtb.data_misses 31 # DTB misses +system.cpu.dtb.data_hits 978 # DTB hits +system.cpu.dtb.data_misses 38 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 638 # DTB read accesses +system.cpu.dtb.read_accesses 648 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 623 # DTB read hits -system.cpu.dtb.read_misses 15 # DTB read misses -system.cpu.dtb.write_accesses 372 # DTB write accesses +system.cpu.dtb.read_hits 627 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 368 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.fetch.Branches 916 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 789 # Number of cache lines fetched -system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 351 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.fetch.Branches 926 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 782 # Number of cache lines fetched +system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency -system.cpu.icache.demand_hits 555 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency +system.cpu.icache.demand_hits 548 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses system.cpu.icache.demand_misses 234 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context -system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context +system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 555 # number of overall hits -system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_hits 548 # number of overall hits +system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses system.cpu.icache.overall_misses 234 # number of overall misses system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use -system.cpu.icache.total_refs 555 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use +system.cpu.icache.total_refs 548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 607 # Number of branches executed -system.cpu.iew.EXEC:nop 310 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate -system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 372 # Number of stores executed +system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 601 # Number of branches executed +system.cpu.iew.EXEC:nop 306 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate +system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 368 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1984 # num instructions consuming a value -system.cpu.iew.WB:count 3409 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back +system.cpu.iew.WB:consumers 1981 # num instructions consuming a value +system.cpu.iew.WB:count 3402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1585 # num instructions producing a value -system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:producers 1576 # num instructions producing a value +system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available @@ -300,38 +300,38 @@ system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # at system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5134 76.74% 76.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 621 9.28% 86.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 357 5.34% 91.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 240 3.59% 94.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 184 2.75% 97.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 102 1.52% 99.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 36 0.54% 99.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 11 0.16% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate -system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 818 # ITB accesses +system.cpu.itb.fetch_accesses 811 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 789 # ITB hits +system.cpu.itb.fetch_hits 782 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,23 +351,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -377,63 +368,64 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14571 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index ab47c5c67..c142fa659 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 2135491a6..6dd6e994b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:06 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 17374000 because target called exit() +Exiting @ tick 16769000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3c63125e0..f08ca087e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 400715 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2582342449 # Simulator tick rate (ticks/s) +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_mem_usage 203308 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 629585132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17374000 # Number of ticks simulated +sim_ticks 16769000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 93 # number of overall misses +system.cpu.dcache.overall_hits 627 # number of overall hits +system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 218 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 245 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34748 # number of cpu cycles simulated +system.cpu.numCycles 33538 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 2e799ebf3..4692f4932 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:33 -M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr -M5 started Jun 25 2010 15:39:34 -M5 executing on zooks -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:32 +M5 executing on zizzer +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29206500 because target called exit() +Exiting @ tick 28659500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index dd117802e..18095c949 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 22033 # Simulator instruction rate (inst/s) -host_mem_usage 154168 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -host_tick_rate 110232758 # Simulator tick rate (ticks/s) +host_inst_rate 16536 # Simulator instruction rate (inst/s) +host_mem_usage 205460 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 81268272 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29206500 # Number of ticks simulated +sim_ticks 28659500 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10682 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7272 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10688 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7278 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 31 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 20.277673 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 25 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 20.706560 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,8 +42,8 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads +system.cpu.cpi 9.836966 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.836966 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency @@ -55,15 +55,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3601000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3409000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56254.901961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53254.901961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2716000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56245.033113 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8493000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses -system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 56239.130435 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7761000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8040000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7347000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021533 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 88.199028 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56239.130435 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1938 # number of overall hits -system.cpu.dcache.overall_miss_latency 8493000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses -system.cpu.dcache.overall_misses 151 # number of overall misses +system.cpu.dcache.overall_hits 1951 # number of overall hits +system.cpu.dcache.overall_miss_latency 7761000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8040000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7347000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 88.199028 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -118,64 +118,64 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 5869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55795.379538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52795.379538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5566 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16906000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.051627 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15997000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.051627 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.369637 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency -system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses +system.cpu.icache.demand_accesses 5869 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55795.379538 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency +system.cpu.icache.demand_hits 5566 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16906000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.051627 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15997000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.051627 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context -system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.065748 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 134.651831 # Average occupied blocks per context +system.cpu.icache.overall_accesses 5869 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55795.379538 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5571 # number of overall hits -system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses +system.cpu.icache.overall_hits 5566 # number of overall hits +system.cpu.icache.overall_miss_latency 16906000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.051627 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15997000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.051627 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use -system.cpu.icache.total_refs 5571 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 134.651831 # Cycle average of tags in use +system.cpu.icache.total_refs 5566 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads +system.cpu.idleCycles 45451 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.101657 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.101657 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -186,46 +186,37 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52254.901961 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2665000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52086.340206 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20209500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52192.307692 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40153.846154 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 678500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 522000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52105.922551 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22874500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -235,14 +226,14 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 190.726729 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52105.922551 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22874500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses system.cpu.l2cache.overall_misses 439 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -252,34 +243,34 @@ system.cpu.l2cache.overall_mshr_misses 439 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 190.726729 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 58414 # number of cpu cycles simulated -system.cpu.runCycles 11845 # Number of cycles cpu stages are processed. +system.cpu.numCycles 57320 # number of cpu cycles simulated +system.cpu.runCycles 11869 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 51451 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 5869 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.239009 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 51492 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 10.167481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 51488 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.174459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 55230 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.646197 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 51493 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.165736 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 57320 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 17b9c89ad..5dcdeab67 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simout -Redirecting stderr to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simerr +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:55:57 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:56:00 +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:32 M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14021500 because target called exit() +Exiting @ tick 14010500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 9cdd99a02..ed89de0db 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59393 # Simulator instruction rate (inst/s) -host_mem_usage 205240 # Number of bytes of host memory used +host_inst_rate 60755 # Simulator instruction rate (inst/s) +host_mem_usage 205968 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 160627549 # Simulator tick rate (ticks/s) +host_tick_rate 164238154 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14021500 # Number of ticks simulated +sim_ticks 14010500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 1895 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1584 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2400 # Number of BP lookups system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14458 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402960 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127371 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 11934 82.37% 82.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1210 8.35% 90.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 523 3.61% 94.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 294 2.03% 98.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 11898 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1218 8.42% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 521 3.60% 94.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 296 2.05% 98.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 65 0.45% 98.84% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6 62 0.43% 99.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 37 0.26% 99.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 39 0.27% 99.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 67 0.46% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14458 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,85 +44,85 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5944 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses +system.cpu.cpi 5.421165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.421165 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36021.978022 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2179 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.055483 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039445 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36046.875000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 628 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8188500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.321081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 297 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 233 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2307000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 27330.827068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 659 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.287568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 266 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 216 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1808000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.054054 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.127660 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses -system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 3232 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29741.116751 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2838 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 11718000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.121906 # miss rate for demand accesses +system.cpu.dcache.demand_misses 394 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5086000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.043626 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022299 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.337822 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3232 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29741.116751 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2804 # number of overall hits -system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses -system.cpu.dcache.overall_misses 431 # number of overall misses -system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2838 # number of overall hits +system.cpu.dcache.overall_miss_latency 11718000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.121906 # miss rate for overall accesses +system.cpu.dcache.overall_misses 394 # number of overall misses +system.cpu.dcache.overall_mshr_hits 253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5086000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.043626 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use -system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.337822 # Cycle average of tags in use +system.cpu.dcache.total_refs 2838 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 514 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 14307 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3899 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1070 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,118 +133,118 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched -system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Branches 2400 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2213 # Number of cache lines fetched +system.cpu.fetch.Cycles 6297 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 357 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15518 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 762 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085647 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2213 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 0.553779 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261429 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11461 73.81% 73.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1813 11.68% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 195 1.26% 86.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 114 0.73% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 288 1.85% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 259 1.67% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 938 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15528 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2213 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35692.399050 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34907.294833 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1792 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190239 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 421 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11484500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148667 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.446809 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency -system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses -system.cpu.icache.demand_misses 422 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 2213 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35692.399050 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency +system.cpu.icache.demand_hits 1792 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190239 # miss rate for demand accesses +system.cpu.icache.demand_misses 421 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11484500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148667 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076220 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.098402 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2213 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35692.399050 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1794 # number of overall hits -system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses -system.cpu.icache.overall_misses 422 # number of overall misses -system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1792 # number of overall hits +system.cpu.icache.overall_miss_latency 15026500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190239 # miss rate for overall accesses +system.cpu.icache.overall_misses 421 # number of overall misses +system.cpu.icache.overall_mshr_hits 92 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11484500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148667 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use -system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.098402 # Cycle average of tags in use +system.cpu.icache.total_refs 1792 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1268 # Number of branches executed -system.cpu.iew.EXEC:nop 1827 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate -system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1049 # Number of stores executed +system.cpu.idleCycles 12494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1265 # Number of branches executed +system.cpu.iew.EXEC:nop 1823 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295232 # Inst execution rate +system.cpu.iew.EXEC:refs 3434 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1042 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4139 # num instructions consuming a value -system.cpu.iew.WB:count 7538 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back +system.cpu.iew.WB:consumers 4130 # num instructions consuming a value +system.cpu.iew.WB:count 7520 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704843 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2914 # num instructions producing a value -system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle -system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2911 # num instructions producing a value +system.cpu.iew.WB:rate 0.268361 # insts written-back per cycle +system.cpu.iew.WB:sent 7608 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 678 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2792 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions +system.cpu.iew.iewDispStoreInsts 1150 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11774 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2392 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 540 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8273 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1070 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -252,71 +252,71 @@ system.cpu.iew.lsq.thread.0.forwLoads 67 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 19 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1628 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 225 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads +system.cpu.ipc 0.184462 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184462 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5164 58.60% 58.60% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2584 29.32% 88.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1056 11.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8813 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 160 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018155 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 8 5.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 100 62.50% 67.50% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 52 32.50% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567555 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215524 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 11605 74.58% 74.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1745 11.21% 85.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 791 5.08% 90.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 727 4.67% 95.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 340 2.18% 97.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 213 1.37% 99.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 93 0.60% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.21% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 11574 74.54% 74.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1747 11.25% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 792 5.10% 90.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 724 4.66% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 342 2.20% 97.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 211 1.36% 99.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 94 0.61% 99.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 29 0.19% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate -system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.314503 # Inst issue rate +system.cpu.iq.iqInstsAdded 9939 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8813 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 4094 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2672 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -336,37 +336,28 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34319.711538 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14277000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34428.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 482000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009950 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34358.369099 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16011000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -376,14 +367,14 @@ system.cpu.l2cache.demand_mshr_misses 466 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 215.818258 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34358.369099 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16011000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -393,33 +384,33 @@ system.cpu.l2cache.overall_mshr_misses 466 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 215.818258 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28044 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 2792 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1150 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28022 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 10436 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15725 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13557 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8322 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3509 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1070 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4912 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 104 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index b04189060..e2f4de6ac 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -211,7 +211,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 31e8564a2..bfd8a31fc 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:22 -M5 executing on SC2B0619 -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:30 +M5 executing on zizzer +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32803000 because target called exit() +Exiting @ tick 32088000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 5c8b8dc04..f4ea21892 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 534293 # Simulator instruction rate (inst/s) -host_mem_usage 190944 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2928316372 # Simulator tick rate (ticks/s) +host_inst_rate 5098 # Simulator instruction rate (inst/s) +host_mem_usage 204896 # Number of bytes of host memory used +host_seconds 1.14 # Real time elapsed on the host +host_tick_rate 28066026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32803000 # Number of ticks simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32088000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 87 # nu system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses -system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8003000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 87.887695 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1938 # number of overall hits -system.cpu.dcache.overall_miss_latency 8456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses -system.cpu.dcache.overall_misses 151 # number of overall misses +system.cpu.dcache.overall_hits 1951 # number of overall hits +system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8003000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 87.887695 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 303 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.065174 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 133.475693 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.475693 # Cycle average of tags in use +system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -166,18 +166,9 @@ system.cpu.l2cache.ReadReq_misses 388 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 520000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -197,8 +188,8 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005638 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 184.758016 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -214,14 +205,14 @@ system.cpu.l2cache.overall_mshr_misses 439 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 184.758016 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 65606 # number of cpu cycles simulated +system.cpu.numCycles 64176 # number of cpu cycles simulated system.cpu.num_insts 5827 # Number of instructions executed system.cpu.num_refs 2090 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 91e0a0356..d552956c6 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17982776. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index b9932c144..f838ffb8f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simout -Redirecting stderr to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simerr +Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout +Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:59:10 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:59:12 +M5 compiled Aug 26 2010 12:59:22 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:59:25 M5 executing on zizzer -command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11864500 because target called exit() +Exiting @ tick 11733000 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index e78679f83..914654ad0 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82571 # Simulator instruction rate (inst/s) -host_mem_usage 202992 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 168278845 # Simulator tick rate (ticks/s) +host_inst_rate 8561 # Simulator instruction rate (inst/s) +host_mem_usage 202624 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 17311106 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11864500 # Number of ticks simulated +sim_ticks 11733000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 189 # Nu system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8225 76.26% 76.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1129 10.47% 86.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 673 6.24% 92.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 258 2.39% 95.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 226 2.10% 97.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 120 1.11% 98.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 82 0.76% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 21 0.19% 99.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed @@ -47,30 +47,30 @@ system.cpu.commit.commitNonSpecStalls 16 # Th system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. @@ -80,51 +80,51 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses -system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses +system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2050 # number of overall hits -system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses -system.cpu.dcache.overall_misses 440 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2093 # number of overall hits +system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses +system.cpu.dcache.overall_misses 397 # number of overall misses +system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -140,36 +140,36 @@ system.cpu.fetch.Cycles 3561 # Nu system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -181,31 +181,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses system.cpu.icache.demand_misses 386 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1104 # number of overall hits -system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses system.cpu.icache.overall_misses 386 # number of overall misses system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,27 +213,27 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:consumers 5926 # num instructions consuming a value system.cpu.iew.WB:count 7582 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3806 # num instructions producing a value -system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:producers 3825 # num instructions producing a value +system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch @@ -246,7 +246,7 @@ system.cpu.iew.iewIQFullEvents 4 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores @@ -260,8 +260,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 # system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads +system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued @@ -293,24 +293,24 @@ system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # at system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8066 71.03% 71.03% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1182 10.41% 81.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 820 7.22% 88.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 507 4.46% 93.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 388 3.42% 96.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 218 1.92% 98.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 121 1.07% 99.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -328,46 +328,37 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -377,14 +368,14 @@ system.cpu.l2cache.demand_mshr_misses 428 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -394,9 +385,9 @@ system.cpu.l2cache.overall_mshr_misses 428 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -404,24 +395,24 @@ system.cpu.memDep0.conflictingLoads 67 # Nu system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23730 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking +system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index d91ebcc59..35f8386c3 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 9485c1bb2..9b5f99faf 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:37:59 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:05:08 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 29031000 because target called exit() +Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 11fb745f1..49d0076df 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 462498 # Simulator instruction rate (inst/s) -host_mem_usage 190336 # Number of bytes of host memory used +host_inst_rate 369934 # Simulator instruction rate (inst/s) +host_mem_usage 207380 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2452978454 # Simulator tick rate (ticks/s) +host_tick_rate 1923223783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29031000 # Number of ticks simulated +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28206000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 54 # nu system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4536000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses -system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1254 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097192 # miss rate for demand accesses +system.cpu.dcache.demand_misses 135 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020107 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 82.357482 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 82.065697 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses -system.cpu.dcache.overall_misses 150 # number of overall misses +system.cpu.dcache.overall_hits 1254 # number of overall hits +system.cpu.dcache.overall_miss_latency 7518000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097192 # miss rate for overall accesses +system.cpu.dcache.overall_misses 135 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 257 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.057478 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 117.715481 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use +system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses 308 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses 389 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004176 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 136.844792 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 142.102892 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses 389 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 58062 # number of cpu cycles simulated +system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 2a02cd35e..f57480110 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:33:02 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 29813000 because target called exit() +Exiting @ tick 28768000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index cc8de12ad..eecf4ab78 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 734670 # Simulator instruction rate (inst/s) -host_mem_usage 220588 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2255655595 # Simulator tick rate (ticks/s) +host_inst_rate 397795 # Simulator instruction rate (inst/s) +host_mem_usage 205892 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1184355702 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9561 # Number of instructions simulated -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29813000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28768000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1837 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8568000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.076884 # miss rate for demand accesses -system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.076884 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.019841 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 81.267134 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1837 # number of overall hits -system.cpu.dcache.overall_miss_latency 8568000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.076884 # miss rate for overall accesses -system.cpu.dcache.overall_misses 153 # number of overall misses +system.cpu.dcache.overall_hits 1856 # number of overall hits +system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_misses 134 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8109000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.076884 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.267134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 228 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.052030 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 106.557747 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 106.557747 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses 282 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003802 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses 361 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003920 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 128.459536 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses 361 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 263 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 128.459536 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59626 # number of cpu cycles simulated +system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.num_insts 9561 # Number of instructions executed system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 849e6b2a1..8e80e0787 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,15 +7,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:17:19 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:11:50 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14406500 because target called exit() +Exiting @ tick 14139000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index b84cef0e7..f38e46afc 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 70938 # Simulator instruction rate (inst/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 79897622 # Simulator tick rate (ticks/s) +host_inst_rate 53800 # Simulator instruction rate (inst/s) +host_mem_usage 205552 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 59488297 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14406500 # Number of ticks simulated +sim_ticks 14139000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 801 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4845 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4600 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1651 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3171 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5637 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 690 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3069 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5341 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches::0 1051 # Number of branches committed system.cpu.commit.COM:branches::1 1051 # Number of branches committed system.cpu.commit.COM:branches::total 2102 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 135 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 132 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 23178 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.552550 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.284564 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 22158 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.577985 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.311672 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 17373 74.95% 74.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 2862 12.35% 87.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1369 5.91% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 536 2.31% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 355 1.53% 97.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 284 1.23% 98.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 169 0.73% 99.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 95 0.41% 99.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 135 0.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 16375 73.90% 73.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 2877 12.98% 86.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1274 5.75% 92.63% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 599 2.70% 95.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 362 1.63% 96.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 252 1.14% 98.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 188 0.85% 98.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 99 0.45% 99.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 132 0.60% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 23178 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22158 # Number of insts commited each cycle system.cpu.commit.COM:count::0 6404 # Number of instructions committed system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed @@ -55,118 +55,118 @@ system.cpu.commit.COM:refs::total 4100 # Nu system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1214 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1116 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 11211 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10253 # The number of squashed insts skipped by commit system.cpu.committedInsts::0 6387 # Number of Instructions Simulated system.cpu.committedInsts::1 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.511351 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.512058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.255852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 35613.003096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35613.003096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36812.195122 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3630 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 11503000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.051859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses +system.cpu.cpi::0 4.427587 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.428281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.213967 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 36145.962733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36145.962733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36908.415842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3474 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 11639000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11639000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.084826 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 322 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.053214 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053214 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 33528.289474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33528.289474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36083.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 25481500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25481500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 6278500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6278500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency::0 32784.604520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32784.604520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36119.863014 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::0 23211500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23211500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::0 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5273500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5273500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.282051 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.919540 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5683 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 34150.046168 # average overall miss latency +system.cpu.dcache.demand_accesses 5526 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33835.436893 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34150.046168 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.436893 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4600 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 36984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 4496 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 34850500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.190568 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1083 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 704 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_miss_latency::total 34850500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.186392 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1030 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 682 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 704 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 13825000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 12729000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13825000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.066690 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency::total 12729000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.062975 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066690 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 379 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 379 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.054473 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 223.120996 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5683 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 34150.046168 # average overall miss latency +system.cpu.dcache.occ_%::0 0.053836 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 220.510583 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5526 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33835.436893 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34150.046168 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.436893 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4600 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 36984500 # number of overall miss cycles +system.cpu.dcache.overall_hits 4496 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 34850500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.190568 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1083 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 704 # number of overall MSHR hits +system.cpu.dcache.overall_miss_latency::total 34850500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.186392 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1030 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 682 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 704 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 13825000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 12729000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13825000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.066690 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency::total 12729000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.062975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066690 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 379 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 379 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -176,153 +176,153 @@ system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.120996 # Cycle average of tags in use -system.cpu.dcache.total_refs 4662 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 220.510583 # Cycle average of tags in use +system.cpu.dcache.total_refs 4496 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 451 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 595 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 27842 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 34006 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4930 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2198 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 677 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6328 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 4667 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 414 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 569 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 26624 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32585 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4771 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2039 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 734 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 6131 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 6178 # DTB hits -system.cpu.dtb.data_misses 150 # DTB misses +system.cpu.dtb.data_hits 5993 # DTB hits +system.cpu.dtb.data_misses 138 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 4160 # DTB read accesses +system.cpu.dtb.read_accesses 3997 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 4072 # DTB read hits -system.cpu.dtb.read_misses 88 # DTB read misses -system.cpu.dtb.write_accesses 2168 # DTB write accesses +system.cpu.dtb.read_hits 3913 # DTB read hits +system.cpu.dtb.read_misses 84 # DTB read misses +system.cpu.dtb.write_accesses 2134 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2106 # DTB write hits -system.cpu.dtb.write_misses 62 # DTB write misses -system.cpu.fetch.Branches 5637 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4152 # Number of cache lines fetched -system.cpu.fetch.Cycles 9523 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 615 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 31429 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1766 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.195634 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1491 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.090754 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 23259 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.351262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.751825 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 2080 # DTB write hits +system.cpu.dtb.write_misses 54 # DTB write misses +system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched +system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1570 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.056650 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 22205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.345688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.736511 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17946 77.16% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 425 1.83% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 330 1.42% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 452 1.94% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 406 1.75% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 353 1.52% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 452 1.94% 87.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 273 1.17% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2622 11.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17092 76.97% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 418 1.88% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 346 1.56% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 428 1.93% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 443 2.00% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 320 1.44% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 433 1.95% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 283 1.27% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23259 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4152 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 35658.767773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35658.767773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35482.171799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3308 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 30096000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30096000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.203276 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.148603 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148603 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 617 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 617 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35489.482201 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3157 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 29902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.209366 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.154771 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154771 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.361426 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.108414 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4152 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 35658.767773 # average overall miss latency +system.cpu.icache.demand_accesses 3993 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35767.942584 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35658.767773 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency::total 35767.942584 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3308 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 30096000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 3157 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 29902000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30096000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.203276 # miss rate for demand accesses -system.cpu.icache.demand_misses 844 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_miss_latency::total 29902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.209366 # miss rate for demand accesses +system.cpu.icache.demand_misses 836 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 218 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21932500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.148603 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 21932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.154771 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148603 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 617 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_rate::total 0.154771 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 617 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.156062 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 319.614812 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4152 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 35658.767773 # average overall miss latency +system.cpu.icache.occ_%::0 0.155666 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 318.803897 # Average occupied blocks per context +system.cpu.icache.overall_accesses 3993 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35767.942584 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35658.767773 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency::total 35767.942584 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3308 # number of overall hits -system.cpu.icache.overall_miss_latency::0 30096000 # number of overall miss cycles +system.cpu.icache.overall_hits 3157 # number of overall hits +system.cpu.icache.overall_miss_latency::0 29902000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30096000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.203276 # miss rate for overall accesses -system.cpu.icache.overall_misses 844 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 227 # number of overall MSHR hits +system.cpu.icache.overall_miss_latency::total 29902000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.209366 # miss rate for overall accesses +system.cpu.icache.overall_misses 836 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 218 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21892500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21932500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.148603 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency::total 21932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.154771 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148603 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 617 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_rate::total 0.154771 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 617 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -332,198 +332,198 @@ system.cpu.icache.overall_mshr_uncacheable_misses::total 0 system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 617 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 319.614812 # Cycle average of tags in use -system.cpu.icache.total_refs 3308 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 318.803897 # Cycle average of tags in use +system.cpu.icache.total_refs 3157 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks::0 0 # number of writebacks system.cpu.icache.writebacks::1 0 # number of writebacks system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5555 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches::0 1592 # Number of branches executed -system.cpu.iew.EXEC:branches::1 1585 # Number of branches executed -system.cpu.iew.EXEC:branches::total 3177 # Number of branches executed -system.cpu.iew.EXEC:nop::0 69 # number of nop insts executed -system.cpu.iew.EXEC:nop::1 66 # number of nop insts executed -system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.670750 # Inst execution rate -system.cpu.iew.EXEC:refs::0 3218 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::1 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::total 6350 # number of memory reference insts executed -system.cpu.iew.EXEC:stores::0 1105 # Number of stores executed -system.cpu.iew.EXEC:stores::1 1082 # Number of stores executed -system.cpu.iew.EXEC:stores::total 2187 # Number of stores executed +system.cpu.idleCycles 6074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches::0 1552 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1552 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3104 # Number of branches executed +system.cpu.iew.EXEC:nop::0 64 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 70 # number of nop insts executed +system.cpu.iew.EXEC:nop::total 134 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.666325 # Inst execution rate +system.cpu.iew.EXEC:refs::0 3105 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3045 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6150 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1087 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1064 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2151 # Number of stores executed system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed -system.cpu.iew.WB:consumers::0 6017 # num instructions consuming a value -system.cpu.iew.WB:consumers::1 5962 # num instructions consuming a value -system.cpu.iew.WB:consumers::total 11979 # num instructions consuming a value -system.cpu.iew.WB:count::0 9293 # cumulative count of insts written-back -system.cpu.iew.WB:count::1 9238 # cumulative count of insts written-back -system.cpu.iew.WB:count::total 18531 # cumulative count of insts written-back -system.cpu.iew.WB:fanout::0 0.773143 # average fanout of values written-back -system.cpu.iew.WB:fanout::1 0.773398 # average fanout of values written-back -system.cpu.iew.WB:fanout::total 1.546541 # average fanout of values written-back +system.cpu.iew.WB:consumers::0 5852 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5867 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11719 # num instructions consuming a value +system.cpu.iew.WB:count::0 9073 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9067 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18140 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.775290 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.774501 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.549792 # average fanout of values written-back system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers::0 4652 # num instructions producing a value -system.cpu.iew.WB:producers::1 4611 # num instructions producing a value -system.cpu.iew.WB:producers::total 9263 # num instructions producing a value -system.cpu.iew.WB:rate::0 0.322517 # insts written-back per cycle -system.cpu.iew.WB:rate::1 0.320608 # insts written-back per cycle -system.cpu.iew.WB:rate::total 0.643125 # insts written-back per cycle -system.cpu.iew.WB:sent::0 9430 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::1 9343 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::total 18773 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1399 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1055 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 5029 # Number of dispatched load instructions +system.cpu.iew.WB:producers::0 4537 # num instructions producing a value +system.cpu.iew.WB:producers::1 4544 # num instructions producing a value +system.cpu.iew.WB:producers::total 9081 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.320839 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.320627 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.641465 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9197 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9165 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18362 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1270 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 840 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4751 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 731 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2605 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24098 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 2113 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2050 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1224 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 19327 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2526 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 23137 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts::0 2018 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1981 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3999 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1059 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18843 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2198 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 2039 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1385 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 471 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1198 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 429 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1274 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 404 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 135 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1143 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 256 # Number of branches that were predicted taken incorrectly -system.cpu.ipc::0 0.221663 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.221628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.443291 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.1.squashedLoads 1183 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 367 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly +system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6901 66.76% 66.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2273 21.99% 88.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1158 11.20% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6654 67.06% 67.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 10337 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 9923 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntAlu 6867 67.23% 67.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemRead 2182 21.36% 88.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemWrite 1160 11.36% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6748 67.62% 67.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::total 10214 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 9979 # Type of FU issued system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntAlu 13768 66.99% 67.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemRead 4455 21.68% 88.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemWrite 2318 11.28% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13402 67.34% 67.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::total 20551 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt::0 79 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::total 167 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate::0 0.003844 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::1 0.004282 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::total 0.008126 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type::total 19902 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 80 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 165 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.004020 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004271 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008291 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 9 5.39% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 95 56.89% 62.28% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 37.72% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 16 9.70% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 23259 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.883572 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458526 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 22205 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.896285 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.439530 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 14576 62.67% 62.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 3197 13.75% 76.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2342 10.07% 86.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1327 5.71% 92.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 883 3.80% 95.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 568 2.44% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 270 1.16% 99.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 71 0.31% 99.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 25 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 13672 61.57% 61.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 3186 14.35% 75.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 2211 9.96% 85.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1439 6.48% 92.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 897 4.04% 96.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 509 2.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 214 0.96% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 56 0.25% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 21 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 23259 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.713230 # Inst issue rate -system.cpu.iq.iqInstsAdded 23917 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20551 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate +system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9939 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9000 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 5071 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4210 # ITB accesses +system.cpu.itb.fetch_accesses 4049 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 4152 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.itb.fetch_hits 3993 # ITB hits +system.cpu.itb.fetch_misses 56 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -533,11 +533,11 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34623.287671 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5055000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5055000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles @@ -546,103 +546,89 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34548.170732 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34548.170732 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31393.902439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34537.897311 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34537.897311 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31396.088020 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28329500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28329500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997567 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25743000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25743000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997567 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997567 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 820 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31392.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency::0 966000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 966000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 879000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 879000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency::0 28252000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28252000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002525 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34559.523810 # average overall miss latency +system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34553.941909 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34559.523810 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34553.941909 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33384500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::0 33310000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33384500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997934 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency::total 33310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30348500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30287500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30348500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency::total 30287500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.013217 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 433.083390 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34559.523810 # average overall miss latency +system.cpu.l2cache.occ_%::0 0.013480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 441.702410 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34553.941909 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34559.523810 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34553.941909 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33384500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::0 33310000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33384500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997934 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 966 # number of overall misses +system.cpu.l2cache.overall_miss_latency::total 33310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 964 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30348500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30287500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30348500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 30287500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -652,43 +638,43 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 433.083390 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 441.702410 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::0 0 # number of writebacks system.cpu.l2cache.writebacks::1 0 # number of writebacks system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2570 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 27 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 5 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2459 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1269 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28814 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2841 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2383 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28279 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 34469 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1383 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 33046 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1284 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 33146 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 26493 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19854 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4562 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2198 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1440 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10688 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3428 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 31631 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 25294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18871 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4411 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index a68db2dd5..7b95c8bf1 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing/simerr +Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 04:01:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 04:04:37 +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:47 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -25,4 +25,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 27640500 because target called exit() +Exiting @ tick 27419000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index bf4cbe594..8c02012d9 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 74349 # Simulator instruction rate (inst/s) -host_mem_usage 204528 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 142076938 # Simulator tick rate (ticks/s) +host_inst_rate 45017 # Simulator instruction rate (inst/s) +host_mem_usage 207928 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host +host_tick_rate 85360538 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27640500 # Number of ticks simulated +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27419000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 9185 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 9180 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11479 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 11479 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11474 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11474 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 42520 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.356891 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 0.964493 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 41984 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.361447 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.969782 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 34367 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 4806 11.30% 92.13% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1719 4.04% 96.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 713 1.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 414 0.97% 98.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 146 0.34% 99.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 193 0.45% 99.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 33831 80.58% 80.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 4806 11.45% 92.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1719 4.09% 96.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 713 1.70% 97.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 414 0.99% 98.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 146 0.35% 99.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 193 0.46% 99.61% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::7 48 0.11% 99.73% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 42520 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 41984 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,35 +44,35 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 19910 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 19909 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 3.826009 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.826009 # CPI: Total CPI of All Threads +system.cpu.cpi 3.795349 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.795349 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35228.070175 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35561.538462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4016000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2311500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 35221.238938 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35546.153846 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029412 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2310500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31248.306998 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35612.745098 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13843000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3632500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 31011.029412 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35620.481928 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12652500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2956500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks. @@ -82,160 +82,160 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32062.836625 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4727 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17859000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.105413 # miss rate for demand accesses -system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 390 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5944000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.031605 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_avg_miss_latency 31924.184261 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4763 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16632500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.098600 # miss rate for demand accesses +system.cpu.dcache.demand_misses 521 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 373 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.028009 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026503 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 108.555093 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.026492 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 108.511216 # Average occupied blocks per context system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32062.836625 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 31924.184261 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4727 # number of overall hits -system.cpu.dcache.overall_miss_latency 17859000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.105413 # miss rate for overall accesses -system.cpu.dcache.overall_misses 557 # number of overall misses -system.cpu.dcache.overall_mshr_hits 390 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5944000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.031605 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses +system.cpu.dcache.overall_hits 4763 # number of overall hits +system.cpu.dcache.overall_miss_latency 16632500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.098600 # miss rate for overall accesses +system.cpu.dcache.overall_misses 521 # number of overall misses +system.cpu.dcache.overall_mshr_hits 373 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5267000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.028009 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 108.555093 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 108.511216 # Cycle average of tags in use system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7141 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 51862 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20451 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14795 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4325 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 6598 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51837 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20462 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14791 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 11479 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 7330 # Number of cache lines fetched -system.cpu.fetch.Cycles 23798 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 830 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 58419 # Number of instructions fetch has processed +system.cpu.fetch.Branches 11474 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7329 # Number of cache lines fetched +system.cpu.fetch.Cycles 23792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 833 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58386 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.207644 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 7330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.branchRate 0.209231 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7329 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.056745 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 46845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.247070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.396969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 1.064680 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 46308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.260819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.406261 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 30399 64.89% 64.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7442 15.89% 80.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1110 2.37% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 985 2.10% 85.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1044 2.23% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1211 2.59% 90.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 663 1.42% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 335 0.72% 92.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3656 7.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29867 64.50% 64.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7441 16.07% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1110 2.40% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 985 2.13% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1044 2.25% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1211 2.62% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 663 1.43% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 335 0.72% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3652 7.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46845 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 7330 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33618.691589 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34870.473538 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6795 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 17986000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.072988 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12518500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048977 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 46308 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 7329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33501.855288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6790 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 18057500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.073543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 539 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 180 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048983 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.980447 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.966480 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7330 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33618.691589 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency -system.cpu.icache.demand_hits 6795 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 17986000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.072988 # miss rate for demand accesses -system.cpu.icache.demand_misses 535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12518500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048977 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 7329 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33501.855288 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.demand_hits 6790 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 18057500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.073543 # miss rate for demand accesses +system.cpu.icache.demand_misses 539 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 180 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048983 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.110625 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 226.560324 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7330 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33618.691589 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.110645 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 226.601923 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7329 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33501.855288 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6795 # number of overall hits -system.cpu.icache.overall_miss_latency 17986000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.072988 # miss rate for overall accesses -system.cpu.icache.overall_misses 535 # number of overall misses -system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12518500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048977 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 6790 # number of overall hits +system.cpu.icache.overall_miss_latency 18057500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.073543 # miss rate for overall accesses +system.cpu.icache.overall_misses 539 # number of overall misses +system.cpu.icache.overall_mshr_hits 180 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048983 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 226.560324 # Cycle average of tags in use -system.cpu.icache.total_refs 6795 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 226.601923 # Cycle average of tags in use +system.cpu.icache.total_refs 6790 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8437 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4838 # Number of branches executed +system.cpu.idleCycles 8531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4839 # Number of branches executed system.cpu.iew.EXEC:nop 2088 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.449477 # Inst execution rate +system.cpu.iew.EXEC:rate 0.453126 # Inst execution rate system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed system.cpu.iew.EXEC:stores 2469 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 13103 # num instructions consuming a value -system.cpu.iew.WB:count 23891 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.824239 # average fanout of values written-back +system.cpu.iew.WB:consumers 13105 # num instructions consuming a value +system.cpu.iew.WB:count 23892 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.824189 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10800 # num instructions producing a value -system.cpu.iew.WB:rate 0.432166 # insts written-back per cycle -system.cpu.iew.WB:sent 24095 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3199 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 10801 # num instructions producing a value +system.cpu.iew.WB:rate 0.435675 # insts written-back per cycle +system.cpu.iew.WB:sent 24096 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3043 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 3048 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 35165 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4355 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 24848 # Number of executed instructions +system.cpu.iew.iewExecSquashedInsts 4356 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24849 # Number of executed instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4325 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -248,12 +248,12 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads 1 system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 814 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 815 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.261369 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.261369 # IPC: Total IPC of All Threads +system.cpu.ipc 0.263480 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263480 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 21370 73.18% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 21372 73.18% 73.18% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued @@ -266,7 +266,7 @@ system.cpu.iq.ISSUE:FU_type_0::MemRead 4722 16.17% 89.35% # Ty system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 29203 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 29205 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available @@ -283,35 +283,35 @@ system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # at system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 46845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623396 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.283288 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 46308 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.630669 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.289103 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 33954 72.48% 72.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 5459 11.65% 84.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 3016 6.44% 90.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 2133 4.55% 95.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 995 2.12% 97.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 695 1.48% 98.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.72% 99.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 33418 72.16% 72.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 5459 11.79% 83.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 3013 6.51% 90.46% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 2134 4.61% 95.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 995 2.15% 97.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 696 1.50% 98.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.73% 99.45% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::7 214 0.46% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 46845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.528255 # Inst issue rate -system.cpu.iq.iqInstsAdded 32305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 29203 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 46308 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.532559 # Inst issue rate +system.cpu.iq.iqInstsAdded 32304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29205 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15689 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 15678 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 12321 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 12314 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.590361 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34391.566265 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2855000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2854500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles @@ -319,65 +319,56 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.761905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.380952 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13022000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13021000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34342.105263 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 652500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009547 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34248.508946 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34247.514911 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17227000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 17226500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15621000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15620000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007671 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 251.347828 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.008034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 263.251984 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34248.508946 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34247.514911 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17227000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 17226500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses system.cpu.l2cache.overall_misses 503 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15621000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15620000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 419 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 251.347828 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 263.251984 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -385,24 +376,24 @@ system.cpu.memDep0.conflictingLoads 26 # Nu system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 55282 # number of cpu cycles simulated +system.cpu.numCycles 54839 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 22239 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 22249 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 74814 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 42611 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenameLookups 74810 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42608 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13163 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4325 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RunCycles 13159 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 6774 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 6232 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5153 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 824 # count of temporary serializing insts renamed -system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 5138 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 822 # count of temporary serializing insts renamed +system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 29f855cba..04665360b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 2c0f40a56..27524a121 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:01 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:44 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -23,4 +25,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 42735000 because target called exit() +Exiting @ tick 41800000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 07c8914c3..6c8846c5d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 227392 # Simulator instruction rate (inst/s) -host_mem_usage 190044 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 637540839 # Simulator tick rate (ticks/s) +host_inst_rate 255958 # Simulator instruction rate (inst/s) +host_mem_usage 207264 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 701295215 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 42735000 # Number of ticks simulated +sim_seconds 0.000042 # Number of seconds simulated +sim_ticks 41800000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -23,13 +23,13 @@ system.cpu.dcache.SwapReq_hits 6 # nu system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. @@ -41,37 +41,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses -system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 97.747327 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3513 # number of overall hits -system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses -system.cpu.dcache.overall_misses 155 # number of overall misses +system.cpu.dcache.overall_hits 3530 # number of overall hits +system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -107,8 +107,8 @@ system.cpu.icache.demand_mshr_misses 280 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 153.073222 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.074920 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency @@ -126,7 +126,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use +system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,18 +150,9 @@ system.cpu.l2cache.ReadReq_misses 331 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -181,8 +172,8 @@ system.cpu.l2cache.demand_mshr_misses 416 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -198,14 +189,14 @@ system.cpu.l2cache.overall_mshr_misses 416 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 85470 # number of cpu cycles simulated +system.cpu.numCycles 83600 # number of cpu cycles simulated system.cpu.num_insts 15175 # Number of instructions executed system.cpu.num_refs 3684 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 7292b0c1a..587e758aa 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -264,7 +265,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -284,7 +285,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -410,7 +411,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 74b825924..2604d666e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:44:34 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:21 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 7f610a74e..9b7657157 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3116744 # Simulator instruction rate (inst/s) -host_mem_usage 276812 # Number of bytes of host memory used -host_seconds 20.26 # Real time elapsed on the host -host_tick_rate 92302855126 # Simulator tick rate (ticks/s) +host_inst_rate 2244323 # Simulator instruction rate (inst/s) +host_mem_usage 293120 # Number of bytes of host memory used +host_seconds 28.14 # Real time elapsed on the host +host_tick_rate 66466128576 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -24,18 +24,18 @@ system.cpu0.dcache.ReadReq_misses::0 1683563 # nu system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits::0 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.146793 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 27500 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 27500 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_hits::0 165851 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 165851 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114696 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 21487 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21487 # number of StoreCondReq misses system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits::0 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate::0 0.065030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 373808 # number of WriteReq misses +system.cpu0.dcache.WriteReq_hits::0 5400040 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5400040 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate::0 0.060578 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 348221 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 348221 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. @@ -51,16 +51,16 @@ system.cpu0.dcache.demand_avg_miss_latency::0 0 system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12698146 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12698146 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::0 0.137936 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2031784 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2031784 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -80,16 +80,16 @@ system.cpu0.dcache.overall_avg_miss_latency::1 no_value system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::0 12698146 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::total 12698146 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.137936 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::0 2031784 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::total 2031784 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -104,7 +104,7 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 396793 # number of writebacks +system.cpu0.dcache.writebacks 419022 # number of writebacks system.cpu0.dtb.data_accesses 698037 # DTB accesses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_hits 15091429 # DTB hits @@ -323,18 +323,18 @@ system.cpu1.dcache.ReadReq_misses::0 41650 # nu system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_hits::0 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.177853 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 2907 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2907 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_hits::0 13853 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 13853 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.152463 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2492 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2492 # number of StoreCondReq misses system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits::0 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate::0 0.041595 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 30502 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 30502 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits::0 703732 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 703732 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate::0 0.040328 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 29573 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 29573 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. @@ -350,16 +350,16 @@ system.cpu1.dcache.demand_avg_miss_latency::0 0 system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1813047 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1813047 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::0 0.037799 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 71223 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 71223 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -379,16 +379,16 @@ system.cpu1.dcache.overall_avg_miss_latency::1 no_value system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::0 1813047 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::total 1813047 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.037799 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 72152 # number of overall misses +system.cpu1.dcache.overall_misses::0 71223 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 72152 # number of overall misses +system.cpu1.dcache.overall_misses::total 71223 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -403,7 +403,7 @@ system.cpu1.dcache.soft_prefetch_mshr_full 0 # system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30848 # number of writebacks +system.cpu1.dcache.writebacks 31228 # number of writebacks system.cpu1.dtb.data_accesses 323622 # DTB accesses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_hits 1914885 # DTB hits @@ -683,72 +683,81 @@ system.iocache.writebacks 41520 # nu system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits -system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses -system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses -system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses -system.l2c.SCUpgradeReq_accesses::0 26914 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 2297 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29211 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 26914 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 2297 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29211 # number of SCUpgradeReq misses -system.l2c.UpgradeReq_accesses::0 90515 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 5281 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 95796 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 90515 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 5281 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95796 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 427641 # number of Writeback hits -system.l2c.Writeback_hits::total 427641 # number of Writeback hits +system.l2c.ReadExReq_hits::0 1653 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1792 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.994139 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.994262 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 280370 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 24085 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304455 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2581832 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 142288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2724120 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1623623 # number of ReadReq hits +system.l2c.ReadReq_hits::1 136766 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1760389 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.371135 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.038809 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 958209 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5522 # number of ReadReq misses +system.l2c.ReadReq_misses::total 963731 # number of ReadReq misses +system.l2c.SCUpgradeReq_accesses::0 20901 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 1879 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22780 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_rate::0 0.999856 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.997871 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 20898 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 1875 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22773 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 64914 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 69266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.999815 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999311 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 64902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 4349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69251 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 450250 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 450250 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 450250 # number of Writeback hits +system.l2c.Writeback_hits::total 450250 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. +system.l2c.avg_refs 1.817381 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2863855 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 166512 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3030367 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits -system.l2c.demand_hits::1 136618 # number of demand (read+write) hits +system.l2c.demand_hits::0 1625276 # number of demand (read+write) hits +system.l2c.demand_hits::1 136905 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits +system.l2c.demand_hits::total 1762181 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.432487 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.177807 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses -system.l2c.demand_misses::1 29945 # number of demand (read+write) misses +system.l2c.demand_misses::0 1238579 # number of demand (read+write) misses +system.l2c.demand_misses::1 29607 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses +system.l2c.demand_misses::total 1268186 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -759,35 +768,35 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context -system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context -system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context -system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.144031 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.004095 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.343441 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9439.247714 # Average occupied blocks per context +system.l2c.occ_blocks::1 268.394267 # Average occupied blocks per context +system.l2c.occ_blocks::2 22507.731761 # Average occupied blocks per context +system.l2c.overall_accesses::0 2863855 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 166512 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3030367 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1623113 # number of overall hits -system.l2c.overall_hits::1 136618 # number of overall hits +system.l2c.overall_hits::0 1625276 # number of overall hits +system.l2c.overall_hits::1 136905 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1759731 # number of overall hits +system.l2c.overall_hits::total 1762181 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.432487 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.177807 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1240838 # number of overall misses -system.l2c.overall_misses::1 29945 # number of overall misses +system.l2c.overall_misses::0 1238579 # number of overall misses +system.l2c.overall_misses::1 29607 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 1270783 # number of overall misses +system.l2c.overall_misses::total 1268186 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -797,13 +806,13 @@ system.l2c.overall_mshr_miss_rate::total no_value # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1056803 # number of replacements -system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. +system.l2c.replacements 1055565 # number of replacements +system.l2c.sampled_refs 1090545 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use -system.l2c.total_refs 1952499 # Total number of references to valid blocks. +system.l2c.tagsinuse 32215.373742 # Cycle average of tags in use +system.l2c.total_refs 1981936 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123882 # number of writebacks +system.l2c.writebacks 123249 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c4ecb27ec..95ba28054 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -157,7 +158,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +178,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -303,7 +304,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index af78d2d19..88c4f9cc3 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:39:16 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:50 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7a54ae203..da0ed6f79 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3274924 # Simulator instruction rate (inst/s) -host_mem_usage 275440 # Number of bytes of host memory used -host_seconds 18.33 # Real time elapsed on the host -host_tick_rate 99783911231 # Simulator tick rate (ticks/s) +host_inst_rate 2897706 # Simulator instruction rate (inst/s) +host_mem_usage 291728 # Number of bytes of host memory used +host_seconds 20.72 # Real time elapsed on the host +host_tick_rate 88290469218 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -24,18 +24,18 @@ system.cpu.dcache.ReadReq_misses::0 1721705 # nu system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_hits::0 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111415 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22203 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22203 # number of StoreCondReq misses system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::0 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.060377 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 371472 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 371472 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -51,16 +51,16 @@ system.cpu.dcache.demand_avg_miss_latency::0 0 system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.133476 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -80,16 +80,16 @@ system.cpu.dcache.overall_avg_miss_latency::1 no_value system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13588884 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13560932 # number of overall hits +system.cpu.dcache.overall_hits::total 13588884 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.133476 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::0 2093177 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2121129 # number of overall misses +system.cpu.dcache.overall_misses::total 2093177 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -104,7 +104,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks 450979 # number of writebacks system.cpu.dtb.data_accesses 1020787 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_hits 16062925 # DTB hits @@ -395,33 +395,35 @@ system.iocache.warmup_cycle 1685780659017 # C system.iocache.writebacks 41512 # number of writebacks system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadExReq_hits::0 1965 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1965 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.993544 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302381 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302381 # number of ReadExReq misses system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses -system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses -system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1697753 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1697753 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361524 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 961318 # number of ReadReq misses +system.l2c.ReadReq_misses::total 961318 # number of ReadReq misses +system.l2c.SCUpgradeReq_accesses::0 22203 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22203 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses -system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::0 22203 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22203 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 67126 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 67126 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 428893 # number of Writeback hits -system.l2c.Writeback_hits::total 428893 # number of Writeback hits +system.l2c.UpgradeReq_misses::0 67126 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 67126 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 450979 # number of Writeback hits +system.l2c.Writeback_hits::total 450979 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. +system.l2c.avg_refs 1.759381 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -434,16 +436,16 @@ system.l2c.demand_avg_miss_latency::0 0 # av system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1699718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::total 1699718 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.426433 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::0 1263699 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::total 1263699 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -453,10 +455,10 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context -system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.occ_%::0 0.141683 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.342776 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9285.312813 # Average occupied blocks per context +system.l2c.occ_blocks::1 22464.151503 # Average occupied blocks per context system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses @@ -465,16 +467,16 @@ system.l2c.overall_avg_miss_latency::1 no_value # av system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::0 1699718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1696652 # number of overall hits +system.l2c.overall_hits::total 1699718 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.426433 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::0 1263699 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 1266765 # number of overall misses +system.l2c.overall_misses::total 1263699 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -483,13 +485,13 @@ system.l2c.overall_mshr_miss_rate::total no_value # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1050724 # number of replacements -system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. +system.l2c.replacements 1048986 # number of replacements +system.l2c.sampled_refs 1079842 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use -system.l2c.total_refs 1867269 # Total number of references to valid blocks. +system.l2c.tagsinuse 31749.464316 # Cycle average of tags in use +system.l2c.total_refs 1899854 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119147 # number of writebacks +system.l2c.writebacks 118452 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index d4b4f018c..425a86d16 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -258,7 +259,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -278,7 +279,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -404,7 +405,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 24b896c4e..079f41b2d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:43:55 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:18 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 591544000 -Exiting @ tick 1972135461000 because m5_exit instruction encountered +info: Launching CPU 1 @ 591240000 +Exiting @ tick 1967163347000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index c2f737377..eb5599859 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,157 +1,159 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1520606 # Simulator instruction rate (inst/s) -host_mem_usage 273632 # Number of bytes of host memory used -host_seconds 39.08 # Real time elapsed on the host -host_tick_rate 50467758461 # Simulator tick rate (ticks/s) +host_inst_rate 1510892 # Simulator instruction rate (inst/s) +host_mem_usage 289944 # Number of bytes of host memory used +host_seconds 40.42 # Real time elapsed on the host +host_tick_rate 48670449492 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59420593 # Number of instructions simulated -sim_seconds 1.972135 # Number of seconds simulated -sim_ticks 1972135461000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency +sim_insts 61066894 # Number of instructions simulated +sim_seconds 1.967163 # Number of seconds simulated +sim_ticks 1967163347000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses::0 150276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 150276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 11859.655689 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 8859.655689 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 136916 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 136916 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 158445000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.088903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 13360 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13360 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 118365000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.088903 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 13360 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 7279990 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7279990 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 26932.541490 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23932.489517 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6346809 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6346809 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 25132936000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.128184 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 933181 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 933181 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 22333344500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.128184 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 933181 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 149766 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 149766 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 42774.669320 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 39774.669320 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 132680 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132680 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 730848000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 17086 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 17086 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 679590000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.114085 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 17086 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 4822937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4822937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 54619.723929 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 51619.723929 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 4533446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4533446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 15811918500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.060024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 289491 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289491 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 14943445500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060024 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_misses 289491 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1351640000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.594836 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 12102927 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 12102927 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 33488.011912 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 30487.972244 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10880255 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10880255 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 40944854500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.101023 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 1222672 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1222672 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_latency 37276790000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.101023 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1222672 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.983612 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 503.609177 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.971951 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 497.638883 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 12102927 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14335823 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 12102927 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 33488.011912 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30487.972244 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::0 10880255 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12917865 # number of overall hits -system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10880255 # number of overall hits +system.cpu0.dcache.overall_miss_latency 40944854500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.101023 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::0 1222672 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::total 1222672 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_latency 37276790000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.101023 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1222672 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2235239000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1338610 # number of replacements -system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1168722 # number of replacements +system.cpu0.dcache.sampled_refs 1169234 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.609177 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403520 # number of writebacks +system.cpu0.dcache.tagsinuse 496.638883 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11218608 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 339648 # number of writebacks system.cpu0.dtb.data_accesses 719860 # DTB accesses system.cpu0.dtb.data_acv 289 # DTB access violations -system.cpu0.dtb.data_hits 14704826 # DTB hits +system.cpu0.dtb.data_hits 12394366 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -159,106 +161,106 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8664724 # DTB read hits +system.cpu0.dtb.read_hits 7418432 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6040102 # DTB write hits +system.cpu0.dtb.write_hits 4975934 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses::0 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_accesses::0 47254591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47254591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14914.060222 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 53248092 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53248092 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.016917 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 916324 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916324 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11912.744970 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 46572212 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46572212 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 10177041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.014440 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 682379 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 682379 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 8129007000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.014440 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses 682379 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 68.262978 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 47254591 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54164416 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.demand_accesses::total 47254591 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14914.060222 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 11912.744970 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 46572212 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53248092 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 46572212 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 10177041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.014440 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 682379 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 682379 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_latency 8129007000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.014440 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 682379 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.993443 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 508.642782 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 54164416 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.993449 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 508.646096 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 47254591 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54164416 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.overall_accesses::total 47254591 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14914.060222 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11912.744970 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 53248092 # number of overall hits +system.cpu0.icache.overall_hits::0 46572212 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 53248092 # number of overall hits -system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 46572212 # number of overall hits +system.cpu0.icache.overall_miss_latency 10177041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.014440 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 916324 # number of overall misses +system.cpu0.icache.overall_misses::0 682379 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 916324 # number of overall misses +system.cpu0.icache.overall_misses::total 682379 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_latency 8129007000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.014440 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 682379 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 915684 # number of replacements -system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 681735 # number of replacements +system.cpu0.icache.sampled_refs 682247 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.642782 # Cycle average of tags in use -system.cpu0.icache.total_refs 53248092 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.646096 # Cycle average of tags in use +system.cpu0.icache.total_refs 46572212 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 38669170000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles +system.cpu0.idle_fraction 0.943058 # Percentage of idle cycles system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 3953747 # ITB accesses +system.cpu0.itb.fetch_accesses 3572127 # ITB accesses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_hits 3949906 # ITB hits +system.cpu0.itb.fetch_hits 3568286 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -269,63 +271,63 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3868 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.13% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172068 91.52% 93.65% # number of callpals executed -system.cpu0.kern.callpal::rdps 6698 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rti 4713 2.51% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188012 # number of callpals executed +system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2975 2.03% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 131234 89.72% 92.16% # number of callpals executed +system.cpu0.kern.callpal::rdps 6694 4.58% 96.73% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.73% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::rti 4260 2.91% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.24% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 146277 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 72641 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1987 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104141 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178906 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96186500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 576952000 0.03% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5442500 0.00% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1972134703000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981154 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 161605 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6835 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 55380 40.11% 40.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1982 1.44% 41.64% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 455 0.33% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80115 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 138063 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54908 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1982 1.77% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 455 0.41% 51.35% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54453 48.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 111929 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909262510000 97.06% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 87868000 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 573921000 0.03% 97.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 337802000 0.02% 97.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56900501000 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1967162602000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991477 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679685 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good::kernel 1231 system.cpu0.kern.mode_good::user 1232 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6788 # number of protection mode switches system.cpu0.kern.mode_switch::user 1232 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.170098 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181349 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3804198000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1963346065000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3816535000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3869 # number of times the context was actually changed +system.cpu0.kern.swap_context 2976 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -357,154 +359,154 @@ system.cpu0.kern.syscall::132 2 0.89% 98.66% # nu system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 224 # number of syscalls executed -system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles -system.cpu0.numCycles 3944270922 # number of cpu cycles simulated -system.cpu0.num_insts 54155641 # Number of instructions executed -system.cpu0.num_refs 14946215 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses::0 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13303.501946 # average LoadLockedReq miss latency +system.cpu0.not_idle_fraction 0.056942 # Percentage of non-idle cycles +system.cpu0.numCycles 3934326694 # number of cpu cycles simulated +system.cpu0.num_insts 47245816 # Number of instructions executed +system.cpu0.num_refs 12627213 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses::0 61432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10283.624203 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 11306 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11306 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.083347 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 1028 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1028 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7283.624203 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 51863 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51863 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 98404000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.155766 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 9569 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9569 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 69697000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155766 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 9569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2468175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2468175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 13829.556740 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10829.528932 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 984803 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 984803 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.035021 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 35740 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35740 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2342312 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2342312 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 1740629500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.050994 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 125863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 125863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 1363037000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.050994 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses 125863 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 60921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 60921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35881.530265 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 2422 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2422 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32881.530265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 47407 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 47407 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 484903000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.221828 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 13514 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 13514 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 444361000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.221828 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 13514 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1805806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1805806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 52324.342254 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 49324.342254 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 623656 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 26352 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 26352 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1713103 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1713103 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 4850623500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.051336 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 92703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 4572514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.051336 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_misses 92703 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 413889500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 23.182705 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 4273981 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1670551 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 4273981 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 30156.808470 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 27156.792456 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 4055415 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1608459 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 4055415 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6591253000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.051139 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 218566 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 218566 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_latency 5935551500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.051139 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 218566 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 388.878897 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.916301 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 469.145893 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 4273981 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1670551 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 4273981 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 30156.808470 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 27156.792456 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::0 4055415 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1608459 # number of overall hits -system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 4055415 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6591253000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.051139 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 62092 # number of overall misses +system.cpu1.dcache.overall_misses::0 218566 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 62092 # number of overall misses +system.cpu1.dcache.overall_misses::total 218566 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_latency 5935551500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.051139 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 218566 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 426415500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 53724 # number of replacements -system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 180512 # number of replacements +system.cpu1.dcache.sampled_refs 180909 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.878897 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26831 # number of writebacks +system.cpu1.dcache.tagsinuse 469.145893 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4193960 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1949703501000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 96724 # number of writebacks system.cpu1.dtb.data_accesses 302878 # DTB accesses system.cpu1.dtb.data_acv 84 # DTB access violations -system.cpu1.dtb.data_hits 1693851 # DTB hits +system.cpu1.dtb.data_hits 4382020 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -512,106 +514,106 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1029710 # DTB read hits +system.cpu1.dtb.read_hits 2517470 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 664141 # DTB write hits +system.cpu1.dtb.write_hits 1864550 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses::0 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_accesses::0 13824268 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13824268 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14182.361205 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 5180706 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5180706 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.016597 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 87436 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87436 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11182.239180 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 13488270 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13488270 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 4765245000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.024305 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 335998 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 335998 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 3757210000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.024305 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses 335998 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 40.147245 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 13824268 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5268142 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.demand_accesses::total 13824268 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14182.361205 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11182.239180 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 13488270 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5180706 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 13488270 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 4765245000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.024305 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 335998 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 335998 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_latency 3757210000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.024305 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 335998 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.819152 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 419.405627 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 5268142 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.872600 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 446.771254 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 13824268 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5268142 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.overall_accesses::total 13824268 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14182.361205 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11182.239180 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 5180706 # number of overall hits +system.cpu1.icache.overall_hits::0 13488270 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 5180706 # number of overall hits -system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 13488270 # number of overall hits +system.cpu1.icache.overall_miss_latency 4765245000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.024305 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 87436 # number of overall misses +system.cpu1.icache.overall_misses::0 335998 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 87436 # number of overall misses +system.cpu1.icache.overall_misses::total 335998 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_latency 3757210000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.024305 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 335998 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 86896 # number of replacements -system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 335458 # number of replacements +system.cpu1.icache.sampled_refs 335970 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.405627 # Cycle average of tags in use -system.cpu1.icache.total_refs 5180706 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 446.771254 # Cycle average of tags in use +system.cpu1.icache.total_refs 13488270 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1962800602000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.idle_fraction 0.984741 # Percentage of idle cycles system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 1397517 # ITB accesses +system.cpu1.itb.fetch_accesses 1913285 # ITB accesses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_hits 1396271 # ITB hits +system.cpu1.itb.fetch_hits 1912039 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -622,59 +624,59 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.03% 1.30% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24144 81.84% 83.16% # number of callpals executed -system.cpu1.kern.callpal::rdps 2172 7.36% 90.52% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.53% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.55% # number of callpals executed -system.cpu1.kern.callpal::rti 2594 8.79% 99.35% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 455 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2159 2.85% 3.46% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.01% 3.47% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed +system.cpu1.kern.callpal::swpipl 66683 88.18% 91.66% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 2.87% 94.53% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.53% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.53% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::rti 3936 5.20% 99.74% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.21% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29503 # number of callpals executed +system.cpu1.kern.callpal::total 75623 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 9173 31.84% 31.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1980 6.87% 38.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17566 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28810 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20310 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 511194500 0.03% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999128 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 82618 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2771 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 28203 38.56% 38.56% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1977 2.70% 41.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 540 0.74% 42.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 42416 58.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 73136 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 27298 48.25% 48.25% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1977 3.49% 51.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 540 0.95% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26759 47.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 56574 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1915291540500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 515904000 0.03% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 422495500 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50571037000 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1966800977000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967911 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516566 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 532 -system.cpu1.kern.mode_good::user 516 -system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch::kernel 880 # number of protection mode switches -system.cpu1.kern.mode_switch::user 516 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2081 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.604545 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.630870 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 981 +system.cpu1.kern.mode_good::user 517 +system.cpu1.kern.mode_good::idle 464 +system.cpu1.kern.mode_switch::kernel 2246 # number of protection mode switches +system.cpu1.kern.mode_switch::user 517 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2954 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.436776 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.612234 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1703543000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.157075 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.593852 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 23054472000 1.17% 1.17% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1704524000 0.09% 1.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941246244000 98.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2160 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -697,10 +699,10 @@ system.cpu1.kern.syscall::92 2 1.96% 97.06% # nu system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 102 # number of syscalls executed -system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles -system.cpu1.numCycles 3943367734 # number of cpu cycles simulated -system.cpu1.num_insts 5264952 # Number of instructions executed -system.cpu1.num_refs 1703740 # Number of memory references +system.cpu1.not_idle_fraction 0.015259 # Percentage of non-idle cycles +system.cpu1.numCycles 3933602014 # number of cpu cycles simulated +system.cpu1.num_insts 13821078 # Number of instructions executed +system.cpu1.num_refs 4410345 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -713,282 +715,290 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137872.733106 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85869.242491 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5728887806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568038764 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.774548 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64487836 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137778.382879 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5748940804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579043762 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.036380 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.582075 # Average occupied blocks per context +system.iocache.occ_%::1 0.036248 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.579966 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137778.382879 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles +system.iocache.overall_miss_latency 5748940804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579043762 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41698 # number of replacements -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.replacements 41694 # number of replacements +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.582075 # Cycle average of tags in use +system.iocache.tagsinuse 0.579966 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1759378217000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 285538 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55877.476903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 749912.718556 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 236787 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 61172 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 297959 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 65502.824330 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 252326.309748 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 285538 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 21276 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 306814 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.074512 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 14.420662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.055004 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 1864 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 187 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2051 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15388120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992128 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.996943 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 234923 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 60985 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 295908 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 11837224000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.249680 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4.837311 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1969770 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 120535 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2090305 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52549.257150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 5128541.212316 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 295908 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1614705 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 454179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2068884 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52561.218952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5017624.332810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.414894 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1665469 # number of ReadReq hits -system.l2c.ReadReq_hits::1 117417 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1782886 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.154486 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.025868 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304301 # number of ReadReq misses -system.l2c.ReadReq_misses::1 3118 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307419 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1310657 # number of ReadReq hits +system.l2c.ReadReq_hits::1 450994 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1761651 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15981133500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.188299 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.007013 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304048 # number of ReadReq misses +system.l2c.ReadReq_misses::1 3185 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307233 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12293883000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.190264 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.676432 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 27944 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 1988 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29932 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 55471.228171 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 779722.334004 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 307221 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 802535000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 12669 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 8188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 20857 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 78597.820938 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 121582.804104 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.405452 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1550088000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.028004 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 995520000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.999763 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 27944 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 1988 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29932 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1197352000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.071142 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.056338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 12666 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 8188 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 20854 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 834244000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.646065 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.546898 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 29932 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 92926 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4380 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 97306 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52795.955922 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 1120118.036530 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 20854 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 46404 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 25015 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 71419 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 74757.458826 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 138647.409244 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.114731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 4906117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 92926 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 4380 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 97306 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3892835000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.047134 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 22.215982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40008.977591 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 3467849000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.999655 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999880 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 46388 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 25012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 71400 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2856641000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.538660 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.854287 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 97306 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 71400 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430351 # number of Writeback hits -system.l2c.Writeback_hits::total 430351 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1594965500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 436372 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 436372 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 436372 # number of Writeback hits +system.l2c.Writeback_hits::total 436372 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. +system.l2c.avg_refs 4.549954 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1851492 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 515351 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.demand_accesses::total 2366843 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 58202.117554 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 488846.088515 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency -system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits -system.l2c.demand_hits::1 117417 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency +system.l2c.demand_hits::0 1312521 # number of demand (read+write) hits +system.l2c.demand_hits::1 451181 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses +system.l2c.demand_hits::total 1763702 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31369253500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.291101 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.124517 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 589839 # number of demand (read+write) misses -system.l2c.demand_misses::1 24394 # number of demand (read+write) misses +system.l2c.demand_misses::0 538971 # number of demand (read+write) misses +system.l2c.demand_misses::1 64170 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 614233 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 603141 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24131107000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.325753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.170327 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 603129 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context -system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context -system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context -system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.162138 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.003912 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.340573 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10625.898715 # Average occupied blocks per context +system.l2c.occ_blocks::1 256.359763 # Average occupied blocks per context +system.l2c.occ_blocks::2 22319.780586 # Average occupied blocks per context +system.l2c.overall_accesses::0 1851492 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 515351 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.overall_accesses::total 2366843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 58202.117554 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 488846.088515 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1665469 # number of overall hits -system.l2c.overall_hits::1 117417 # number of overall hits +system.l2c.overall_hits::0 1312521 # number of overall hits +system.l2c.overall_hits::1 451181 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1782886 # number of overall hits -system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses +system.l2c.overall_hits::total 1763702 # number of overall hits +system.l2c.overall_miss_latency 31369253500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.291101 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.124517 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 589839 # number of overall misses -system.l2c.overall_misses::1 24394 # number of overall misses +system.l2c.overall_misses::0 538971 # number of overall misses +system.l2c.overall_misses::1 64170 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 614233 # number of overall misses -system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 603141 # number of overall misses +system.l2c.overall_mshr_hits 12 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24131107000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.325753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.170327 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 603129 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2397500500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 399005 # number of replacements -system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. +system.l2c.replacements 398396 # number of replacements +system.l2c.sampled_refs 431420 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use -system.l2c.total_refs 1961635 # Total number of references to valid blocks. -system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123162 # number of writebacks +system.l2c.tagsinuse 33202.039064 # Cycle average of tags in use +system.l2c.total_refs 1962941 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10911264000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 122806 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 38041459e..14a4f1725 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -154,7 +155,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -174,7 +175,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -300,7 +301,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 7b8726b2e..8049df732 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:44:55 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:16 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1930164593000 because m5_exit instruction encountered +Exiting @ tick 1927951878000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index f93fce19a..3b140faa7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1511189 # Simulator instruction rate (inst/s) -host_mem_usage 272256 # Number of bytes of host memory used -host_seconds 37.19 # Real time elapsed on the host -host_tick_rate 51895589412 # Simulator tick rate (ticks/s) +host_inst_rate 1563603 # Simulator instruction rate (inst/s) +host_mem_usage 288804 # Number of bytes of host memory used +host_seconds 35.93 # Real time elapsed on the host +host_tick_rate 53658174093 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56205703 # Number of instructions simulated -sim_seconds 1.930165 # Number of seconds simulated -sim_ticks 1930164593000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency +sim_insts 56180319 # Number of instructions simulated +sim_seconds 1.927952 # Number of seconds simulated +sim_ticks 1927951878000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14335.708080 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11335.708080 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 247506000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086164 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 195711000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086164 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17265 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 25418.459915 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22418.417380 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27190304500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.120414 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 23981138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120414 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 1069707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.626718 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.626718 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1246775000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111672 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1179989000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.111672 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 22262 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 55757.232436 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52757.232436 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20664857000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.060197 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 19552991000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.060197 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 370622 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1200971000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097149 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15040372 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15040372 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13600043 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13600043 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 47855161500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.095764 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 43534129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095764 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1440329 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.984152 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15040372 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15040372 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13577961 # number of overall hits +system.cpu.dcache.overall_hits::0 13600043 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13577961 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13600043 # number of overall hits +system.cpu.dcache.overall_miss_latency 47855161500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.095764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1471029 # number of overall misses +system.cpu.dcache.overall_misses::0 1440329 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1471029 # number of overall misses +system.cpu.dcache.overall_misses::total 1440329 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 43534129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095764 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1440329 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2063734000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1391606 # number of replacements -system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1390845 # number of replacements +system.cpu.dcache.sampled_refs 1391357 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use -system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430459 # number of writebacks +system.cpu.dcache.tagsinuse 511.984152 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048739 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 452168 # number of writebacks system.cpu.dtb.data_accesses 1020784 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_hits 15429793 # DTB hits +system.cpu.dtb.data_hits 15421062 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -159,106 +159,106 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9069700 # DTB read hits +system.cpu.dtb.read_hits 9064565 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6360093 # DTB write hits +system.cpu.dtb.write_hits 6356497 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14699.293599 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.559265 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13681735000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.016564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10888726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016564 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 930775 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.381568 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 56192153 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.demand_accesses::total 56192153 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 55261378 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 55261378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13681735000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.016564 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 930775 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 930775 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 10888726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.016564 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 930775 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.993310 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 508.574724 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 56192153 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.overall_accesses::total 56192153 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 55286436 # number of overall hits +system.cpu.icache.overall_hits::0 55261378 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 55286436 # number of overall hits -system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 55261378 # number of overall hits +system.cpu.icache.overall_miss_latency 13681735000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.016564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 931101 # number of overall misses +system.cpu.icache.overall_misses::0 930775 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 931101 # number of overall misses +system.cpu.icache.overall_misses::total 930775 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 10888726500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.016564 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 930775 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 930429 # number of replacements -system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930104 # number of replacements +system.cpu.icache.sampled_refs 930615 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use -system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.574724 # Cycle average of tags in use +system.cpu.icache.total_refs 55261378 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 38310365000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.idle_fraction 0.930310 # Percentage of idle cycles system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4982987 # ITB accesses +system.cpu.itb.fetch_accesses 4982567 # ITB accesses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_hits 4977977 # ITB hits +system.cpu.itb.fetch_hits 4977557 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -272,55 +272,55 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6844 3.54% 96.95% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpipl 176202 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6843 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5167 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193221 # number of callpals executed +system.cpu.kern.callpal::total 193169 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212271 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6373 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74979 40.87% 40.87% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1942 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106391 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183443 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73612 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1942 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73612 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149297 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1865248449500 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 84324500 0.00% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 564095000 0.03% 96.78% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 62054251000 3.22% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1927951120000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981768 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.ipl_used::31 0.691901 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1914 system.cpu.kern.mode_good::user 1744 -system.cpu.kern.mode_good::idle 167 -system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch::kernel 5914 # number of protection mode switches system.cpu.kern.mode_switch::user 1744 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323639 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4172 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.404746 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 47869140000 2.48% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5515150000 0.29% 2.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874566828000 97.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -352,10 +352,10 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles -system.cpu.numCycles 3860329186 # number of cpu cycles simulated -system.cpu.num_insts 56205703 # Number of instructions executed -system.cpu.num_refs 15677891 # Number of memory references +system.cpu.not_idle_fraction 0.069690 # Percentage of non-idle cycles +system.cpu.numCycles 3855903756 # number of cpu cycles simulated +system.cpu.num_insts 56180319 # Number of instructions executed +system.cpu.num_refs 15669216 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -386,37 +386,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137846.765643 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85843.300347 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727808806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566960816 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.192131 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64561892 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747747804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -424,7 +424,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577903814 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -432,20 +432,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context +system.iocache.occ_%::1 0.084569 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.353112 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747747804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -453,7 +453,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577903814 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -463,151 +463,153 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353399 # Cycle average of tags in use +system.iocache.tagsinuse 1.353112 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1760339542000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52003.580327 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.580327 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 2179 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2179 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15715846000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992841 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302207 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302207 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12089362000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.992841 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 302207 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52016.477812 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.459857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1711407 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1711407 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15933739500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.151815 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 306321 # number of ReadReq misses +system.l2c.ReadReq_misses::total 306321 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12257882000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.151815 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses 306321 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.366085 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.626718 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.366085 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1560339000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.626718 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1157727000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1200291000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_misses::0 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 890583000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 30004 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52001.013313 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 22262 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52000.030195 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.391669 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5003485500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40007.095839 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 3444274000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3849375000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2649910000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 96219 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 66236 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430459 # number of Writeback hits -system.l2c.Writeback_hits::total 430459 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085051000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 452168 # number of Writeback hits +system.l2c.Writeback_hits::total 452168 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. +system.l2c.avg_refs 4.517115 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2322114 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.demand_accesses::total 2322114 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency -system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency +system.l2c.demand_hits::0 1713586 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses +system.l2c.demand_hits::total 1713586 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31649585500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.262058 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 612229 # number of demand (read+write) misses +system.l2c.demand_misses::0 608528 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 612229 # number of demand (read+write) misses +system.l2c.demand_misses::total 608528 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24347244000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.262058 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 608528 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context -system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context -system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.156745 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.334961 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10272.459916 # Average occupied blocks per context +system.l2c.occ_blocks::1 21951.974033 # Average occupied blocks per context +system.l2c.overall_accesses::0 2322114 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.overall_accesses::total 2322114 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1710971 # number of overall hits +system.l2c.overall_hits::0 1713586 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1710971 # number of overall hits -system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses +system.l2c.overall_hits::total 1713586 # number of overall hits +system.l2c.overall_miss_latency 31649585500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.262058 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 612229 # number of overall misses +system.l2c.overall_misses::0 608528 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 612229 # number of overall misses +system.l2c.overall_misses::total 608528 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24347244000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.262058 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 608528 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857724000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 394928 # number of replacements -system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. +system.l2c.replacements 393234 # number of replacements +system.l2c.sampled_refs 424575 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use -system.l2c.total_refs 1889545 # Total number of references to valid blocks. -system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119060 # number of writebacks +system.l2c.tagsinuse 32224.433949 # Cycle average of tags in use +system.l2c.total_refs 1917854 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6967096000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 118566 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index f8aa4e39a..380aa38da 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -153,7 +153,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index 3a00a516f..2cf640280 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:33:34 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing +M5 compiled Aug 26 2010 19:15:13 +M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix +M5 started Aug 26 2010 19:20:56 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries 49508 bytes wasted ->Exiting @ tick 737389000 because a thread reached the max instruction count +>Exiting @ tick 727929000 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index fb5a17baa..43dab4e5c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409192 # Simulator instruction rate (inst/s) -host_mem_usage 189184 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 2076450214 # Simulator tick rate (ticks/s) +host_inst_rate 1184343 # Simulator instruction rate (inst/s) +host_mem_usage 203180 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host +host_tick_rate 1723169900 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000737 # Number of seconds simulated -sim_ticks 737389000 # Number of ticks simulated +sim_seconds 0.000728 # Number of seconds simulated +sim_ticks 727929000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 315 # nu system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses -system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180149 # number of overall hits -system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses -system.cpu.dcache.overall_misses 626 # number of overall misses +system.cpu.dcache.overall_hits 180321 # number of overall hits +system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 403 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use +system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 718 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 857 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 857 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1474778 # number of cpu cycles simulated +system.cpu.numCycles 1455858 # number of cpu cycles simulated system.cpu.num_insts 500001 # Number of instructions executed system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 0a51ea28f..f95ff0355 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -115,7 +115,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -227,7 +227,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -339,7 +339,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -451,7 +451,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 1abe4a9de..75c83d350 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -5,3 +5,7 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 6a26281d0..97f8bb1e7 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:22:16 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp +M5 compiled Aug 26 2010 19:15:13 +M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix +M5 started Aug 26 2010 19:20:56 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 94c888d5d..390fcd6e5 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1651065 # Simulator instruction rate (inst/s) -host_mem_usage 1114084 # Number of bytes of host memory used -host_seconds 1.21 # Real time elapsed on the host -host_tick_rate 206342663 # Simulator tick rate (ticks/s) +host_inst_rate 3552670 # Simulator instruction rate (inst/s) +host_mem_usage 1128260 # Number of bytes of host memory used +host_seconds 0.56 # Real time elapsed on the host +host_tick_rate 443935332 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -13,9 +13,9 @@ system.cpu0.dcache.ReadReq_hits 124111 # nu system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. @@ -27,10 +27,10 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -44,10 +44,10 @@ system.cpu0.dcache.overall_accesses 180775 # nu system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_hits 180312 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 463 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -153,9 +153,9 @@ system.cpu1.dcache.ReadReq_hits 124111 # nu system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. @@ -167,10 +167,10 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -184,10 +184,10 @@ system.cpu1.dcache.overall_accesses 180775 # nu system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180140 # number of overall hits +system.cpu1.dcache.overall_hits 180312 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 463 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -293,9 +293,9 @@ system.cpu2.dcache.ReadReq_hits 124111 # nu system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. @@ -307,10 +307,10 @@ system.cpu2.dcache.cache_copies 0 # nu system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -324,10 +324,10 @@ system.cpu2.dcache.overall_accesses 180775 # nu system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_hits 180312 # number of overall hits system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 463 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -433,9 +433,9 @@ system.cpu3.dcache.ReadReq_hits 124111 # nu system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. @@ -447,10 +447,10 @@ system.cpu3.dcache.cache_copies 0 # nu system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -464,10 +464,10 @@ system.cpu3.dcache.overall_accesses 180775 # nu system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180140 # number of overall hits +system.cpu3.dcache.overall_hits 180312 # number of overall hits system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 463 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -603,28 +603,13 @@ system.l2c.ReadReq_misses::1 718 # nu system.l2c.ReadReq_misses::2 718 # number of ReadReq misses system.l2c.ReadReq_misses::3 718 # number of ReadReq misses system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -668,16 +653,16 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.005715 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005715 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005715 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.005715 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000475 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 374.558766 # Average occupied blocks per context -system.l2c.occ_blocks::1 374.558766 # Average occupied blocks per context -system.l2c.occ_blocks::2 374.558766 # Average occupied blocks per context -system.l2c.occ_blocks::3 374.558766 # Average occupied blocks per context -system.l2c.occ_blocks::4 31.139534 # Average occupied blocks per context +system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses @@ -717,10 +702,10 @@ system.l2c.overall_mshr_misses 0 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use -system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use +system.l2c.total_refs 332 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 786aa64a8..a23113a37 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -112,7 +112,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -221,7 +221,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -330,7 +330,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -439,7 +439,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index eb2ca2ce0..7e841f3da 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:37:40 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:37:50 -M5 executing on phenom +M5 compiled Aug 26 2010 19:15:13 +M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix +M5 started Aug 26 2010 19:20:56 +M5 executing on zizzer command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,4 +20,4 @@ main dictionary has 1245 entries 49508 bytes wasted 49508 bytes wasted 49508 bytes wasted ->>>>Exiting @ tick 738387000 because a thread reached the max instruction count +>>>>Exiting @ tick 728920000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 78c1b80b2..cc069962f 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1240283 # Simulator instruction rate (inst/s) -host_mem_usage 197852 # Number of bytes of host memory used -host_seconds 1.61 # Real time elapsed on the host -host_tick_rate 457858198 # Simulator tick rate (ticks/s) +host_inst_rate 1077320 # Simulator instruction rate (inst/s) +host_mem_usage 210756 # Number of bytes of host memory used +host_seconds 1.86 # Real time elapsed on the host +host_tick_rate 392590905 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1999941 # Number of instructions simulated -sim_seconds 0.000738 # Number of seconds simulated -sim_ticks 738387000 # Number of ticks simulated +sim_insts 1999954 # Number of instructions simulated +sim_seconds 0.000729 # Number of seconds simulated +sim_ticks 728920000 # Number of ticks simulated system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 # system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context +system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180140 # number of overall hits -system.cpu0.dcache.overall_miss_latency 35212000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_hits 180312 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 463 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 61 # number of replacements system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 29 # number of writebacks @@ -90,13 +90,13 @@ system.cpu0.dtb.write_acv 0 # DT system.cpu0.dtb.write_hits 56340 # DTB write hits system.cpu0.dtb.write_misses 10 # DTB write misses system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -108,31 +108,31 @@ system.cpu0.icache.blocked_cycles::no_mshrs 0 # system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.421796 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 215.959580 # Average occupied blocks per context +system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 499557 # number of overall hits -system.cpu0.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu0.icache.overall_misses 463 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,7 +140,7 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0 system.cpu0.icache.replacements 152 # number of replacements system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks @@ -162,135 +162,135 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 1476774 # number of cpu cycles simulated +system.cpu0.numCycles 1457840 # number of cpu cycles simulated system.cpu0.num_insts 500001 # Number of instructions executed system.cpu0.num_refs 182222 # Number of memory references system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 124109 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180772 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180137 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 180772 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180137 # number of overall hits -system.cpu1.dcache.overall_miss_latency 35229000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_hits 180311 # number of overall hits +system.cpu1.dcache.overall_miss_latency 25588000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 463 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 61 # number of replacements system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 272.916356 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.data_accesses 180790 # DTB accesses +system.cpu1.dtb.data_accesses 180792 # DTB accesses system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_hits 180772 # DTB hits +system.cpu1.dtb.data_hits 180774 # DTB hits system.cpu1.dtb.data_misses 18 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 124441 # DTB read accesses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124433 # DTB read hits +system.cpu1.dtb.read_hits 124435 # DTB read hits system.cpu1.dtb.read_misses 8 # DTB read misses system.cpu1.dtb.write_accesses 56349 # DTB write accesses system.cpu1.dtb.write_acv 0 # DTB write access violations system.cpu1.dtb.write_hits 56339 # DTB write hits system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 499540 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_accesses 500012 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499549 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23473000 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 22084000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 500003 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency -system.cpu1.icache.demand_hits 499540 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_accesses 500012 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50697.624190 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499549 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23473000 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 22084000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.421787 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 215.955045 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 500003 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499540 # number of overall hits -system.cpu1.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu1.icache.overall_hits 499549 # number of overall hits +system.cpu1.icache.overall_miss_latency 23473000 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu1.icache.overall_misses 463 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 22084000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -298,8 +298,8 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0 system.cpu1.icache.replacements 152 # number of replacements system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 215.955045 # Cycle average of tags in use -system.cpu1.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use +system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0 # Percentage of idle cycles @@ -307,9 +307,9 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 500016 # ITB accesses +system.cpu1.itb.fetch_accesses 500025 # ITB accesses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_hits 500003 # ITB hits +system.cpu1.itb.fetch_hits 500012 # ITB hits system.cpu1.itb.fetch_misses 13 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -320,135 +320,135 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.numCycles 1476774 # number of cpu cycles simulated -system.cpu1.num_insts 499984 # Number of instructions executed -system.cpu1.num_refs 182219 # Number of memory references +system.cpu1.numCycles 1457840 # number of cpu cycles simulated +system.cpu1.num_insts 499993 # Number of instructions executed +system.cpu1.num_refs 182221 # Number of memory references system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 124108 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180771 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180136 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_miss_latency 24202000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 180771 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180136 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35230000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_hits 180309 # number of overall hits +system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 463 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_miss_latency 24202000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 61 # number of replacements system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 272.914158 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.data_accesses 180789 # DTB accesses +system.cpu2.dtb.data_accesses 180790 # DTB accesses system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_hits 180771 # DTB hits +system.cpu2.dtb.data_hits 180772 # DTB hits system.cpu2.dtb.data_misses 18 # DTB misses system.cpu2.dtb.fetch_accesses 0 # ITB accesses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.read_accesses 124440 # DTB read accesses +system.cpu2.dtb.read_accesses 124441 # DTB read accesses system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124432 # DTB read hits +system.cpu2.dtb.read_hits 124433 # DTB read hits system.cpu2.dtb.read_misses 8 # DTB read misses system.cpu2.dtb.write_accesses 56349 # DTB write accesses system.cpu2.dtb.write_acv 0 # DTB write access violations system.cpu2.dtb.write_hits 56339 # DTB write hits system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 499537 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency -system.cpu2.icache.demand_hits 499537 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.421784 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 215.953225 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499537 # number of overall hits -system.cpu2.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu2.icache.overall_hits 499538 # number of overall hits +system.cpu2.icache.overall_miss_latency 23483000 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu2.icache.overall_misses 463 # number of overall misses system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -456,8 +456,8 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0 system.cpu2.icache.replacements 152 # number of replacements system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 215.953225 # Cycle average of tags in use -system.cpu2.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use +system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks system.cpu2.idle_fraction 0 # Percentage of idle cycles @@ -465,9 +465,9 @@ system.cpu2.itb.data_accesses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_hits 0 # DTB hits system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.fetch_accesses 500013 # ITB accesses +system.cpu2.itb.fetch_accesses 500014 # ITB accesses system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_hits 500000 # ITB hits +system.cpu2.itb.fetch_hits 500001 # ITB hits system.cpu2.itb.fetch_misses 13 # ITB misses system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -478,14 +478,14 @@ system.cpu2.itb.write_acv 0 # DT system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 1476774 # number of cpu cycles simulated -system.cpu2.num_insts 499981 # Number of instructions executed +system.cpu2.numCycles 1457840 # number of cpu cycles simulated +system.cpu2.num_insts 499982 # Number of instructions executed system.cpu2.num_refs 182218 # Number of memory references system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits 124107 # number of ReadReq hits system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses @@ -493,120 +493,120 @@ system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180768 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180133 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_accesses 180770 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180307 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 180768 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180133 # number of overall hits -system.cpu3.dcache.overall_miss_latency 35220000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_hits 180307 # number of overall hits +system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 463 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 61 # number of replacements system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 272.910830 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.data_accesses 180786 # DTB accesses +system.cpu3.dtb.data_accesses 180788 # DTB accesses system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_hits 180768 # DTB hits +system.cpu3.dtb.data_hits 180770 # DTB hits system.cpu3.dtb.data_misses 18 # DTB misses system.cpu3.dtb.fetch_accesses 0 # ITB accesses system.cpu3.dtb.fetch_acv 0 # ITB acv system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.read_accesses 124437 # DTB read accesses +system.cpu3.dtb.read_accesses 124439 # DTB read accesses system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124429 # DTB read hits +system.cpu3.dtb.read_hits 124431 # DTB read hits system.cpu3.dtb.read_misses 8 # DTB read misses system.cpu3.dtb.write_accesses 56349 # DTB write accesses system.cpu3.dtb.write_acv 0 # DTB write access violations system.cpu3.dtb.write_hits 56339 # DTB write hits system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 499531 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 499994 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency -system.cpu3.icache.demand_hits 499531 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.421779 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 215.951034 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 499994 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499531 # number of overall hits -system.cpu3.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu3.icache.overall_hits 499534 # number of overall hits +system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_misses 463 # number of overall misses system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -614,8 +614,8 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0 system.cpu3.icache.replacements 152 # number of replacements system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 215.951034 # Cycle average of tags in use -system.cpu3.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use +system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks system.cpu3.idle_fraction 0 # Percentage of idle cycles @@ -623,9 +623,9 @@ system.cpu3.itb.data_accesses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_hits 0 # DTB hits system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.fetch_accesses 500007 # ITB accesses +system.cpu3.itb.fetch_accesses 500010 # ITB accesses system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_hits 499994 # ITB hits +system.cpu3.itb.fetch_hits 499997 # ITB hits system.cpu3.itb.fetch_misses 13 # ITB misses system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.read_acv 0 # DTB read access violations @@ -636,22 +636,22 @@ system.cpu3.itb.write_acv 0 # DT system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.numCycles 1476774 # number of cpu cycles simulated -system.cpu3.num_insts 499975 # Number of instructions executed -system.cpu3.num_refs 182214 # Number of memory references +system.cpu3.numCycles 1457840 # number of cpu cycles simulated +system.cpu3.num_insts 499978 # Number of instructions executed +system.cpu3.num_refs 182216 # Number of memory references system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 208035.971223 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 208035.971223 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 208035.971223 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 208035.971223 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 832143.884892 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses @@ -662,7 +662,7 @@ system.l2c.ReadExReq_misses::1 139 # nu system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses @@ -674,18 +674,18 @@ system.l2c.ReadReq_accesses::1 787 # nu system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 208032.033426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 208032.033426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 208032.033426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 208032.033426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 832128.133705 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency system.l2c.ReadReq_hits::0 69 # number of ReadReq hits system.l2c.ReadReq_hits::1 69 # number of ReadReq hits system.l2c.ReadReq_hits::2 69 # number of ReadReq hits system.l2c.ReadReq_hits::3 69 # number of ReadReq hits system.l2c.ReadReq_hits::total 276 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses @@ -696,49 +696,20 @@ system.l2c.ReadReq_misses::1 718 # nu system.l2c.ReadReq_misses::2 718 # number of ReadReq misses system.l2c.ReadReq_misses::3 718 # number of ReadReq misses system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 208005.813953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 208005.813953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 208005.813953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 208005.813953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 832023.255814 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 4 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 4 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 4 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 16 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -749,18 +720,18 @@ system.l2c.demand_accesses::1 926 # nu system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 208032.672112 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 208032.672112 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 208032.672112 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 208032.672112 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 832130.688448 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency system.l2c.demand_hits::0 69 # number of demand (read+write) hits system.l2c.demand_hits::1 69 # number of demand (read+write) hits system.l2c.demand_hits::2 69 # number of demand (read+write) hits system.l2c.demand_hits::3 69 # number of demand (read+write) hits system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses @@ -772,7 +743,7 @@ system.l2c.demand_misses::2 857 # nu system.l2c.demand_misses::3 857 # number of demand (read+write) misses system.l2c.demand_misses::total 3428 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses @@ -782,34 +753,34 @@ system.l2c.demand_mshr_misses 3428 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.005650 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005650 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005650 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.005650 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000464 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 370.305065 # Average occupied blocks per context -system.l2c.occ_blocks::1 370.297695 # Average occupied blocks per context -system.l2c.occ_blocks::2 370.294638 # Average occupied blocks per context -system.l2c.occ_blocks::3 370.290796 # Average occupied blocks per context -system.l2c.occ_blocks::4 30.383926 # Average occupied blocks per context +system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context +system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context +system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context +system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context +system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 208032.672112 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 208032.672112 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 208032.672112 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 208032.672112 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 832130.688448 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 69 # number of overall hits system.l2c.overall_hits::1 69 # number of overall hits system.l2c.overall_hits::2 69 # number of overall hits system.l2c.overall_hits::3 69 # number of overall hits system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.overall_miss_latency 178284000 # number of overall miss cycles +system.l2c.overall_miss_latency 178290000 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses @@ -821,7 +792,7 @@ system.l2c.overall_misses::2 857 # nu system.l2c.overall_misses::3 857 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses @@ -831,10 +802,10 @@ system.l2c.overall_mshr_misses 3428 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use -system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use +system.l2c.total_refs 332 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index fe6b6401b..98bb2c9ad 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:40:18 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:40:33 -M5 executing on phenom +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:47 +M5 executing on zizzer command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -84,4 +86,4 @@ Iteration 9 completed [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 217002500 because target called exit() +Exiting @ tick 216428500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 68fb0ebc9..2b69b1c05 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 52624 # Simulator instruction rate (inst/s) -host_mem_usage 204896 # Number of bytes of host memory used -host_seconds 8.25 # Real time elapsed on the host -host_tick_rate 26298944 # Simulator tick rate (ticks/s) +host_inst_rate 29197 # Simulator instruction rate (inst/s) +host_mem_usage 217900 # Number of bytes of host memory used +host_seconds 14.87 # Real time elapsed on the host +host_tick_rate 14552660 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 434213 # Number of instructions simulated -sim_seconds 0.000217 # Number of seconds simulated -sim_ticks 217002500 # Number of ticks simulated +sim_seconds 0.000216 # Number of seconds simulated +sim_ticks 216428500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 68672 # Number of BTB lookups +system.cpu0.BPredUnit.BTBLookups 68668 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 70853 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 70853 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 70848 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 70848 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu0.commit.COM:branches 23275 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_lim_events 180 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 370366 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.369578 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 0.675268 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 264099 71.08% 71.08% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 83154 22.38% 93.46% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 22390 6.03% 99.48% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 687 0.18% 99.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 334 0.09% 99.76% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 262900 70.98% 70.98% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 83158 22.45% 93.44% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 22390 6.05% 99.48% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 687 0.19% 99.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 335 0.09% 99.76% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 180 0.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::total 370366 # Number of insts commited each cycle system.cpu0.commit.COM:count 136879 # Number of instructions committed system.cpu0.commit.COM:loads 41762 # Number of loads committed system.cpu0.commit.COM:membars 84 # Number of memory barriers committed @@ -47,16 +47,16 @@ system.cpu0.commit.commitNonSpecStalls 559 # Th system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit system.cpu0.committedInsts 116789 # Number of Instructions Simulated system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated -system.cpu0.cpi 3.716155 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.716155 # CPI: Total CPI of All Threads +system.cpu0.cpi 3.706325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.706325 # CPI: Total CPI of All Threads system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency 30381.703470 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 24347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 318 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_hits 24348 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 9631000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.012852 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 317 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses @@ -71,156 +71,156 @@ system.cpu0.dcache.SwapReq_mshr_miss_latency 329000 system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 20768 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 577 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_avg_miss_latency 44931.354360 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36030.726257 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 20806 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 24218000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.025252 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 360 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 6449500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008386 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 179 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25250 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 162.931818 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 162.926136 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 50500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 45115 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 895 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_avg_miss_latency 39543.224299 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 45154 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 33849000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.018605 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 856 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 11937500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.008846 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 407 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context +system.cpu0.dcache.occ_%::0 0.285120 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.014413 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 145.981294 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -7.379294 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_miss_latency 39543.224299 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 45115 # number of overall hits -system.cpu0.dcache.overall_miss_latency 36067000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 895 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 467 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 428 # number of overall MSHR misses +system.cpu0.dcache.overall_hits 45154 # number of overall hits +system.cpu0.dcache.overall_miss_latency 33849000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.018605 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 856 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 449 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 11937500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.008846 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 407 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 10 # number of replacements system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 141.792519 # Cycle average of tags in use -system.cpu0.dcache.total_refs 28676 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 138.602000 # Cycle average of tags in use +system.cpu0.dcache.total_refs 28675 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 154431 # Number of cycles decode is running +system.cpu0.decode.DECODE:BlockedCycles 52020 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 451824 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 163842 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 154430 # Number of cycles decode is running system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 70853 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 87025 # Number of cache lines fetched -system.cpu0.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 457882 # Number of instructions fetch has processed +system.cpu0.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 70848 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 87024 # Number of cache lines fetched +system.cpu0.fetch.Cycles 242789 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 20667 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 457866 # Number of instructions fetch has processed system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.163254 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.branchRate 0.163675 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 87024 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 1.055013 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rate 1.057774 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 414658 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.104202 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.128179 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 258930 62.44% 62.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 86799 20.93% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1004 0.24% 83.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 21052 5.08% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1074 0.26% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 20905 5.04% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680 0.16% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 710 0.17% 94.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 23504 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 86155 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles +system.cpu0.fetch.rateDist::total 414658 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 87024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 37020.114943 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35068.011958 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 86154 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 32207500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 23460500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.007688 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 669 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 128.781764 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 128.973054 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 87025 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency -system.cpu0.icache.demand_hits 86155 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_accesses 87024 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 37020.114943 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency +system.cpu0.icache.demand_hits 86154 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 32207500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 23460500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.007688 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 669 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.526442 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 269.538121 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 87025 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.526858 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 269.751047 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 87024 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 37020.114943 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 86155 # number of overall hits -system.cpu0.icache.overall_miss_latency 32248500 # number of overall miss cycles +system.cpu0.icache.overall_hits 86154 # number of overall hits +system.cpu0.icache.overall_miss_latency 32207500 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses system.cpu0.icache.overall_misses 870 # number of overall misses -system.cpu0.icache.overall_mshr_hits 200 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 670 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_hits 201 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 23460500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.007688 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 669 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.replacements 363 # number of replacements -system.cpu0.icache.sampled_refs 669 # Sample count of references to valid blocks. +system.cpu0.icache.sampled_refs 668 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 269.538121 # Cycle average of tags in use -system.cpu0.icache.total_refs 86155 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 269.751047 # Cycle average of tags in use +system.cpu0.icache.total_refs 86154 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 18200 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.iew.EXEC:branches 44503 # Number of branches executed system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.434987 # Inst execution rate +system.cpu0.iew.EXEC:rate 0.436141 # Inst execution rate system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed system.cpu0.iew.EXEC:stores 22312 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed @@ -230,7 +230,7 @@ system.cpu0.iew.WB:fanout 0.972912 # av system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.iew.WB:producers 92594 # num instructions producing a value -system.cpu0.iew.WB:rate 0.431358 # insts written-back per cycle +system.cpu0.iew.WB:rate 0.432502 # insts written-back per cycle system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking @@ -248,7 +248,7 @@ system.cpu0.iew.iewLSQFullEvents 0 # Nu system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -260,8 +260,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores 21634 # system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.269095 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.269095 # IPC: Total IPC of All Threads +system.cpu0.ipc 0.269809 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.269809 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued @@ -293,28 +293,28 @@ system.cpu0.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # at system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 414658 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.558933 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948995 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 281858 67.78% 67.78% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 66212 15.92% 83.70% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.31% 94.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.24% 99.25% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 280664 67.69% 67.69% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 66211 15.97% 83.65% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.34% 93.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.25% 99.25% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 926 0.22% 99.90% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 279 0.07% 99.96% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 925 0.22% 99.90% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 280 0.07% 99.96% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.534016 # Inst issue rate +system.cpu0.iq.ISSUE:issued_per_cycle::total 414658 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.535432 # Inst issue rate system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsExamined 98222 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph @@ -322,23 +322,23 @@ system.cpu0.memDep0.conflictingLoads 19721 # Nu system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores. system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 434006 # number of cpu cycles simulated +system.cpu0.numCycles 432858 # number of cpu cycles simulated system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle +system.cpu0.rename.RENAME:IdleCycles 185237 # Number of cycles rename is idle system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 133139 # Number of cycles rename is running +system.cpu0.rename.RENAME:RunCycles 133140 # Number of cycles rename is running system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UnblockCycles 353 # Number of cycles rename is unblocking system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializeStallCycles 51604 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed -system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.rename.RENAME:skidInsts 83212 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 20768 # count of temporary serializing insts renamed +system.cpu0.timesIdled 340 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits @@ -379,8 +379,8 @@ system.cpu1.commit.commitNonSpecStalls 9688 # Th system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit system.cpu1.committedInsts 102085 # Number of Instructions Simulated system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated -system.cpu1.cpi 3.876926 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 3.876926 # CPI: Total CPI of All Threads +system.cpu1.cpi 3.872714 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 3.872714 # CPI: Total CPI of All Threads system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency @@ -436,8 +436,10 @@ system.cpu1.dcache.demand_mshr_misses 286 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context +system.cpu1.dcache.occ_%::0 0.053273 # Average percentage of cache occupancy +system.cpu1.dcache.occ_%::1 -0.013192 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 27.275525 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -6.754298 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency @@ -455,7 +457,7 @@ system.cpu1.dcache.overall_mshr_uncacheable_misses 0 system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 27.232391 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 20.521228 # Cycle average of tags in use system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks @@ -471,27 +473,27 @@ system.cpu1.fetch.Cycles 239936 # Nu system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.211405 # Number of branch fetches per cycle +system.cpu1.fetch.branchRate 0.211635 # Number of branch fetches per cycle system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.037284 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rate 1.038412 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 392437 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.046109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.946317 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 234991 59.88% 59.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 84908 21.64% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 20175 5.14% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13313 3.39% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 2697 0.69% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 17066 4.35% 95.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1329 0.34% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 2421 0.62% 96.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 15537 3.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 392437 # Number of instructions fetched each cycle (Total) system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency @@ -525,8 +527,8 @@ system.cpu1.icache.demand_mshr_misses 636 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.182938 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 93.664377 # Average occupied blocks per context +system.cpu1.icache.occ_%::0 0.183206 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 93.801528 # Average occupied blocks per context system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency @@ -544,14 +546,14 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0 system.cpu1.icache.replacements 524 # number of replacements system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 93.664377 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 93.801528 # Cycle average of tags in use system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.iew.EXEC:branches 36547 # Number of branches executed system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.410224 # Inst execution rate +system.cpu1.iew.EXEC:rate 0.410671 # Inst execution rate system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed system.cpu1.iew.EXEC:stores 12164 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed @@ -561,7 +563,7 @@ system.cpu1.iew.WB:fanout 0.929676 # av system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.iew.WB:producers 73225 # num instructions producing a value -system.cpu1.iew.WB:rate 0.401065 # insts written-back per cycle +system.cpu1.iew.WB:rate 0.401501 # insts written-back per cycle system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -591,8 +593,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores 10115 # system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.257936 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.257936 # IPC: Total IPC of All Threads +system.cpu1.ipc 0.258217 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.258217 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued @@ -624,15 +626,15 @@ system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # at system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 392437 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.499262 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.956261 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 276221 70.31% 70.31% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.17% 88.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 275791 70.28% 70.28% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.19% 88.46% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.38% 99.27% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.39% 99.27% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle @@ -640,8 +642,8 @@ system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Nu system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.495050 # Inst issue rate +system.cpu1.iq.ISSUE:issued_per_cycle::total 392437 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.495589 # Inst issue rate system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ @@ -653,7 +655,7 @@ system.cpu1.memDep0.conflictingLoads 6760 # Nu system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores. system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 395776 # number of cpu cycles simulated +system.cpu1.numCycles 395346 # number of cpu cycles simulated system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full @@ -708,8 +710,8 @@ system.cpu2.commit.commitNonSpecStalls 8513 # Th system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit system.cpu2.committedInsts 104211 # Number of Instructions Simulated system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated -system.cpu2.cpi 3.794734 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.794734 # CPI: Total CPI of All Threads +system.cpu2.cpi 3.790608 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.790608 # CPI: Total CPI of All Threads system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency @@ -765,8 +767,10 @@ system.cpu2.dcache.demand_mshr_misses 284 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context +system.cpu2.dcache.occ_%::0 0.057032 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.010468 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 29.200191 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -5.359479 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency @@ -784,7 +788,7 @@ system.cpu2.dcache.overall_mshr_uncacheable_misses 0 system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 29.152957 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 23.840712 # Cycle average of tags in use system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 1 # number of writebacks @@ -800,27 +804,27 @@ system.cpu2.fetch.Cycles 236913 # Nu system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.205860 # Number of branch fetches per cycle +system.cpu2.fetch.branchRate 0.206084 # Number of branch fetches per cycle system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.042974 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rate 1.044109 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 389876 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.057893 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.974904 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 234334 60.10% 60.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 83865 21.51% 81.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 17837 4.58% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 14411 3.70% 89.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 2742 0.70% 90.59% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1358 0.35% 95.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 2423 0.62% 95.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 16356 4.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 389876 # Number of instructions fetched each cycle (Total) system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency @@ -854,8 +858,8 @@ system.cpu2.icache.demand_mshr_misses 632 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.191179 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 97.883584 # Average occupied blocks per context +system.cpu2.icache.occ_%::0 0.191472 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 98.033912 # Average occupied blocks per context system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency @@ -873,14 +877,14 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0 system.cpu2.icache.replacements 522 # number of replacements system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 97.883584 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 98.033912 # Cycle average of tags in use system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.iew.EXEC:branches 37149 # Number of branches executed system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed -system.cpu2.iew.EXEC:rate 0.419532 # Inst execution rate +system.cpu2.iew.EXEC:rate 0.419988 # Inst execution rate system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed system.cpu2.iew.EXEC:stores 13043 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed @@ -890,7 +894,7 @@ system.cpu2.iew.WB:fanout 0.931855 # av system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.iew.WB:producers 75620 # num instructions producing a value -system.cpu2.iew.WB:rate 0.410403 # insts written-back per cycle +system.cpu2.iew.WB:rate 0.410849 # insts written-back per cycle system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -920,8 +924,8 @@ system.cpu2.iew.lsq.thread.0.squashedStores 11000 # system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 0.263523 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.263523 # IPC: Total IPC of All Threads +system.cpu2.ipc 0.263810 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.263810 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued @@ -953,14 +957,14 @@ system.cpu2.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # at system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 389876 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.513307 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969448 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0 272942 69.93% 69.93% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.79% 87.72% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.45% 94.16% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.71% 97.88% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0 272512 69.90% 69.90% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.80% 87.70% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.46% 94.16% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.72% 97.87% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle @@ -969,8 +973,8 @@ system.cpu2.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Nu system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 0.506068 # Inst issue rate +system.cpu2.iq.ISSUE:issued_per_cycle::total 389876 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 0.506619 # Inst issue rate system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ @@ -982,7 +986,7 @@ system.cpu2.memDep0.conflictingLoads 7669 # Nu system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores. system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 395453 # number of cpu cycles simulated +system.cpu2.numCycles 395023 # number of cpu cycles simulated system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made @@ -1036,8 +1040,8 @@ system.cpu3.commit.commitNonSpecStalls 6025 # Th system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit system.cpu3.committedInsts 111128 # Number of Instructions Simulated system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated -system.cpu3.cpi 3.555675 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 3.555675 # CPI: Total CPI of All Threads +system.cpu3.cpi 3.551805 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 3.551805 # CPI: Total CPI of All Threads system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency @@ -1093,8 +1097,10 @@ system.cpu3.dcache.demand_mshr_misses 267 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context +system.cpu3.dcache.occ_%::0 0.054908 # Average percentage of cache occupancy +system.cpu3.dcache.occ_%::1 -0.015654 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 28.113086 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -8.014642 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency @@ -1112,7 +1118,7 @@ system.cpu3.dcache.overall_mshr_uncacheable_misses 0 system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 28.067737 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 20.098444 # Cycle average of tags in use system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks @@ -1128,27 +1134,27 @@ system.cpu3.fetch.Cycles 235714 # Nu system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.208197 # Number of branch fetches per cycle +system.cpu3.fetch.branchRate 0.208424 # Number of branch fetches per cycle system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.103263 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rate 1.104465 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 392184 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.111565 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.082267 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 237449 60.55% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 82939 21.15% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 12394 3.16% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 15941 4.06% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 2706 0.69% 89.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 16830 4.29% 93.90% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 2412 0.62% 94.97% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 19726 5.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 392184 # Number of instructions fetched each cycle (Total) system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency @@ -1182,8 +1188,8 @@ system.cpu3.icache.demand_mshr_misses 639 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.188794 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 96.662446 # Average occupied blocks per context +system.cpu3.icache.occ_%::0 0.189077 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 96.807549 # Average occupied blocks per context system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency @@ -1201,14 +1207,14 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0 system.cpu3.icache.replacements 527 # number of replacements system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 96.662446 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 96.807549 # Cycle average of tags in use system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.iew.EXEC:branches 39408 # Number of branches executed system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed -system.cpu3.iew.EXEC:rate 0.449348 # Inst execution rate +system.cpu3.iew.EXEC:rate 0.449837 # Inst execution rate system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed system.cpu3.iew.EXEC:stores 15425 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed @@ -1218,7 +1224,7 @@ system.cpu3.iew.WB:fanout 0.937246 # av system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.iew.WB:producers 82697 # num instructions producing a value -system.cpu3.iew.WB:rate 0.440189 # insts written-back per cycle +system.cpu3.iew.WB:rate 0.440668 # insts written-back per cycle system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -1248,8 +1254,8 @@ system.cpu3.iew.lsq.thread.0.squashedStores 13369 # system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 0.281241 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.281241 # IPC: Total IPC of All Threads +system.cpu3.ipc 0.281547 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.281547 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued @@ -1281,14 +1287,14 @@ system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # at system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 392184 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.547009 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.999225 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0 270914 69.00% 69.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.85% 85.85% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.74% 93.59% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.29% 97.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0 270484 68.97% 68.97% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.87% 85.84% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.75% 93.58% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.30% 97.88% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle @@ -1297,8 +1303,8 @@ system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Nu system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 0.542923 # Inst issue rate +system.cpu3.iq.ISSUE:issued_per_cycle::total 392184 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 0.543515 # Inst issue rate system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ @@ -1310,7 +1316,7 @@ system.cpu3.memDep0.conflictingLoads 10938 # Nu system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores. system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 395135 # number of cpu cycles simulated +system.cpu3.numCycles 394705 # number of cpu cycles simulated system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full @@ -1331,13 +1337,13 @@ system.l2c.ReadExReq_accesses::1 12 # nu system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 73122.340426 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 528730.769231 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 73117.021277 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 572750 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 528692.307692 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 572750 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1747309.328969 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40309.160305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6873000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses @@ -1348,179 +1354,181 @@ system.l2c.ReadExReq_misses::1 12 # nu system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5280500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 751 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 63425.601751 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2229653.846154 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 362318.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 4830916.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_accesses::total 2700 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 63452.850877 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 2225730.769231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 361681.250000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 4822416.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 7473281.536775 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39996.370236 # average ReadReq mshr miss latency system.l2c.ReadReq_hits::0 295 # number of ReadReq hits system.l2c.ReadReq_hits::1 637 # number of ReadReq hits system.l2c.ReadReq_hits::2 566 # number of ReadReq hits system.l2c.ReadReq_hits::3 647 # number of ReadReq hits system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.607713 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_latency 28934500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.607190 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 457 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::total 0.760218 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 456 # number of ReadReq misses system.l2c.ReadReq_misses::1 13 # number of ReadReq misses system.l2c.ReadReq_misses::2 80 # number of ReadReq misses system.l2c.ReadReq_misses::3 6 # number of ReadReq misses -system.l2c.ReadReq_misses::total 556 # number of ReadReq misses +system.l2c.ReadReq_misses::total 555 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.734043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.849231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.854489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 0.845329 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 53 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_mshr_miss_latency 22038000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.733688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.847692 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.852941 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.843798 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.278120 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 551 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 24698.113208 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 59500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_accesses::total 95 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5625 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 7500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 27784.090909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.903226 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 53 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::total 3.903226 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 2.207547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 5.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.318182 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::total 92 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 3680000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 2.967742 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.380952 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.380952 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 4.181818 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.911465 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 92 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.003738 # Average number of references to valid blocks. +system.l2c.avg_refs 3.873418 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 846 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 845 # number of demand (read+write) accesses system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 65079.854809 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1434360 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 385580.645161 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1992166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency +system.l2c.demand_accesses::total 2831 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 65104.545455 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1432300 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 385026.881720 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1989305.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3871736.982731 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency system.l2c.demand_hits::0 295 # number of demand (read+write) hits system.l2c.demand_hits::1 637 # number of demand (read+write) hits system.l2c.demand_hits::2 566 # number of demand (read+write) hits system.l2c.demand_hits::3 647 # number of demand (read+write) hits system.l2c.demand_hits::total 2145 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.651300 # miss rate for demand accesses +system.l2c.demand_miss_latency 35807500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.650888 # miss rate for demand accesses system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses -system.l2c.demand_misses::0 551 # number of demand (read+write) misses +system.l2c.demand_miss_rate::total 0.856843 # miss rate for demand accesses +system.l2c.demand_misses::0 550 # number of demand (read+write) misses system.l2c.demand_misses::1 25 # number of demand (read+write) misses system.l2c.demand_misses::2 93 # number of demand (read+write) misses system.l2c.demand_misses::3 18 # number of demand (read+write) misses -system.l2c.demand_misses::total 687 # number of demand (read+write) misses +system.l2c.demand_misses::total 686 # number of demand (read+write) misses system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.807329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.031722 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.036419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.027068 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 27318500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.807101 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.030211 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.034901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.025564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 3.897777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 682 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.005570 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.005838 # Average percentage of cache occupancy system.l2c.occ_%::1 0.000152 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.001067 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.001069 # Average percentage of cache occupancy system.l2c.occ_%::3 0.000056 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 365.031703 # Average occupied blocks per context -system.l2c.occ_blocks::1 9.942146 # Average occupied blocks per context -system.l2c.occ_blocks::2 69.921003 # Average occupied blocks per context -system.l2c.occ_blocks::3 3.643564 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context -system.l2c.overall_accesses::0 846 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 382.596816 # Average occupied blocks per context +system.l2c.occ_blocks::1 9.957586 # Average occupied blocks per context +system.l2c.occ_blocks::2 70.028959 # Average occupied blocks per context +system.l2c.occ_blocks::3 3.647267 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.949685 # Average occupied blocks per context +system.l2c.overall_accesses::0 845 # number of overall (read+write) accesses system.l2c.overall_accesses::1 662 # number of overall (read+write) accesses system.l2c.overall_accesses::2 659 # number of overall (read+write) accesses system.l2c.overall_accesses::3 665 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 65079.854809 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1434360 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 385580.645161 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1992166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency +system.l2c.overall_accesses::total 2831 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 65104.545455 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1432300 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 385026.881720 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1989305.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3871736.982731 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 295 # number of overall hits system.l2c.overall_hits::1 637 # number of overall hits system.l2c.overall_hits::2 566 # number of overall hits system.l2c.overall_hits::3 647 # number of overall hits system.l2c.overall_hits::total 2145 # number of overall hits -system.l2c.overall_miss_latency 35859000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.651300 # miss rate for overall accesses +system.l2c.overall_miss_latency 35807500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.650888 # miss rate for overall accesses system.l2c.overall_miss_rate::1 0.037764 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.141123 # miss rate for overall accesses system.l2c.overall_miss_rate::3 0.027068 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses -system.l2c.overall_misses::0 551 # number of overall misses +system.l2c.overall_miss_rate::total 0.856843 # miss rate for overall accesses +system.l2c.overall_misses::0 550 # number of overall misses system.l2c.overall_misses::1 25 # number of overall misses system.l2c.overall_misses::2 93 # number of overall misses system.l2c.overall_misses::3 18 # number of overall misses -system.l2c.overall_misses::total 687 # number of overall misses +system.l2c.overall_misses::total 686 # number of overall misses system.l2c.overall_mshr_hits 4 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.807329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.031722 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.036419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.027068 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 683 # number of overall MSHR misses +system.l2c.overall_mshr_miss_latency 27318500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.807101 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.030211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.034901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.025564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 3.897777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 682 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 535 # Sample count of references to valid blocks. +system.l2c.sampled_refs 553 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 454.478308 # Cycle average of tags in use +system.l2c.tagsinuse 472.180314 # Cycle average of tags in use system.l2c.total_refs 2142 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index a92224734..e833b46ac 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -119,7 +119,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index b2a4f9d96..9ac3c5e14 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:40:18 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:40:33 -M5 executing on phenom +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:04:32 +M5 executing on zizzer command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 41fb8c75a..0544aca9b 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 339283 # Simulator instruction rate (inst/s) -host_mem_usage 1120212 # Number of bytes of host memory used -host_seconds 2.00 # Real time elapsed on the host -host_tick_rate 43931389 # Simulator tick rate (ticks/s) +host_inst_rate 1027581 # Simulator instruction rate (inst/s) +host_mem_usage 1133204 # Number of bytes of host memory used +host_seconds 0.66 # Real time elapsed on the host +host_tick_rate 133016942 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated @@ -17,9 +17,9 @@ system.cpu0.dcache.SwapReq_hits 15 # nu system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 27561 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 194 # number of WriteReq misses +system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. @@ -31,10 +31,10 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 81992 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -48,10 +48,10 @@ system.cpu0.dcache.overall_accesses 82337 # nu system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 81992 # number of overall hits +system.cpu0.dcache.overall_hits 82009 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 345 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 328 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -488,28 +488,30 @@ system.l2c.ReadReq_misses::1 69 # nu system.l2c.ReadReq_misses::2 3 # number of ReadReq misses system.l2c.ReadReq_misses::3 3 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 106 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 48 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 29 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 106 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.968447 # Average number of references to valid blocks. +system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -553,12 +555,12 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.004314 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.004495 # Average percentage of cache occupancy system.l2c.occ_%::1 0.001011 # Average percentage of cache occupancy system.l2c.occ_%::2 0.000044 # Average percentage of cache occupancy system.l2c.occ_%::3 0.000029 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000098 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 282.753459 # Average occupied blocks per context +system.l2c.occ_blocks::0 294.613840 # Average occupied blocks per context system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context @@ -602,9 +604,9 @@ system.l2c.overall_mshr_misses 0 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 412 # Sample count of references to valid blocks. +system.l2c.sampled_refs 426 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 360.120529 # Cycle average of tags in use +system.l2c.tagsinuse 371.980910 # Cycle average of tags in use system.l2c.total_refs 1223 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index ca866c925..276044213 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -116,7 +116,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index e3768c24f..cae225db3 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:40:18 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:40:36 -M5 executing on phenom +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:03:45 +M5 executing on zizzer command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -84,4 +86,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 263312000 because target called exit() +Exiting @ tick 262295000 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 20f477582..a2bed5a68 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 940671 # Simulator instruction rate (inst/s) -host_mem_usage 202704 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host -host_tick_rate 380696818 # Simulator tick rate (ticks/s) +host_inst_rate 583465 # Simulator instruction rate (inst/s) +host_mem_usage 215700 # Number of bytes of host memory used +host_seconds 1.12 # Real time elapsed on the host +host_tick_rate 235218525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263312000 # Number of ticks simulated +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 262295000 # Number of ticks simulated system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency @@ -29,15 +29,15 @@ system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 41030 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38030 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 24724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 8206000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.008024 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 200 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 7606000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008024 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_avg_miss_latency 39191.256831 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36191.256831 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 7172000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 6623000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. @@ -47,39 +47,39 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 # system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 35787.292818 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 73482 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 12955000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.004902 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 362 # number of demand (read+write) misses +system.cpu0.dcache.demand_avg_miss_latency 34553.623188 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31553.623188 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 11921000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 11869000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.004902 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 10886000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.275555 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 141.084106 # Average occupied blocks per context +system.cpu0.dcache.occ_%::0 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 141.233241 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_miss_latency 34553.623188 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31553.623188 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 73482 # number of overall hits -system.cpu0.dcache.overall_miss_latency 12955000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.004902 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 362 # number of overall misses +system.cpu0.dcache.overall_hits 73499 # number of overall hits +system.cpu0.dcache.overall_miss_latency 11921000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 345 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 11869000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.004902 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_miss_latency 10886000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 141.084106 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 141.233241 # Cycle average of tags in use system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 6 # number of writebacks @@ -115,8 +115,8 @@ system.cpu0.icache.demand_mshr_misses 467 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.414415 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 212.180630 # Average occupied blocks per context +system.cpu0.icache.occ_%::0 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 212.478999 # Average occupied blocks per context system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency @@ -134,13 +134,13 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0 system.cpu0.icache.replacements 215 # number of replacements system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 212.180630 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.478999 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 526624 # number of cpu cycles simulated +system.cpu0.numCycles 524590 # number of cpu cycles simulated system.cpu0.num_insts 158353 # Number of instructions executed system.cpu0.num_refs 73905 # Number of memory references system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls @@ -196,8 +196,10 @@ system.cpu1.dcache.demand_mshr_misses 276 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.051885 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 26.564950 # Average occupied blocks per context +system.cpu1.dcache.occ_%::0 0.052024 # Average percentage of cache occupancy +system.cpu1.dcache.occ_%::1 -0.007792 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 26.636390 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -3.989577 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 46826 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency @@ -215,7 +217,7 @@ system.cpu1.dcache.overall_mshr_uncacheable_misses 0 system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 26.564950 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 22.646814 # Cycle average of tags in use system.cpu1.dcache.total_refs 17931 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks @@ -251,8 +253,8 @@ system.cpu1.icache.demand_mshr_misses 358 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.136289 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 69.779720 # Average occupied blocks per context +system.cpu1.icache.occ_%::0 0.136637 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 69.958167 # Average occupied blocks per context system.cpu1.icache.overall_accesses 168396 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency @@ -270,13 +272,13 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0 system.cpu1.icache.replacements 278 # number of replacements system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 69.779720 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 69.958167 # Cycle average of tags in use system.cpu1.icache.total_refs 168038 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.134073 # Percentage of idle cycles -system.cpu1.not_idle_fraction 0.865927 # Percentage of non-idle cycles -system.cpu1.numCycles 515096 # number of cpu cycles simulated +system.cpu1.idle_fraction 0.130715 # Percentage of idle cycles +system.cpu1.not_idle_fraction 0.869285 # Percentage of non-idle cycles +system.cpu1.numCycles 513666 # number of cpu cycles simulated system.cpu1.num_insts 168364 # Number of instructions executed system.cpu1.num_refs 46919 # Number of memory references system.cpu2.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses) @@ -331,8 +333,10 @@ system.cpu2.dcache.demand_mshr_misses 262 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.048480 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 24.821539 # Average occupied blocks per context +system.cpu2.dcache.occ_%::0 0.048606 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.003199 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 24.886220 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -1.638018 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 56889 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency @@ -350,7 +354,7 @@ system.cpu2.dcache.overall_mshr_uncacheable_misses 0 system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 24.821539 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 23.248201 # Cycle average of tags in use system.cpu2.dcache.total_refs 33601 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 1 # number of writebacks @@ -386,8 +390,8 @@ system.cpu2.icache.demand_mshr_misses 358 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.127582 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 65.321793 # Average occupied blocks per context +system.cpu2.icache.occ_%::0 0.127896 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 65.482956 # Average occupied blocks per context system.cpu2.icache.overall_accesses 161568 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency @@ -405,13 +409,13 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0 system.cpu2.icache.replacements 278 # number of replacements system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 65.321793 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 65.482956 # Cycle average of tags in use system.cpu2.icache.total_refs 161210 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0.134570 # Percentage of idle cycles -system.cpu2.not_idle_fraction 0.865430 # Percentage of non-idle cycles -system.cpu2.numCycles 515092 # number of cpu cycles simulated +system.cpu2.idle_fraction 0.131215 # Percentage of idle cycles +system.cpu2.not_idle_fraction 0.868785 # Percentage of non-idle cycles +system.cpu2.numCycles 513662 # number of cpu cycles simulated system.cpu2.num_insts 161536 # Number of instructions executed system.cpu2.num_refs 56961 # Number of memory references system.cpu3.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses) @@ -466,8 +470,10 @@ system.cpu3.dcache.demand_mshr_misses 262 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.049924 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 25.561342 # Average occupied blocks per context +system.cpu3.dcache.occ_%::0 0.050054 # Average percentage of cache occupancy +system.cpu3.dcache.occ_%::1 -0.007034 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 25.627740 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -3.601472 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 56189 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency @@ -485,7 +491,7 @@ system.cpu3.dcache.overall_mshr_uncacheable_misses 0 system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 25.561342 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 22.026268 # Cycle average of tags in use system.cpu3.dcache.total_refs 32498 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks @@ -521,8 +527,8 @@ system.cpu3.icache.demand_mshr_misses 359 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.131739 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 67.450287 # Average occupied blocks per context +system.cpu3.icache.occ_%::0 0.132070 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 67.619703 # Average occupied blocks per context system.cpu3.icache.overall_accesses 162202 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency @@ -540,13 +546,13 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0 system.cpu3.icache.replacements 279 # number of replacements system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 67.450287 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 67.619703 # Cycle average of tags in use system.cpu3.icache.total_refs 161843 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0.135045 # Percentage of idle cycles -system.cpu3.not_idle_fraction 0.864955 # Percentage of non-idle cycles -system.cpu3.numCycles 515100 # number of cpu cycles simulated +system.cpu3.idle_fraction 0.131691 # Percentage of idle cycles +system.cpu3.not_idle_fraction 0.868309 # Percentage of non-idle cycles +system.cpu3.numCycles 513670 # number of cpu cycles simulated system.cpu3.num_insts 162170 # Number of instructions executed system.cpu3.num_refs 56264 # Number of memory references system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) @@ -613,42 +619,44 @@ system.l2c.ReadReq_mshr_miss_rate::2 1.143243 # ms system.l2c.ReadReq_mshr_miss_rate::3 1.140162 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 4.212894 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 30 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 91 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 22127.659574 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 86666.666667 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 65000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 65000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 238794.326241 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5571.428571 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 13000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 9750 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 9750 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 47 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::total 3.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::2 16 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 91 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.936170 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 7.583333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 5.687500 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.687500 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 20.894504 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 91 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 2.400000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 6 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.500000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 4.500000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 17.400000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 72 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.953883 # Average number of references to valid blocks. +system.l2c.avg_refs 2.850117 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -692,16 +700,16 @@ system.l2c.demand_mshr_misses 559 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.004171 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000879 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.004365 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000881 # Average percentage of cache occupancy system.l2c.occ_%::2 0.000040 # Average percentage of cache occupancy system.l2c.occ_%::3 0.000026 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000085 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 273.330650 # Average occupied blocks per context -system.l2c.occ_blocks::1 57.582989 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.602775 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.727475 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.583152 # Average occupied blocks per context +system.l2c.occ_blocks::0 286.079338 # Average occupied blocks per context +system.l2c.occ_blocks::1 57.730266 # Average occupied blocks per context +system.l2c.occ_blocks::2 2.608262 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.731871 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.597892 # Average occupied blocks per context system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses @@ -741,9 +749,9 @@ system.l2c.overall_mshr_misses 559 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 412 # Sample count of references to valid blocks. +system.l2c.sampled_refs 427 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 340.827042 # Cycle average of tags in use +system.l2c.tagsinuse 353.747628 # Cycle average of tags in use system.l2c.total_refs 1217 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr index 984b0004c..ac8ae900f 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu2: completed 10000 read accesses @26695905 -system.cpu6: completed 10000 read accesses @26791606 -system.cpu5: completed 10000 read accesses @26792650 -system.cpu1: completed 10000 read accesses @26942582 -system.cpu7: completed 10000 read accesses @27101805 -system.cpu3: completed 10000 read accesses @27218798 -system.cpu0: completed 10000 read accesses @27391241 -system.cpu4: completed 10000 read accesses @27569488 -system.cpu6: completed 20000 read accesses @53349763 -system.cpu2: completed 20000 read accesses @53503744 -system.cpu5: completed 20000 read accesses @53714174 -system.cpu7: completed 20000 read accesses @53950546 -system.cpu3: completed 20000 read accesses @54185930 -system.cpu0: completed 20000 read accesses @54225484 -system.cpu1: completed 20000 read accesses @54276231 -system.cpu4: completed 20000 read accesses @54597598 -system.cpu0: completed 30000 read accesses @80866924 -system.cpu7: completed 30000 read accesses @80945592 -system.cpu6: completed 30000 read accesses @81027764 -system.cpu2: completed 30000 read accesses @81035060 -system.cpu4: completed 30000 read accesses @81318103 -system.cpu5: completed 30000 read accesses @81377684 -system.cpu3: completed 30000 read accesses @81429000 -system.cpu1: completed 30000 read accesses @81820011 -system.cpu2: completed 40000 read accesses @106813760 -system.cpu3: completed 40000 read accesses @106974444 -system.cpu6: completed 40000 read accesses @106993530 -system.cpu7: completed 40000 read accesses @107261306 -system.cpu5: completed 40000 read accesses @107310319 -system.cpu0: completed 40000 read accesses @107652944 -system.cpu1: completed 40000 read accesses @107852182 -system.cpu4: completed 40000 read accesses @108023308 -system.cpu2: completed 50000 read accesses @133853751 -system.cpu6: completed 50000 read accesses @134086054 -system.cpu3: completed 50000 read accesses @134273902 -system.cpu7: completed 50000 read accesses @134574750 -system.cpu0: completed 50000 read accesses @134577823 -system.cpu1: completed 50000 read accesses @134778033 -system.cpu5: completed 50000 read accesses @134896821 -system.cpu4: completed 50000 read accesses @135759299 -system.cpu2: completed 60000 read accesses @161211555 -system.cpu3: completed 60000 read accesses @161581369 -system.cpu6: completed 60000 read accesses @161831828 -system.cpu0: completed 60000 read accesses @161942121 -system.cpu1: completed 60000 read accesses @162215822 -system.cpu7: completed 60000 read accesses @162487402 -system.cpu5: completed 60000 read accesses @162758928 -system.cpu4: completed 60000 read accesses @162827113 -system.cpu2: completed 70000 read accesses @188493937 -system.cpu1: completed 70000 read accesses @189035964 -system.cpu3: completed 70000 read accesses @189157397 -system.cpu6: completed 70000 read accesses @189252661 -system.cpu0: completed 70000 read accesses @189257028 -system.cpu7: completed 70000 read accesses @189348164 -system.cpu5: completed 70000 read accesses @189769120 -system.cpu4: completed 70000 read accesses @191028989 -system.cpu2: completed 80000 read accesses @215328997 -system.cpu7: completed 80000 read accesses @216072978 -system.cpu1: completed 80000 read accesses @216240482 -system.cpu6: completed 80000 read accesses @216413258 -system.cpu3: completed 80000 read accesses @216551338 -system.cpu5: completed 80000 read accesses @216884718 -system.cpu0: completed 80000 read accesses @216894493 -system.cpu4: completed 80000 read accesses @218108705 -system.cpu2: completed 90000 read accesses @242508064 -system.cpu7: completed 90000 read accesses @242698389 -system.cpu1: completed 90000 read accesses @242967798 -system.cpu5: completed 90000 read accesses @243529194 -system.cpu3: completed 90000 read accesses @243598064 -system.cpu6: completed 90000 read accesses @243621284 -system.cpu0: completed 90000 read accesses @244529131 -system.cpu4: completed 90000 read accesses @246008618 -system.cpu2: completed 100000 read accesses @269223994 +system.cpu4: completed 10000 read accesses @26562477 +system.cpu0: completed 10000 read accesses @26652602 +system.cpu6: completed 10000 read accesses @26653472 +system.cpu1: completed 10000 read accesses @27123929 +system.cpu2: completed 10000 read accesses @27264228 +system.cpu5: completed 10000 read accesses @27378204 +system.cpu3: completed 10000 read accesses @27427879 +system.cpu7: completed 10000 read accesses @27467412 +system.cpu4: completed 20000 read accesses @53181289 +system.cpu2: completed 20000 read accesses @53547298 +system.cpu0: completed 20000 read accesses @53713168 +system.cpu5: completed 20000 read accesses @54003765 +system.cpu6: completed 20000 read accesses @54078034 +system.cpu1: completed 20000 read accesses @54428010 +system.cpu7: completed 20000 read accesses @54428201 +system.cpu3: completed 20000 read accesses @54538530 +system.cpu2: completed 30000 read accesses @79806624 +system.cpu4: completed 30000 read accesses @80477319 +system.cpu0: completed 30000 read accesses @80890126 +system.cpu6: completed 30000 read accesses @80990962 +system.cpu5: completed 30000 read accesses @81492903 +system.cpu1: completed 30000 read accesses @81521875 +system.cpu7: completed 30000 read accesses @81619556 +system.cpu3: completed 30000 read accesses @82646612 +system.cpu2: completed 40000 read accesses @105920590 +system.cpu4: completed 40000 read accesses @106535590 +system.cpu0: completed 40000 read accesses @106901597 +system.cpu6: completed 40000 read accesses @107068434 +system.cpu5: completed 40000 read accesses @107463528 +system.cpu7: completed 40000 read accesses @108151860 +system.cpu1: completed 40000 read accesses @108295057 +system.cpu3: completed 40000 read accesses @109438245 +system.cpu2: completed 50000 read accesses @132968913 +system.cpu4: completed 50000 read accesses @133752042 +system.cpu0: completed 50000 read accesses @133897400 +system.cpu6: completed 50000 read accesses @134191909 +system.cpu5: completed 50000 read accesses @135041964 +system.cpu7: completed 50000 read accesses @135432848 +system.cpu1: completed 50000 read accesses @136127784 +system.cpu3: completed 50000 read accesses @137167267 +system.cpu2: completed 60000 read accesses @160901546 +system.cpu4: completed 60000 read accesses @161170032 +system.cpu6: completed 60000 read accesses @161540559 +system.cpu0: completed 60000 read accesses @161693235 +system.cpu5: completed 60000 read accesses @161854598 +system.cpu1: completed 60000 read accesses @163372166 +system.cpu7: completed 60000 read accesses @163560871 +system.cpu3: completed 60000 read accesses @163979808 +system.cpu2: completed 70000 read accesses @188319198 +system.cpu5: completed 70000 read accesses @188516414 +system.cpu4: completed 70000 read accesses @188575474 +system.cpu6: completed 70000 read accesses @188767860 +system.cpu0: completed 70000 read accesses @189199394 +system.cpu3: completed 70000 read accesses @191117524 +system.cpu7: completed 70000 read accesses @191140120 +system.cpu1: completed 70000 read accesses @191152245 +system.cpu2: completed 80000 read accesses @215320174 +system.cpu4: completed 80000 read accesses @215525158 +system.cpu6: completed 80000 read accesses @215775319 +system.cpu5: completed 80000 read accesses @215842805 +system.cpu0: completed 80000 read accesses @216807334 +system.cpu3: completed 80000 read accesses @218320776 +system.cpu1: completed 80000 read accesses @218370718 +system.cpu7: completed 80000 read accesses @218390295 +system.cpu2: completed 90000 read accesses @241936829 +system.cpu4: completed 90000 read accesses @242559490 +system.cpu6: completed 90000 read accesses @242752208 +system.cpu5: completed 90000 read accesses @242972513 +system.cpu0: completed 90000 read accesses @243685265 +system.cpu1: completed 90000 read accesses @244981315 +system.cpu3: completed 90000 read accesses @245492671 +system.cpu7: completed 90000 read accesses @245612294 +system.cpu2: completed 100000 read accesses @268782974 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index 35f602702..d0c56eeac 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 20 2010 12:21:09 -M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates -M5 started Aug 20 2010 12:21:31 -M5 executing on SC2B0629 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:02 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 269223994 because maximum number of loads reached +Exiting @ tick 268782974 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index c1f9d137d..41d25a32a 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,925 +1,943 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 328092 # Number of bytes of host memory used -host_seconds 194.79 # Real time elapsed on the host -host_tick_rate 1382135 # Simulator tick rate (ticks/s) +host_mem_usage 330984 # Number of bytes of host memory used +host_seconds 227.97 # Real time elapsed on the host +host_tick_rate 1179002 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 269223994 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44447 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 35088.024234 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 34084.129987 # average ReadReq mshr miss latency +sim_ticks 268782974 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44543 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 36123.721103 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 35119.772902 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7474 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 1297309520 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.831845 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 36973 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1260192538 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831845 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 36973 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 822421052 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24198 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 49598.993348 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 48595.207082 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7515 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1337589145 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.831287 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37028 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1300414951 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831287 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37028 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 858196470 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24111 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 46338.684471 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 45334.813405 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 898 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 1155656545 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.962889 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23300 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 1132268325 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962889 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23300 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529109628 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3801.306186 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 1045 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1068848096 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.956659 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23066 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1045692806 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.956659 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23066 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 565288628 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3782.376120 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.409698 # Average number of references to valid blocks. -system.cpu0.l1c.blocked::no_mshrs 69363 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.409032 # Average number of references to valid blocks. +system.cpu0.l1c.blocked::no_mshrs 69095 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_mshrs 263670001 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_mshrs 261343278 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 68645 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 40697.593699 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8372 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 2452966065 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.878039 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60273 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68654 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40044.550887 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39040.632293 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8560 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2406437241 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.875317 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60094 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 2392460863 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.878039 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60273 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2346107757 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.875317 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60094 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy -system.cpu0.l1c.occ_%::1 -0.006962 # Average percentage of cache occupancy -system.cpu0.l1c.occ_blocks::0 346.381949 # Average occupied blocks per context -system.cpu0.l1c.occ_blocks::1 -3.564360 # Average occupied blocks per context -system.cpu0.l1c.overall_accesses 68645 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 40697.593699 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency +system.cpu0.l1c.occ_%::0 0.677077 # Average percentage of cache occupancy +system.cpu0.l1c.occ_%::1 -0.479198 # Average percentage of cache occupancy +system.cpu0.l1c.occ_blocks::0 346.663656 # Average occupied blocks per context +system.cpu0.l1c.occ_blocks::1 -245.349451 # Average occupied blocks per context +system.cpu0.l1c.overall_accesses 68654 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40044.550887 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39040.632293 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8372 # number of overall hits -system.cpu0.l1c.overall_miss_latency 2452966065 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.878039 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60273 # number of overall misses +system.cpu0.l1c.overall_hits 8560 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2406437241 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.875317 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60094 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 2392460863 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.878039 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60273 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 1351530680 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2346107757 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.875317 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60094 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1423485098 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.replacements 27642 # number of replacements -system.cpu0.l1c.sampled_refs 27984 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27651 # number of replacements +system.cpu0.l1c.sampled_refs 28010 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 342.817588 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11465 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 101.314205 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11457 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10964 # number of writebacks +system.cpu0.l1c.writebacks 10896 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 98887 # number of read accesses completed -system.cpu0.num_writes 53455 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44742 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 35246.657121 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34242.680675 # average ReadReq mshr miss latency +system.cpu0.num_reads 99124 # number of read accesses completed +system.cpu0.num_writes 53367 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44692 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 36448.304577 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 35444.437717 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7551 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 1310858425 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.831232 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37191 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1273519537 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831232 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 821041101 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24235 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 48987.169998 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47983.555251 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7483 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1356204965 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.832565 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37209 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1318852083 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.832565 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37209 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 832262163 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24176 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 46547.854438 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 45544.069690 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 923 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 1141988907 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961915 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23312 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 1118592640 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961915 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23312 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 537191159 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3781.018448 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1076698421 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.956775 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23131 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1053479876 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.956775 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23131 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 547880829 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3789.476053 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.407526 # Average number of references to valid blocks. -system.cpu1.l1c.blocked::no_mshrs 69602 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.406952 # Average number of references to valid blocks. +system.cpu1.l1c.blocked::no_mshrs 69154 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_mshrs 263166446 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_mshrs 262057427 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68977 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 40540.920814 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8474 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 2452847332 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.877147 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60503 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68868 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40319.910275 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39316.074892 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8528 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2432903386 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876169 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60340 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 2392112177 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.877147 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60503 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2372331959 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876169 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60340 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy -system.cpu1.l1c.occ_%::1 -0.006074 # Average percentage of cache occupancy -system.cpu1.l1c.occ_blocks::0 346.381795 # Average occupied blocks per context -system.cpu1.l1c.occ_blocks::1 -3.109691 # Average occupied blocks per context -system.cpu1.l1c.overall_accesses 68977 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 40540.920814 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency +system.cpu1.l1c.occ_%::0 0.676672 # Average percentage of cache occupancy +system.cpu1.l1c.occ_%::1 -0.519109 # Average percentage of cache occupancy +system.cpu1.l1c.occ_blocks::0 346.455959 # Average occupied blocks per context +system.cpu1.l1c.occ_blocks::1 -265.783624 # Average occupied blocks per context +system.cpu1.l1c.overall_accesses 68868 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40319.910275 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39316.074892 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8474 # number of overall hits -system.cpu1.l1c.overall_miss_latency 2452847332 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.877147 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60503 # number of overall misses +system.cpu1.l1c.overall_hits 8528 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2432903386 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876169 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60340 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 2392112177 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.877147 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60503 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 1358232260 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2372331959 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876169 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60340 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1380142992 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.replacements 28030 # number of replacements -system.cpu1.l1c.sampled_refs 28381 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27809 # number of replacements +system.cpu1.l1c.sampled_refs 28163 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 343.272105 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11566 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 80.672335 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11461 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 11122 # number of writebacks +system.cpu1.l1c.writebacks 11031 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99459 # number of read accesses completed -system.cpu1.num_writes 53508 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44755 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 34940.465460 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 33936.624875 # average ReadReq mshr miss latency +system.cpu1.num_reads 98655 # number of read accesses completed +system.cpu1.num_writes 53481 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 45038 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 36539.477136 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 35535.528785 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7682 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 1295347876 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.828354 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37073 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1258132494 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.828354 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37073 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 842968180 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 23967 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 49240.876366 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48237.004902 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7709 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1363982142 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.828833 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37329 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1326505754 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.828833 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37329 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 836681722 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 23997 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 46378.263030 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 45374.567249 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 915 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 1135100682 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.961823 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23052 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 1111959437 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.961823 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23052 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 550257500 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3789.796507 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 1030 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1065169567 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.957078 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 22967 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1042117686 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.957078 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 22967 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 541254032 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3784.557167 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.418015 # Average number of references to valid blocks. -system.cpu2.l1c.blocked::no_mshrs 69457 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.422062 # Average number of references to valid blocks. +system.cpu2.l1c.blocked::no_mshrs 69096 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_mshrs 263227896 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_mshrs 261497762 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68722 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 40423.260840 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8597 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 2430448558 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.874902 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60125 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 69035 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40287.112064 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39283.259918 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8739 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2429151709 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.873412 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60296 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 2370091931 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.874902 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60125 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2368623440 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.873412 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60296 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.occ_%::0 0.676497 # Average percentage of cache occupancy -system.cpu2.l1c.occ_%::1 -0.002501 # Average percentage of cache occupancy -system.cpu2.l1c.occ_blocks::0 346.366637 # Average occupied blocks per context -system.cpu2.l1c.occ_blocks::1 -1.280483 # Average occupied blocks per context -system.cpu2.l1c.overall_accesses 68722 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 40423.260840 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency +system.cpu2.l1c.occ_%::0 0.676850 # Average percentage of cache occupancy +system.cpu2.l1c.occ_%::1 -0.478308 # Average percentage of cache occupancy +system.cpu2.l1c.occ_blocks::0 346.547072 # Average occupied blocks per context +system.cpu2.l1c.occ_blocks::1 -244.893619 # Average occupied blocks per context +system.cpu2.l1c.overall_accesses 69035 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40287.112064 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39283.259918 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8597 # number of overall hits -system.cpu2.l1c.overall_miss_latency 2430448558 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.874902 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60125 # number of overall misses +system.cpu2.l1c.overall_hits 8739 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2429151709 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.873412 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60296 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 2370091931 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.874902 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60125 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 1393225680 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2368623440 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.873412 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60296 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1377935754 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.replacements 27483 # number of replacements -system.cpu2.l1c.sampled_refs 27822 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27578 # number of replacements +system.cpu2.l1c.sampled_refs 27939 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 345.086155 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11630 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 101.653453 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11792 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10776 # number of writebacks +system.cpu2.l1c.writebacks 10810 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53740 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44853 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 35352.171998 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34348.249371 # average ReadReq mshr miss latency +system.cpu2.num_writes 53177 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44066 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 36663.733654 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 35659.896412 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7463 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 1321817711 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.833612 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37390 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1284281044 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833612 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 812771594 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24060 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 49141.675980 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48137.889794 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7527 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1339656164 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829188 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 36539 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1302976955 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829188 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 36539 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 855113033 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24215 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 46306.357957 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 45302.529556 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 867 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 1139742891 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.963965 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23193 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 1116462078 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.963965 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 540024650 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3782.890162 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 1039 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1073196152 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.957093 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23176 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1049931425 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.957093 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23176 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 550326400 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3815.748803 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.405809 # Average number of references to valid blocks. -system.cpu3.l1c.blocked::no_mshrs 69548 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.416270 # Average number of references to valid blocks. +system.cpu3.l1c.blocked::no_mshrs 68739 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_mshrs 263092445 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_mshrs 262290757 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68913 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 40631.210108 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8330 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 2461560602 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.879123 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60583 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68281 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40406.134405 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39402.300594 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8566 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2412852316 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.874548 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 59715 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 2400743122 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.879123 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60583 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2352908380 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.874548 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 59715 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.occ_%::0 0.675485 # Average percentage of cache occupancy -system.cpu3.l1c.occ_%::1 -0.002427 # Average percentage of cache occupancy -system.cpu3.l1c.occ_blocks::0 345.848425 # Average occupied blocks per context -system.cpu3.l1c.occ_blocks::1 -1.242713 # Average occupied blocks per context -system.cpu3.l1c.overall_accesses 68913 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 40631.210108 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency +system.cpu3.l1c.occ_%::0 0.676162 # Average percentage of cache occupancy +system.cpu3.l1c.occ_%::1 -0.498781 # Average percentage of cache occupancy +system.cpu3.l1c.occ_blocks::0 346.195007 # Average occupied blocks per context +system.cpu3.l1c.occ_blocks::1 -255.375812 # Average occupied blocks per context +system.cpu3.l1c.overall_accesses 68281 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40406.134405 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39402.300594 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8330 # number of overall hits -system.cpu3.l1c.overall_miss_latency 2461560602 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.879123 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60583 # number of overall misses +system.cpu3.l1c.overall_hits 8566 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2412852316 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.874548 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 59715 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 2400743122 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.879123 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60583 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 1352796244 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2352908380 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.874548 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 59715 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1405439433 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.replacements 27772 # number of replacements -system.cpu3.l1c.sampled_refs 28129 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27386 # number of replacements +system.cpu3.l1c.sampled_refs 27732 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 344.605712 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11415 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 90.819194 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11544 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10844 # number of writebacks +system.cpu3.l1c.writebacks 11018 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99462 # number of read accesses completed -system.cpu3.num_writes 53250 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44365 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 35201.306246 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34197.412075 # average ReadReq mshr miss latency +system.cpu3.num_reads 98478 # number of read accesses completed +system.cpu3.num_writes 53622 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 45008 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 36033.874070 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 35030.059630 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7447 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 1299561824 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.832142 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 36918 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1262500059 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.832142 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 36918 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 824241710 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24091 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 49786.879855 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48783.051269 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7527 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1350585634 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.832763 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37481 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1312961665 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.832763 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37481 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 847380535 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 23997 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 46593.872314 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 45590.001874 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 919 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 1153661580 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.961853 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23172 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 1130400864 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961853 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23172 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 525075683 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3810.709164 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 1050 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1069189588 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.956245 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 22947 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1046153773 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.956245 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 22947 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 545030541 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3774.299862 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.409480 # Average number of references to valid blocks. -system.cpu4.l1c.blocked::no_mshrs 69290 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.407790 # Average number of references to valid blocks. +system.cpu4.l1c.blocked::no_mshrs 69472 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_mshrs 264044038 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_mshrs 262208160 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68456 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 40825.818006 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8366 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 2453223404 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877790 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60090 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69005 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40043.940259 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39040.104554 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8577 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2419775222 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.875705 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60428 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 2392900923 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877790 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60090 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2359115438 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.875705 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60428 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.occ_%::0 0.675570 # Average percentage of cache occupancy -system.cpu4.l1c.occ_%::1 -0.001897 # Average percentage of cache occupancy -system.cpu4.l1c.occ_blocks::0 345.891792 # Average occupied blocks per context -system.cpu4.l1c.occ_blocks::1 -0.971043 # Average occupied blocks per context -system.cpu4.l1c.overall_accesses 68456 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 40825.818006 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency +system.cpu4.l1c.occ_%::0 0.677776 # Average percentage of cache occupancy +system.cpu4.l1c.occ_%::1 -0.492031 # Average percentage of cache occupancy +system.cpu4.l1c.occ_blocks::0 347.021071 # Average occupied blocks per context +system.cpu4.l1c.occ_blocks::1 -251.919968 # Average occupied blocks per context +system.cpu4.l1c.overall_accesses 69005 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40043.940259 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39040.104554 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8366 # number of overall hits -system.cpu4.l1c.overall_miss_latency 2453223404 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877790 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60090 # number of overall misses +system.cpu4.l1c.overall_hits 8577 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2419775222 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.875705 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60428 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 2392900923 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877790 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60090 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 1349317393 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2359115438 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.875705 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60428 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1392411076 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.replacements 27569 # number of replacements -system.cpu4.l1c.sampled_refs 27933 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27777 # number of replacements +system.cpu4.l1c.sampled_refs 28137 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 344.920749 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11438 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 95.101103 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11474 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10833 # number of writebacks +system.cpu4.l1c.writebacks 10886 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98484 # number of read accesses completed -system.cpu4.num_writes 53322 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44597 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 35021.258089 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 34017.390307 # average ReadReq mshr miss latency +system.cpu4.num_reads 99551 # number of read accesses completed +system.cpu4.num_writes 53296 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44744 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 36368.758988 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 35364.864697 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7416 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 1302125397 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.833711 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37181 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1264800589 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.833711 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37181 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 826768479 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24074 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 49364.188581 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48360.315635 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1355536385 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.833006 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37272 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1318119237 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.833006 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37272 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 852691241 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 23986 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 46171.822983 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 45167.996249 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 832 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 1147322471 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.965440 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23242 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 1123990456 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.965440 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23242 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 523151149 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3789.531715 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 1056 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1058719901 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.955974 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 22930 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1035702154 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.955974 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 22930 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 557751081 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3778.589914 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.409166 # Average number of references to valid blocks. -system.cpu5.l1c.blocked::no_mshrs 69635 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.409325 # Average number of references to valid blocks. +system.cpu5.l1c.blocked::no_mshrs 69283 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_mshrs 263884041 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_mshrs 261792045 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68671 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 40538.335865 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8248 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 2449447868 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.879891 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60423 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 68730 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40102.592705 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39098.724145 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8528 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2414256286 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875920 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60202 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 2388791045 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.879891 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60423 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2353821391 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875920 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60202 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.occ_%::0 0.675030 # Average percentage of cache occupancy -system.cpu5.l1c.occ_%::1 -0.001774 # Average percentage of cache occupancy -system.cpu5.l1c.occ_blocks::0 345.615536 # Average occupied blocks per context -system.cpu5.l1c.occ_blocks::1 -0.908352 # Average occupied blocks per context -system.cpu5.l1c.overall_accesses 68671 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 40538.335865 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency +system.cpu5.l1c.occ_%::0 0.676586 # Average percentage of cache occupancy +system.cpu5.l1c.occ_%::1 -0.517786 # Average percentage of cache occupancy +system.cpu5.l1c.occ_blocks::0 346.411919 # Average occupied blocks per context +system.cpu5.l1c.occ_blocks::1 -265.106244 # Average occupied blocks per context +system.cpu5.l1c.overall_accesses 68730 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40102.592705 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39098.724145 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8248 # number of overall hits -system.cpu5.l1c.overall_miss_latency 2449447868 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.879891 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60423 # number of overall misses +system.cpu5.l1c.overall_hits 8528 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2414256286 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875920 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60202 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 2388791045 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.879891 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60423 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 1349919628 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2353821391 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875920 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60202 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1410442322 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.replacements 27529 # number of replacements -system.cpu5.l1c.sampled_refs 27886 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27648 # number of replacements +system.cpu5.l1c.sampled_refs 28012 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 344.707183 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11410 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 81.305675 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11466 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10821 # number of writebacks +system.cpu5.l1c.writebacks 10733 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99231 # number of read accesses completed -system.cpu5.num_writes 53409 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44579 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 34889.637670 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33885.824425 # average ReadReq mshr miss latency +system.cpu5.num_reads 99169 # number of read accesses completed +system.cpu5.num_writes 53407 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44448 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 36132.726042 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 35128.832255 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7552 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 1291858614 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.830593 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37027 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1254690421 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.830593 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37027 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 827526553 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24391 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 49206.403643 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 48202.444762 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7362 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1340018278 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.834368 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37086 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1302787873 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834368 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37086 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 855211413 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24069 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 46585.122881 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 45581.252108 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 947 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 1153594927 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.961174 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23444 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 1130058115 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961174 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23444 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 533892016 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3771.501135 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 1063 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1071737337 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.955835 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23006 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1048642286 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.955835 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23006 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 544765056 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3789.464275 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.414445 # Average number of references to valid blocks. -system.cpu6.l1c.blocked::no_mshrs 69628 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.404372 # Average number of references to valid blocks. +system.cpu6.l1c.blocked::no_mshrs 69181 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_mshrs 262602081 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_mshrs 262158928 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68970 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 40440.104199 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8499 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 2445453541 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.876773 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60471 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68517 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40134.387522 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39130.502546 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8425 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2411755615 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.877038 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60092 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 2384748536 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.876773 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60471 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2351430159 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.877038 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60092 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.occ_%::0 0.676765 # Average percentage of cache occupancy -system.cpu6.l1c.occ_%::1 -0.002698 # Average percentage of cache occupancy -system.cpu6.l1c.occ_blocks::0 346.503445 # Average occupied blocks per context -system.cpu6.l1c.occ_blocks::1 -1.381316 # Average occupied blocks per context -system.cpu6.l1c.overall_accesses 68970 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 40440.104199 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency +system.cpu6.l1c.occ_%::0 0.677801 # Average percentage of cache occupancy +system.cpu6.l1c.occ_%::1 -0.496036 # Average percentage of cache occupancy +system.cpu6.l1c.occ_blocks::0 347.034179 # Average occupied blocks per context +system.cpu6.l1c.occ_blocks::1 -253.970364 # Average occupied blocks per context +system.cpu6.l1c.overall_accesses 68517 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40134.387522 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39130.502546 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8499 # number of overall hits -system.cpu6.l1c.overall_miss_latency 2445453541 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.876773 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60471 # number of overall misses +system.cpu6.l1c.overall_hits 8425 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2411755615 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.877038 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60092 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 2384748536 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.876773 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60471 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 1361418569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2351430159 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.877038 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60092 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1399976469 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.replacements 27737 # number of replacements -system.cpu6.l1c.sampled_refs 28093 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27727 # number of replacements +system.cpu6.l1c.sampled_refs 28088 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 345.122129 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11643 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 93.063815 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11358 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11013 # number of writebacks +system.cpu6.l1c.writebacks 10914 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99221 # number of read accesses completed -system.cpu6.num_writes 53555 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 45091 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 34987.655695 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33983.814011 # average ReadReq mshr miss latency +system.cpu6.num_reads 99683 # number of read accesses completed +system.cpu6.num_writes 53523 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44337 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 36522.690669 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 35518.851968 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7691 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 1308538323 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.829434 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37400 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 1270994644 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.829434 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37400 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 814528138 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24179 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 49459.078476 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48455.291783 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7480 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1346116810 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.831292 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 36857 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1309118327 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.831292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 36857 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 838959921 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24343 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 46424.783164 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 45420.867730 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 898 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 1151456806 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.962860 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23281 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 1128087648 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962860 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23281 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 533243363 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3781.140887 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 1012 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1083136616 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.958427 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23331 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1059714265 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.958427 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23331 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 540840211 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3796.000043 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.414313 # Average number of references to valid blocks. -system.cpu7.l1c.blocked::no_mshrs 69687 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.416064 # Average number of references to valid blocks. +system.cpu7.l1c.blocked::no_mshrs 69142 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles::no_mshrs 263496365 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_mshrs 262463035 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69270 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 40539.792175 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8589 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 2459995129 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.876007 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60681 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 68680 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40361.092344 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39357.223898 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8492 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2429253426 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876354 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60188 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 2399082292 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.876007 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60681 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 2368832592 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876354 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60188 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.occ_%::0 0.680280 # Average percentage of cache occupancy -system.cpu7.l1c.occ_%::1 -0.007590 # Average percentage of cache occupancy -system.cpu7.l1c.occ_blocks::0 348.303356 # Average occupied blocks per context -system.cpu7.l1c.occ_blocks::1 -3.885943 # Average occupied blocks per context -system.cpu7.l1c.overall_accesses 69270 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 40539.792175 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency +system.cpu7.l1c.occ_%::0 0.674827 # Average percentage of cache occupancy +system.cpu7.l1c.occ_%::1 -0.513462 # Average percentage of cache occupancy +system.cpu7.l1c.occ_blocks::0 345.511223 # Average occupied blocks per context +system.cpu7.l1c.occ_blocks::1 -262.892483 # Average occupied blocks per context +system.cpu7.l1c.overall_accesses 68680 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40361.092344 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39357.223898 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8589 # number of overall hits -system.cpu7.l1c.overall_miss_latency 2459995129 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.876007 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60681 # number of overall misses +system.cpu7.l1c.overall_hits 8492 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2429253426 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876354 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60188 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 2399082292 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.876007 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60681 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 1347771501 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 2368832592 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876354 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60188 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1379800132 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.replacements 28023 # number of replacements -system.cpu7.l1c.sampled_refs 28394 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27465 # number of replacements +system.cpu7.l1c.sampled_refs 27801 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 345.385459 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11764 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 82.618740 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11567 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 11064 # number of writebacks +system.cpu7.l1c.writebacks 10979 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99565 # number of read accesses completed -system.cpu7.num_writes 53846 # number of write accesses completed -system.l2c.ReadExReq_accesses::0 9412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 9288 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 9313 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 9344 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::4 9463 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::5 9358 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::6 9360 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::7 9364 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 74902 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 396995.145984 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 402295.253445 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 401215.324171 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 399884.237372 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::4 394855.575822 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::5 399285.992092 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::6 399200.674573 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::7 399030.148868 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 3192762.352326 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 39999.222355 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 3736518314 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::4 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::5 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::6 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::7 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 8 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 9412 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 9288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 9313 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 9344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::4 9463 # number of ReadExReq misses -system.l2c.ReadExReq_misses::5 9358 # number of ReadExReq misses -system.l2c.ReadExReq_misses::6 9360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::7 9364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 74902 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 557 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 2973742186 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 7.898959 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 8.004414 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 7.982927 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 7.956443 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::4 7.856388 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::5 7.944539 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::6 7.942842 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::7 7.939449 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 63.525961 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74345 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 17188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 17330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 17220 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 17498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::4 17144 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::5 17272 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::6 17157 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::7 17383 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 138192 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 401579.741645 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 391420.730324 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 401239.419831 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 391097.402445 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::4 398873.222746 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::5 393306.625187 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::6 405084.287645 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::7 395078.867991 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 3177680.297815 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40002.426325 # average ReadReq mshr miss latency +system.cpu7.num_reads 98421 # number of read accesses completed +system.cpu7.num_writes 53590 # number of write accesses completed +system.l2c.ReadExReq_accesses::0 9369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 9394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 9196 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 9315 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::4 9332 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::5 9245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::6 9400 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::7 9466 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 74717 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 398260.224036 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 396016.805392 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 405312.464104 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 397509.598950 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::4 399391.492087 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::5 403926.306566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::6 396495.407681 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::7 394166.506608 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 3191078.805424 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40001.724786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 1955 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 1938 # number of ReadExReq hits +system.l2c.ReadExReq_hits::2 1911 # number of ReadExReq hits +system.l2c.ReadExReq_hits::3 1887 # number of ReadExReq hits +system.l2c.ReadExReq_hits::4 1939 # number of ReadExReq hits +system.l2c.ReadExReq_hits::5 1935 # number of ReadExReq hits +system.l2c.ReadExReq_hits::6 1953 # number of ReadExReq hits +system.l2c.ReadExReq_hits::7 1975 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15493 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 2952701301 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.791333 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.793698 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 0.792192 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 0.797424 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::4 0.792220 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::5 0.790698 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::6 0.792234 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::7 0.791359 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 6.341158 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 7414 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7456 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 7285 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 7428 # number of ReadExReq misses +system.l2c.ReadExReq_misses::4 7393 # number of ReadExReq misses +system.l2c.ReadExReq_misses::5 7310 # number of ReadExReq misses +system.l2c.ReadExReq_misses::6 7447 # number of ReadExReq misses +system.l2c.ReadExReq_misses::7 7491 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 59224 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 546 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2347221207 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 6.262995 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 6.246327 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 6.380818 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 6.299302 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::4 6.287827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::5 6.346998 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::6 6.242340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::7 6.198817 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 50.265425 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 58678 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 17167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 17274 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 17433 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 17042 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::4 17211 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::5 17351 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::6 17031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::7 17188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 137697 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 404610.500772 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 394067.785201 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 392103.013129 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 400149.903324 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::4 398056.998482 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::5 392037.858092 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::6 398124.169760 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::7 399810.850703 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 3178961.079464 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000.752102 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 11293 # number of ReadReq hits -system.l2c.ReadReq_hits::1 11282 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11320 # number of ReadReq hits -system.l2c.ReadReq_hits::3 11445 # number of ReadReq hits -system.l2c.ReadReq_hits::4 11209 # number of ReadReq hits -system.l2c.ReadReq_hits::5 11253 # number of ReadReq hits -system.l2c.ReadReq_hits::6 11313 # number of ReadReq hits -system.l2c.ReadReq_hits::7 11391 # number of ReadReq hits -system.l2c.ReadReq_hits::total 90506 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 2367312577 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.342972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.348990 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.342625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.345925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::4 0.346185 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::5 0.348483 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::6 0.340619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::7 0.344705 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 2.760504 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 5895 # number of ReadReq misses -system.l2c.ReadReq_misses::1 6048 # number of ReadReq misses -system.l2c.ReadReq_misses::2 5900 # number of ReadReq misses -system.l2c.ReadReq_misses::3 6053 # number of ReadReq misses -system.l2c.ReadReq_misses::4 5935 # number of ReadReq misses -system.l2c.ReadReq_misses::5 6019 # number of ReadReq misses -system.l2c.ReadReq_misses::6 5844 # number of ReadReq misses -system.l2c.ReadReq_misses::7 5992 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47686 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 1864793108 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 2.712183 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.689960 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.707143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 2.664133 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::4 2.719144 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::5 2.698993 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::6 2.717083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::7 2.681758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 21.590396 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 46617 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 3184396233 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 2342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 2293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 2237 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 2252 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::4 2274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::5 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::7 2359 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18459 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 217987.236123 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 222645.489315 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 228219.091194 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 226698.981794 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::4 224505.763852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::5 217152.746491 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::6 217152.746491 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::7 216416.323442 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1770778.378702 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.703945 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 510526107 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::4 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::5 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::6 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::7 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 8 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2342 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 2293 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 2237 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 2252 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::4 2274 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::5 2351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::6 2351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::7 2359 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18459 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 57 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 736092954 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 7.857387 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 8.025294 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 8.226196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 8.171403 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::4 8.092348 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::5 7.827308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::6 7.827308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::7 7.800763 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 63.828007 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18402 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_hits::0 11336 # number of ReadReq hits +system.l2c.ReadReq_hits::1 11287 # number of ReadReq hits +system.l2c.ReadReq_hits::2 11416 # number of ReadReq hits +system.l2c.ReadReq_hits::3 11146 # number of ReadReq hits +system.l2c.ReadReq_hits::4 11284 # number of ReadReq hits +system.l2c.ReadReq_hits::5 11333 # number of ReadReq hits +system.l2c.ReadReq_hits::6 11105 # number of ReadReq hits +system.l2c.ReadReq_hits::7 11287 # number of ReadReq hits +system.l2c.ReadReq_hits::total 90194 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2359283830 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.339663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.346590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.345150 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.345969 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::4 0.344373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::5 0.346839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::6 0.347954 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::7 0.343321 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 2.759859 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 5831 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5987 # number of ReadReq misses +system.l2c.ReadReq_misses::2 6017 # number of ReadReq misses +system.l2c.ReadReq_misses::3 5896 # number of ReadReq misses +system.l2c.ReadReq_misses::4 5927 # number of ReadReq misses +system.l2c.ReadReq_misses::5 6018 # number of ReadReq misses +system.l2c.ReadReq_misses::6 5926 # number of ReadReq misses +system.l2c.ReadReq_misses::7 5901 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47503 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1000 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 1860154975 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 2.708860 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.692081 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 2.667527 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 2.728729 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::4 2.701935 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::5 2.680134 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::6 2.730491 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::7 2.705550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 21.615307 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 46503 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3178879082 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 2136 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 2178 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 2231 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 2193 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::4 2115 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::5 2135 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::6 2103 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::7 2206 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 176402.667868 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 172466.495596 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 171159.931235 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 169676.742923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::4 174412.376485 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::5 178006.328485 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::6 177898.511205 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::7 168315.439542 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1388338.493339 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 39999.820703 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 471 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 475 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::2 515 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::3 462 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::4 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::5 485 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::6 452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::7 461 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3752 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 293710442 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.779494 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.781910 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 0.769162 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 0.789330 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::4 0.796217 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::5 0.772834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::6 0.785069 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::7 0.791024 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 6.265041 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1665 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1703 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 1716 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 1731 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::4 1684 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::5 1650 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::6 1651 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::7 1745 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13545 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 59 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 539437582 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 6.313670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 6.191919 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 6.044823 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 6.149567 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::4 6.376359 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::5 6.316628 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::6 6.412744 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::7 6.113327 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 49.919037 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 13486 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1720878838 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 86764 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 86764 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 86764 # number of Writeback hits -system.l2c.Writeback_hits::total 86764 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs 6575.500000 # average number of cycles each access was blocked +system.l2c.WriteReq_mshr_uncacheable_latency 1717678292 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 86531 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 86531 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 86531 # number of Writeback hits +system.l2c.Writeback_hits::total 86531 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.025850 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 22 # number of cycles access was blocked +system.l2c.avg_refs 1.997257 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 144661 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 26600 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 26618 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 26533 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 26842 # number of demand (read+write) accesses -system.l2c.demand_accesses::4 26607 # number of demand (read+write) accesses -system.l2c.demand_accesses::5 26630 # number of demand (read+write) accesses -system.l2c.demand_accesses::6 26517 # number of demand (read+write) accesses -system.l2c.demand_accesses::7 26747 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 213094 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 398760.755929 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 398006.709116 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 401224.669099 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 396429.881860 # average overall miss latency -system.l2c.demand_avg_miss_latency::4 396404.136316 # average overall miss latency -system.l2c.demand_avg_miss_latency::5 396945.495935 # average overall miss latency -system.l2c.demand_avg_miss_latency::6 401462.173836 # average overall miss latency -system.l2c.demand_avg_miss_latency::7 397488.336220 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3186722.158311 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency -system.l2c.demand_hits::0 11293 # number of demand (read+write) hits -system.l2c.demand_hits::1 11282 # number of demand (read+write) hits -system.l2c.demand_hits::2 11320 # number of demand (read+write) hits -system.l2c.demand_hits::3 11445 # number of demand (read+write) hits -system.l2c.demand_hits::4 11209 # number of demand (read+write) hits -system.l2c.demand_hits::5 11253 # number of demand (read+write) hits -system.l2c.demand_hits::6 11313 # number of demand (read+write) hits -system.l2c.demand_hits::7 11391 # number of demand (read+write) hits -system.l2c.demand_hits::total 90506 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6103830891 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.575451 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.576151 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.573361 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.573616 # miss rate for demand accesses -system.l2c.demand_miss_rate::4 0.578720 # miss rate for demand accesses -system.l2c.demand_miss_rate::5 0.577431 # miss rate for demand accesses -system.l2c.demand_miss_rate::6 0.573368 # miss rate for demand accesses -system.l2c.demand_miss_rate::7 0.574120 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 4.602220 # miss rate for demand accesses -system.l2c.demand_misses::0 15307 # number of demand (read+write) misses -system.l2c.demand_misses::1 15336 # number of demand (read+write) misses -system.l2c.demand_misses::2 15213 # number of demand (read+write) misses -system.l2c.demand_misses::3 15397 # number of demand (read+write) misses -system.l2c.demand_misses::4 15398 # number of demand (read+write) misses -system.l2c.demand_misses::5 15377 # number of demand (read+write) misses -system.l2c.demand_misses::6 15204 # number of demand (read+write) misses -system.l2c.demand_misses::7 15356 # number of demand (read+write) misses -system.l2c.demand_misses::total 122588 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1626 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 4838535294 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 4.547444 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 4.544368 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 4.558927 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 4.506445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::4 4.546247 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::5 4.542321 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::6 4.561677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::7 4.522451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 36.329880 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 120962 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 26536 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 26668 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 26629 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 26357 # number of demand (read+write) accesses +system.l2c.demand_accesses::4 26543 # number of demand (read+write) accesses +system.l2c.demand_accesses::5 26596 # number of demand (read+write) accesses +system.l2c.demand_accesses::6 26431 # number of demand (read+write) accesses +system.l2c.demand_accesses::7 26654 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 212414 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 401055.880030 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 395148.786060 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 399337.327545 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 398677.959397 # average overall miss latency +system.l2c.demand_avg_miss_latency::4 398797.682508 # average overall miss latency +system.l2c.demand_avg_miss_latency::5 398558.308148 # average overall miss latency +system.l2c.demand_avg_miss_latency::6 397217.163763 # average overall miss latency +system.l2c.demand_avg_miss_latency::7 396653.608946 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3185446.716395 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40001.294740 # average overall mshr miss latency +system.l2c.demand_hits::0 13291 # number of demand (read+write) hits +system.l2c.demand_hits::1 13225 # number of demand (read+write) hits +system.l2c.demand_hits::2 13327 # number of demand (read+write) hits +system.l2c.demand_hits::3 13033 # number of demand (read+write) hits +system.l2c.demand_hits::4 13223 # number of demand (read+write) hits +system.l2c.demand_hits::5 13268 # number of demand (read+write) hits +system.l2c.demand_hits::6 13058 # number of demand (read+write) hits +system.l2c.demand_hits::7 13262 # number of demand (read+write) hits +system.l2c.demand_hits::total 105687 # number of demand (read+write) hits +system.l2c.demand_miss_latency 5311985131 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.499133 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.504087 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.499531 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.505520 # miss rate for demand accesses +system.l2c.demand_miss_rate::4 0.501827 # miss rate for demand accesses +system.l2c.demand_miss_rate::5 0.501128 # miss rate for demand accesses +system.l2c.demand_miss_rate::6 0.505959 # miss rate for demand accesses +system.l2c.demand_miss_rate::7 0.502439 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 4.019624 # miss rate for demand accesses +system.l2c.demand_misses::0 13245 # number of demand (read+write) misses +system.l2c.demand_misses::1 13443 # number of demand (read+write) misses +system.l2c.demand_misses::2 13302 # number of demand (read+write) misses +system.l2c.demand_misses::3 13324 # number of demand (read+write) misses +system.l2c.demand_misses::4 13320 # number of demand (read+write) misses +system.l2c.demand_misses::5 13328 # number of demand (read+write) misses +system.l2c.demand_misses::6 13373 # number of demand (read+write) misses +system.l2c.demand_misses::7 13392 # number of demand (read+write) misses +system.l2c.demand_misses::total 106727 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1546 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4207376182 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 3.963710 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 3.944090 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 3.949867 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 3.990629 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::4 3.962664 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::5 3.954768 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::6 3.979456 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::7 3.946162 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 31.691345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 105181 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.025853 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.026694 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.026105 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.026914 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.026038 # Average percentage of cache occupancy -system.l2c.occ_%::5 0.026270 # Average percentage of cache occupancy -system.l2c.occ_%::6 0.025331 # Average percentage of cache occupancy -system.l2c.occ_%::7 0.026254 # Average percentage of cache occupancy -system.l2c.occ_%::8 0.409154 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 26.473544 # Average occupied blocks per context -system.l2c.occ_blocks::1 27.334486 # Average occupied blocks per context -system.l2c.occ_blocks::2 26.731121 # Average occupied blocks per context -system.l2c.occ_blocks::3 27.560151 # Average occupied blocks per context -system.l2c.occ_blocks::4 26.663054 # Average occupied blocks per context -system.l2c.occ_blocks::5 26.900488 # Average occupied blocks per context -system.l2c.occ_blocks::6 25.938523 # Average occupied blocks per context -system.l2c.occ_blocks::7 26.884287 # Average occupied blocks per context -system.l2c.occ_blocks::8 418.973617 # Average occupied blocks per context -system.l2c.overall_accesses::0 26600 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 26618 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 26533 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 26842 # number of overall (read+write) accesses -system.l2c.overall_accesses::4 26607 # number of overall (read+write) accesses -system.l2c.overall_accesses::5 26630 # number of overall (read+write) accesses -system.l2c.overall_accesses::6 26517 # number of overall (read+write) accesses -system.l2c.overall_accesses::7 26747 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 213094 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 398760.755929 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 398006.709116 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 401224.669099 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 396429.881860 # average overall miss latency -system.l2c.overall_avg_miss_latency::4 396404.136316 # average overall miss latency -system.l2c.overall_avg_miss_latency::5 396945.495935 # average overall miss latency -system.l2c.overall_avg_miss_latency::6 401462.173836 # average overall miss latency -system.l2c.overall_avg_miss_latency::7 397488.336220 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3186722.158311 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency +system.l2c.occ_%::0 0.025373 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.025977 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.026279 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.025685 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.025981 # Average percentage of cache occupancy +system.l2c.occ_%::5 0.026528 # Average percentage of cache occupancy +system.l2c.occ_%::6 0.026219 # Average percentage of cache occupancy +system.l2c.occ_%::7 0.025911 # Average percentage of cache occupancy +system.l2c.occ_%::8 0.410377 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 25.981879 # Average occupied blocks per context +system.l2c.occ_blocks::1 26.600597 # Average occupied blocks per context +system.l2c.occ_blocks::2 26.909195 # Average occupied blocks per context +system.l2c.occ_blocks::3 26.301014 # Average occupied blocks per context +system.l2c.occ_blocks::4 26.604829 # Average occupied blocks per context +system.l2c.occ_blocks::5 27.164696 # Average occupied blocks per context +system.l2c.occ_blocks::6 26.848001 # Average occupied blocks per context +system.l2c.occ_blocks::7 26.532744 # Average occupied blocks per context +system.l2c.occ_blocks::8 420.226520 # Average occupied blocks per context +system.l2c.overall_accesses::0 26536 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 26668 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 26629 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 26357 # number of overall (read+write) accesses +system.l2c.overall_accesses::4 26543 # number of overall (read+write) accesses +system.l2c.overall_accesses::5 26596 # number of overall (read+write) accesses +system.l2c.overall_accesses::6 26431 # number of overall (read+write) accesses +system.l2c.overall_accesses::7 26654 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 212414 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 401055.880030 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 395148.786060 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 399337.327545 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 398677.959397 # average overall miss latency +system.l2c.overall_avg_miss_latency::4 398797.682508 # average overall miss latency +system.l2c.overall_avg_miss_latency::5 398558.308148 # average overall miss latency +system.l2c.overall_avg_miss_latency::6 397217.163763 # average overall miss latency +system.l2c.overall_avg_miss_latency::7 396653.608946 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3185446.716395 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40001.294740 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 11293 # number of overall hits -system.l2c.overall_hits::1 11282 # number of overall hits -system.l2c.overall_hits::2 11320 # number of overall hits -system.l2c.overall_hits::3 11445 # number of overall hits -system.l2c.overall_hits::4 11209 # number of overall hits -system.l2c.overall_hits::5 11253 # number of overall hits -system.l2c.overall_hits::6 11313 # number of overall hits -system.l2c.overall_hits::7 11391 # number of overall hits -system.l2c.overall_hits::total 90506 # number of overall hits -system.l2c.overall_miss_latency 6103830891 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.575451 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.576151 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.573361 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.573616 # miss rate for overall accesses -system.l2c.overall_miss_rate::4 0.578720 # miss rate for overall accesses -system.l2c.overall_miss_rate::5 0.577431 # miss rate for overall accesses -system.l2c.overall_miss_rate::6 0.573368 # miss rate for overall accesses -system.l2c.overall_miss_rate::7 0.574120 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 4.602220 # miss rate for overall accesses -system.l2c.overall_misses::0 15307 # number of overall misses -system.l2c.overall_misses::1 15336 # number of overall misses -system.l2c.overall_misses::2 15213 # number of overall misses -system.l2c.overall_misses::3 15397 # number of overall misses -system.l2c.overall_misses::4 15398 # number of overall misses -system.l2c.overall_misses::5 15377 # number of overall misses -system.l2c.overall_misses::6 15204 # number of overall misses -system.l2c.overall_misses::7 15356 # number of overall misses -system.l2c.overall_misses::total 122588 # number of overall misses -system.l2c.overall_mshr_hits 1626 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 4838535294 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 4.547444 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 4.544368 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 4.558927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 4.506445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::4 4.546247 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::5 4.542321 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::6 4.561677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::7 4.522451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 36.329880 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 120962 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 4905275071 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 13291 # number of overall hits +system.l2c.overall_hits::1 13225 # number of overall hits +system.l2c.overall_hits::2 13327 # number of overall hits +system.l2c.overall_hits::3 13033 # number of overall hits +system.l2c.overall_hits::4 13223 # number of overall hits +system.l2c.overall_hits::5 13268 # number of overall hits +system.l2c.overall_hits::6 13058 # number of overall hits +system.l2c.overall_hits::7 13262 # number of overall hits +system.l2c.overall_hits::total 105687 # number of overall hits +system.l2c.overall_miss_latency 5311985131 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.499133 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.504087 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.499531 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.505520 # miss rate for overall accesses +system.l2c.overall_miss_rate::4 0.501827 # miss rate for overall accesses +system.l2c.overall_miss_rate::5 0.501128 # miss rate for overall accesses +system.l2c.overall_miss_rate::6 0.505959 # miss rate for overall accesses +system.l2c.overall_miss_rate::7 0.502439 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 4.019624 # miss rate for overall accesses +system.l2c.overall_misses::0 13245 # number of overall misses +system.l2c.overall_misses::1 13443 # number of overall misses +system.l2c.overall_misses::2 13302 # number of overall misses +system.l2c.overall_misses::3 13324 # number of overall misses +system.l2c.overall_misses::4 13320 # number of overall misses +system.l2c.overall_misses::5 13328 # number of overall misses +system.l2c.overall_misses::6 13373 # number of overall misses +system.l2c.overall_misses::7 13392 # number of overall misses +system.l2c.overall_misses::total 106727 # number of overall misses +system.l2c.overall_mshr_hits 1546 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4207376182 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 3.963710 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 3.944090 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 3.949867 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 3.990629 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::4 3.962664 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::5 3.954768 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::6 3.979456 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::7 3.946162 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 31.691345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 105181 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4896557374 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 72848 # number of replacements -system.l2c.sampled_refs 73502 # Sample count of references to valid blocks. +system.l2c.replacements 73319 # number of replacements +system.l2c.sampled_refs 73994 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.459270 # Cycle average of tags in use -system.l2c.total_refs 148904 # Total number of references to valid blocks. +system.l2c.tagsinuse 633.169475 # Cycle average of tags in use +system.l2c.total_refs 147785 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 46916 # number of writebacks |