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-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt514
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt987
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt961
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt1077
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt1077
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt490
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt878
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt977
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt508
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt861
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt1273
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt512
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt968
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt730
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt2844
15 files changed, 6963 insertions, 7694 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index ecf052997..823f9b4c3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19841500 # Number of ticks simulated
-final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 18769500 # Number of ticks simulated
+final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31060 # Simulator instruction rate (inst/s)
-host_op_rate 31057 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96425663 # Simulator tick rate (ticks/s)
-host_mem_usage 216044 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 10228 # Simulator instruction rate (inst/s)
+host_op_rate 10227 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30039955 # Simulator tick rate (ticks/s)
+host_mem_usage 216300 # Number of bytes of host memory used
+host_seconds 0.62 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19827000 # Total gap between requests
+system.physmem.totGap 18755000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1719468 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests
+system.physmem.totQLat 1862969 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests
system.physmem.totBusLat 1876000 # Total cycles spent in databus access
-system.physmem.totBankLat 7868000 # Total cycles spent in bank access
-system.physmem.avgQLat 3666.24 # Average queueing delay per request
-system.physmem.avgBankLat 16776.12 # Average bank access latency per request
+system.physmem.totBankLat 7924000 # Total cycles spent in bank access
+system.physmem.avgQLat 3972.22 # Average queueing delay per request
+system.physmem.avgBankLat 16895.52 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24442.36 # Average memory access latency
-system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24867.74 # Average memory access latency
+system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.43 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.58 # Average read queue length over time
+system.physmem.busUtil 9.97 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.62 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 401 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42275.05 # Average gap between requests
+system.physmem.avgGap 39989.34 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1184 # DTB read hits
+system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1191 # DTB read accesses
-system.cpu.dtb.write_hits 900 # DTB write hits
+system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 903 # DTB write accesses
-system.cpu.dtb.data_hits 2084 # DTB hits
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2094 # DTB accesses
-system.cpu.itb.fetch_hits 908 # ITB hits
+system.cpu.dtb.data_accesses 2058 # DTB accesses
+system.cpu.itb.fetch_hits 909 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 925 # ITB accesses
+system.cpu.itb.fetch_accesses 926 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 39684 # number of cpu cycles simulated
+system.cpu.numCycles 37540 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
+system.cpu.branch_predictor.lookups 1605 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1142 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5205 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 9772 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 2961 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2181 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 4463 # Number of Instructions Executed.
+system.cpu.execution_unit.executions 4462 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 7402 # Number of cycles cpu stages are processed.
-system.cpu.activity 18.652354 # Percentage of cycles cpu is active
+system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 7397 # Number of cycles cpu stages are processed.
+system.cpu.activity 19.704315 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
@@ -265,144 +265,144 @@ system.cpu.committedInsts 6390 # Nu
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
-system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use
-system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use
+system.cpu.icache.total_refs 556 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
-system.cpu.icache.overall_hits::total 558 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
-system.cpu.icache.overall_misses::total 350 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits
+system.cpu.icache.overall_hits::total 556 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses
+system.cpu.icache.overall_misses::total 353 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles
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@@ -413,36 +413,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2048
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
@@ -451,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
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@@ -467,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
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system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -504,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
@@ -537,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -567,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
@@ -589,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index d5736f11f..fb45a6f1f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,51 +1,51 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 11568000 # Number of ticks simulated
-final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 15653000 # Number of ticks simulated
+final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27765 # Simulator instruction rate (inst/s)
-host_op_rate 27764 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50400871 # Simulator tick rate (ticks/s)
-host_mem_usage 217072 # Number of bytes of host memory used
-host_seconds 0.23 # Real time elapsed on the host
+host_inst_rate 11804 # Simulator instruction rate (inst/s)
+host_op_rate 11803 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28994780 # Simulator tick rate (ticks/s)
+host_mem_usage 217308 # Number of bytes of host memory used
+host_seconds 0.54 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
+system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 486 # Total number of read requests seen
+system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 487 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 31104 # Total number of bytes read from memory
+system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 31168 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 11441000 # Total gap between requests
+system.physmem.totGap 15508000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 486 # Categorize read packet sizes
+system.physmem.readPktSize::6 487 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3089486 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests
-system.physmem.totBusLat 1944000 # Total cycles spent in databus access
-system.physmem.totBankLat 7560000 # Total cycles spent in bank access
-system.physmem.avgQLat 6356.97 # Average queueing delay per request
-system.physmem.avgBankLat 15555.56 # Average bank access latency per request
+system.physmem.totQLat 2668987 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests
+system.physmem.totBusLat 1948000 # Total cycles spent in databus access
+system.physmem.totBankLat 7798000 # Total cycles spent in bank access
+system.physmem.avgQLat 5480.47 # Average queueing delay per request
+system.physmem.avgBankLat 16012.32 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25912.52 # Average memory access latency
-system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25492.79 # Average memory access latency
+system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 16.80 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.09 # Average read queue length over time
+system.physmem.busUtil 12.44 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 416 # Number of row buffer hits during reads
+system.physmem.readRowHits 417 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 23541.15 # Average gap between requests
+system.physmem.avgGap 31843.94 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1960 # DTB read hits
+system.cpu.dtb.read_hits 2048 # DTB read hits
system.cpu.dtb.read_misses 58 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2018 # DTB read accesses
-system.cpu.dtb.write_hits 1076 # DTB write hits
+system.cpu.dtb.read_accesses 2106 # DTB read accesses
+system.cpu.dtb.write_hits 1074 # DTB write hits
system.cpu.dtb.write_misses 32 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1108 # DTB write accesses
-system.cpu.dtb.data_hits 3036 # DTB hits
+system.cpu.dtb.write_accesses 1106 # DTB write accesses
+system.cpu.dtb.data_hits 3122 # DTB hits
system.cpu.dtb.data_misses 90 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3126 # DTB accesses
-system.cpu.itb.fetch_hits 2261 # ITB hits
+system.cpu.dtb.data_accesses 3212 # DTB accesses
+system.cpu.itb.fetch_hits 2395 # ITB hits
system.cpu.itb.fetch_misses 38 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2299 # ITB accesses
+system.cpu.itb.fetch_accesses 2433 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -218,244 +218,243 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 23137 # number of cpu cycles simulated
+system.cpu.numCycles 31307 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2774 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2894 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2667 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2779 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2538 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups
+system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2656 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename
+system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 34 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10392 # Type of FU issued
-system.cpu.iq.rate 0.449151 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10660 # Type of FU issued
+system.cpu.iq.rate 0.340499 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 114 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 86 # number of nop insts executed
-system.cpu.iew.exec_refs 3139 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1600 # Number of branches executed
-system.cpu.iew.exec_stores 1110 # Number of stores executed
-system.cpu.iew.exec_rate 0.426373 # Inst execution rate
-system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9479 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5022 # num instructions producing a value
-system.cpu.iew.wb_consumers 6814 # num instructions consuming a value
+system.cpu.iew.exec_nop 88 # number of nop insts executed
+system.cpu.iew.exec_refs 3225 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1609 # Number of branches executed
+system.cpu.iew.exec_stores 1108 # Number of stores executed
+system.cpu.iew.exec_rate 0.319833 # Inst execution rate
+system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9555 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5016 # num instructions producing a value
+system.cpu.iew.wb_consumers 6802 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -466,70 +465,70 @@ system.cpu.commit.branches 1050 # Nu
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 24559 # The number of ROB reads
-system.cpu.rob.rob_writes 26483 # The number of ROB writes
-system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 25734 # The number of ROB reads
+system.cpu.rob.rob_writes 27303 # The number of ROB writes
+system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12554 # number of integer regfile reads
-system.cpu.int_regfile_writes 7112 # number of integer regfile writes
+system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12695 # number of integer regfile reads
+system.cpu.int_regfile_writes 7186 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use
-system.cpu.icache.total_refs 1827 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use
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system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 1827 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 434 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13420000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13420000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13420000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 13420000 # number of overall miss cycles
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-system.cpu.icache.overall_miss_rate::total 0.191950 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30921.658986 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30921.658986 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30921.658986 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30921.658986 # average overall miss latency
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+system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles
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+system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses
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@@ -538,154 +537,154 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 220.821936 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 160.499801 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 60.322135 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004898 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006739 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 60.430298 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004899 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -693,60 +692,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 100 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses
-system.cpu.l2cache.overall_misses::total 486 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10016000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4131000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 14147000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2238500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2238500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 10016000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6369500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 10016000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6369500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 16385500 # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
+system.cpu.l2cache.overall_misses::total 487 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5921000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 20902000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3727500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9648500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 24629500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 14981000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9648500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 24629500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 100 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41310 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34254.237288 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 30664.383562 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 30664.383562 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 33715.020576 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 33715.020576 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47862.619808 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58623.762376 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 50487.922705 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51061.643836 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51061.643836 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50573.921971 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50573.921971 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -756,49 +755,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 100 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8904460 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3801580 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12706040 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2007032 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2007032 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8904460 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5808612 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14713072 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8904460 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5808612 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14713072 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11042494 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4678584 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2834058 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2834058 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7512642 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11042494 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7512642 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18555136 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37973.618357 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38822.712329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38822.712329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index d5e0f20d7..9eea9fb92 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 6408000 # Number of ticks simulated
-final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000009 # Number of seconds simulated
+sim_ticks 9061000 # Number of ticks simulated
+final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 494 # Simulator instruction rate (inst/s)
-host_op_rate 494 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1327192 # Simulator tick rate (ticks/s)
-host_mem_usage 215760 # Number of bytes of host memory used
-host_seconds 4.83 # Real time elapsed on the host
+host_inst_rate 62320 # Simulator instruction rate (inst/s)
+host_op_rate 62299 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 236406021 # Simulator tick rate (ticks/s)
+host_mem_usage 216020 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
-system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 273 # Total number of read requests seen
+system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 272 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 17472 # Total number of bytes read from memory
+system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 17408 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -47,7 +47,7 @@ system.physmem.perBankRdReqs::7 23 # Tr
system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 6357500 # Total gap between requests
+system.physmem.totGap 8992500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 273 # Categorize read packet sizes
+system.physmem.readPktSize::6 272 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1341773 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests
-system.physmem.totBusLat 1092000 # Total cycles spent in databus access
+system.physmem.totQLat 1105772 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests
+system.physmem.totBusLat 1088000 # Total cycles spent in databus access
system.physmem.totBankLat 4620000 # Total cycles spent in bank access
-system.physmem.avgQLat 4914.92 # Average queueing delay per request
-system.physmem.avgBankLat 16923.08 # Average bank access latency per request
+system.physmem.avgQLat 4065.34 # Average queueing delay per request
+system.physmem.avgBankLat 16985.29 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25838.00 # Average memory access latency
-system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25050.63 # Average memory access latency
+system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 17.04 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.10 # Average read queue length over time
+system.physmem.busUtil 12.01 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.75 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 229 # Number of row buffer hits during reads
+system.physmem.readRowHits 228 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 23287.55 # Average gap between requests
+system.physmem.avgGap 33060.66 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 718 # DTB read hits
-system.cpu.dtb.read_misses 36 # DTB read misses
+system.cpu.dtb.read_hits 743 # DTB read hits
+system.cpu.dtb.read_misses 38 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 754 # DTB read accesses
-system.cpu.dtb.write_hits 382 # DTB write hits
+system.cpu.dtb.read_accesses 781 # DTB read accesses
+system.cpu.dtb.write_hits 387 # DTB write hits
system.cpu.dtb.write_misses 24 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 406 # DTB write accesses
-system.cpu.dtb.data_hits 1100 # DTB hits
-system.cpu.dtb.data_misses 60 # DTB misses
+system.cpu.dtb.write_accesses 411 # DTB write accesses
+system.cpu.dtb.data_hits 1130 # DTB hits
+system.cpu.dtb.data_misses 62 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1160 # DTB accesses
-system.cpu.itb.fetch_hits 1042 # ITB hits
+system.cpu.dtb.data_accesses 1192 # DTB accesses
+system.cpu.itb.fetch_hits 1097 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 1072 # ITB accesses
+system.cpu.itb.fetch_accesses 1127 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -218,244 +218,245 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 12817 # number of cpu cycles simulated
+system.cpu.numCycles 18123 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 1162 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits
+system.cpu.BPredUnit.lookups 1200 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1173 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1083 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1207 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1119 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 4204 # Type of FU issued
-system.cpu.iq.rate 0.328002 # Inst issue rate
+system.cpu.iq.FU_type_0::total 4254 # Type of FU issued
+system.cpu.iq.rate 0.234729 # Inst issue rate
system.cpu.iq.fu_busy_cnt 47 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 353 # number of nop insts executed
-system.cpu.iew.exec_refs 1161 # number of memory reference insts executed
-system.cpu.iew.exec_branches 678 # Number of branches executed
-system.cpu.iew.exec_stores 406 # Number of stores executed
-system.cpu.iew.exec_rate 0.312944 # Inst execution rate
-system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3827 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1795 # num instructions producing a value
-system.cpu.iew.wb_consumers 2353 # num instructions consuming a value
+system.cpu.iew.exec_nop 363 # number of nop insts executed
+system.cpu.iew.exec_refs 1193 # number of memory reference insts executed
+system.cpu.iew.exec_branches 672 # Number of branches executed
+system.cpu.iew.exec_stores 411 # Number of stores executed
+system.cpu.iew.exec_rate 0.223087 # Inst execution rate
+system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3836 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1789 # num instructions producing a value
+system.cpu.iew.wb_consumers 2358 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -466,181 +467,181 @@ system.cpu.commit.branches 396 # Nu
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 11717 # The number of ROB reads
-system.cpu.rob.rob_writes 11541 # The number of ROB writes
-system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 12367 # The number of ROB reads
+system.cpu.rob.rob_writes 11843 # The number of ROB writes
+system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4858 # number of integer regfile reads
-system.cpu.int_regfile_writes 2964 # number of integer regfile writes
+system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 122d34e0f..ccb8279d9 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,47 +1,47 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10062000 # Number of ticks simulated
-final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000013 # Number of seconds simulated
+sim_ticks 13414500 # Number of ticks simulated
+final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57856 # Simulator instruction rate (inst/s)
-host_op_rate 72170 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 126623534 # Simulator tick rate (ticks/s)
-host_mem_usage 231188 # Number of bytes of host memory used
+host_inst_rate 59216 # Simulator instruction rate (inst/s)
+host_op_rate 73866 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 172781643 # Simulator tick rate (ticks/s)
+host_mem_usage 231444 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 398 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 398 # Total number of read requests seen
+system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 401 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25472 # Total number of bytes read from memory
+system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25600 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
@@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 10004500 # Total gap between requests
+system.physmem.totGap 13356500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 398 # Categorize read packet sizes
+system.physmem.readPktSize::6 401 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2567898 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests
-system.physmem.totBusLat 1592000 # Total cycles spent in databus access
-system.physmem.totBankLat 6552000 # Total cycles spent in bank access
-system.physmem.avgQLat 6452.01 # Average queueing delay per request
-system.physmem.avgBankLat 16462.31 # Average bank access latency per request
+system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
+system.physmem.totBusLat 1604000 # Total cycles spent in databus access
+system.physmem.totBankLat 6636000 # Total cycles spent in bank access
+system.physmem.avgQLat 6227.93 # Average queueing delay per request
+system.physmem.avgBankLat 16548.63 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26914.32 # Average memory access latency
-system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26776.56 # Average memory access latency
+system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.82 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.06 # Average read queue length over time
+system.physmem.busUtil 11.93 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.80 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 323 # Number of row buffer hits during reads
+system.physmem.readRowHits 326 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25136.93 # Average gap between requests
+system.physmem.avgGap 33307.98 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
@@ -273,243 +273,245 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 20125 # number of cpu cycles simulated
+system.cpu.numCycles 26830 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2519 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2441 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2242 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 46 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer
+system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle
+system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8888 # Type of FU issued
-system.cpu.iq.rate 0.441640 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
+system.cpu.iq.rate 0.331569 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3261 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1428 # Number of branches executed
-system.cpu.iew.exec_stores 1173 # Number of stores executed
-system.cpu.iew.exec_rate 0.421615 # Inst execution rate
-system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8062 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3862 # num instructions producing a value
-system.cpu.iew.wb_consumers 7771 # num instructions consuming a value
+system.cpu.iew.exec_nop 1 # number of nop insts executed
+system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1437 # Number of branches executed
+system.cpu.iew.exec_stores 1174 # Number of stores executed
+system.cpu.iew.exec_rate 0.316996 # Inst execution rate
+system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3897 # num instructions producing a value
+system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle
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@@ -520,307 +522,307 @@ system.cpu.commit.branches 1008 # Nu
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+system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.863014 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.916100 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942373 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.863014 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.916100 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31741.007194 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37089.285714 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 32982.044199 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44666.666667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44666.666667 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34196.782178 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34196.782178 # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -829,59 +831,56 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index f60a54b23..62de1d1aa 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,47 +1,47 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10062000 # Number of ticks simulated
-final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000013 # Number of seconds simulated
+sim_ticks 13414500 # Number of ticks simulated
+final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70596 # Simulator instruction rate (inst/s)
-host_op_rate 88057 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 154493805 # Simulator tick rate (ticks/s)
-host_mem_usage 230168 # Number of bytes of host memory used
+host_inst_rate 64991 # Simulator instruction rate (inst/s)
+host_op_rate 81070 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 189628588 # Simulator tick rate (ticks/s)
+host_mem_usage 230428 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25472 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 398 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 398 # Total number of read requests seen
+system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 401 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25472 # Total number of bytes read from memory
+system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25600 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
@@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 10004500 # Total gap between requests
+system.physmem.totGap 13356500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 398 # Categorize read packet sizes
+system.physmem.readPktSize::6 401 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2567898 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests
-system.physmem.totBusLat 1592000 # Total cycles spent in databus access
-system.physmem.totBankLat 6552000 # Total cycles spent in bank access
-system.physmem.avgQLat 6452.01 # Average queueing delay per request
-system.physmem.avgBankLat 16462.31 # Average bank access latency per request
+system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
+system.physmem.totBusLat 1604000 # Total cycles spent in databus access
+system.physmem.totBankLat 6636000 # Total cycles spent in bank access
+system.physmem.avgQLat 6227.93 # Average queueing delay per request
+system.physmem.avgBankLat 16548.63 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26914.32 # Average memory access latency
-system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26776.56 # Average memory access latency
+system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.82 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.06 # Average read queue length over time
+system.physmem.busUtil 11.93 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.80 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 323 # Number of row buffer hits during reads
+system.physmem.readRowHits 326 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25136.93 # Average gap between requests
+system.physmem.avgGap 33307.98 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -228,243 +228,245 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 20125 # number of cpu cycles simulated
+system.cpu.numCycles 26830 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2519 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2441 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2242 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 46 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer
+system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle
+system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8888 # Type of FU issued
-system.cpu.iq.rate 0.441640 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
+system.cpu.iq.rate 0.331569 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3261 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1428 # Number of branches executed
-system.cpu.iew.exec_stores 1173 # Number of stores executed
-system.cpu.iew.exec_rate 0.421615 # Inst execution rate
-system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8062 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3862 # num instructions producing a value
-system.cpu.iew.wb_consumers 7771 # num instructions consuming a value
+system.cpu.iew.exec_nop 1 # number of nop insts executed
+system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1437 # Number of branches executed
+system.cpu.iew.exec_stores 1174 # Number of stores executed
+system.cpu.iew.exec_rate 0.316996 # Inst execution rate
+system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3897 # num instructions producing a value
+system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4596 # Number of instructions committed
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -475,307 +477,307 @@ system.cpu.commit.branches 1008 # Nu
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22426 # The number of ROB reads
-system.cpu.rob.rob_writes 23541 # The number of ROB writes
-system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23385 # The number of ROB reads
+system.cpu.rob.rob_writes 23680 # The number of ROB writes
+system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39006 # number of integer regfile reads
-system.cpu.int_regfile_writes 7962 # number of integer regfile writes
+system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39120 # number of integer regfile reads
+system.cpu.int_regfile_writes 7969 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15230 # number of misc regfile reads
+system.cpu.misc_regfile_reads 15172 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use
-system.cpu.icache.total_refs 1592 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use
+system.cpu.icache.total_refs 1570 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits
-system.cpu.icache.overall_hits::total 1592 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses
-system.cpu.icache.overall_misses::total 358 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 1570 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses
+system.cpu.icache.overall_misses::total 373 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles
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-system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 8aae2e3f0..02dd2c613 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 19373000 # Number of ticks simulated
-final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 18578000 # Number of ticks simulated
+final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54522 # Simulator instruction rate (inst/s)
-host_op_rate 54510 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 181593348 # Simulator tick rate (ticks/s)
-host_mem_usage 216696 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 97793 # Simulator instruction rate (inst/s)
+host_op_rate 97754 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 312246493 # Simulator tick rate (ticks/s)
+host_mem_usage 216964 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19298000 # Total gap between requests
+system.physmem.totGap 18503000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2404453 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests
+system.physmem.totQLat 2353954 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests
system.physmem.totBusLat 1820000 # Total cycles spent in databus access
-system.physmem.totBankLat 8470000 # Total cycles spent in bank access
-system.physmem.avgQLat 5284.51 # Average queueing delay per request
-system.physmem.avgBankLat 18615.38 # Average bank access latency per request
+system.physmem.totBankLat 8484000 # Total cycles spent in bank access
+system.physmem.avgQLat 5173.53 # Average queueing delay per request
+system.physmem.avgBankLat 18646.15 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27899.90 # Average memory access latency
-system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 27819.68 # Average memory access latency
+system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.39 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.66 # Average read queue length over time
+system.physmem.busUtil 9.80 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.68 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 357 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42413.19 # Average gap between requests
+system.physmem.avgGap 40665.93 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -204,7 +204,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 38747 # number of cpu cycles simulated
+system.cpu.numCycles 37157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
@@ -217,13 +217,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu
system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2235 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken).
@@ -234,12 +234,12 @@ system.cpu.execution_unit.executions 3144 # Nu
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 5385 # Number of cycles cpu stages are processed.
-system.cpu.activity 13.897850 # Percentage of cycles cpu is active
+system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 5375 # Number of cycles cpu stages are processed.
+system.cpu.activity 14.465646 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
@@ -251,144 +251,144 @@ system.cpu.committedInsts 5814 # Nu
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
-system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use
system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits
system.cpu.icache.overall_hits::total 410 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
-system.cpu.icache.overall_misses::total 344 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses
+system.cpu.icache.overall_misses::total 346 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses
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system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@@ -397,38 +397,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 #
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
@@ -437,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
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@@ -453,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
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system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@@ -490,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@@ -523,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -553,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
@@ -575,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 85090bc10..7222464d9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12097500 # Number of ticks simulated
-final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 16437500 # Number of ticks simulated
+final_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46391 # Simulator instruction rate (inst/s)
-host_op_rate 46381 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 108798708 # Simulator tick rate (ticks/s)
-host_mem_usage 217720 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 79981 # Simulator instruction rate (inst/s)
+host_op_rate 79951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 254800448 # Simulator tick rate (ticks/s)
+host_mem_usage 217976 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21696 # Nu
system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 480 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 12035000 # Total gap between requests
+system.physmem.totGap 16357500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3039980 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests
+system.physmem.totQLat 2266480 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests
system.physmem.totBusLat 1920000 # Total cycles spent in databus access
-system.physmem.totBankLat 8708000 # Total cycles spent in bank access
-system.physmem.avgQLat 6333.29 # Average queueing delay per request
-system.physmem.avgBankLat 18141.67 # Average bank access latency per request
+system.physmem.totBankLat 8764000 # Total cycles spent in bank access
+system.physmem.avgQLat 4721.83 # Average queueing delay per request
+system.physmem.avgBankLat 18258.33 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28474.96 # Average memory access latency
-system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26980.17 # Average memory access latency
+system.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.87 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.13 # Average read queue length over time
+system.physmem.busUtil 11.68 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 380 # Number of row buffer hits during reads
+system.physmem.readRowHits 378 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25072.92 # Average gap between requests
+system.physmem.avgGap 34078.12 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -204,243 +204,243 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 24196 # number of cpu cycles simulated
+system.cpu.numCycles 32876 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2174 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2145 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 498 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13016 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2145 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2015 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3079 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3062 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2928 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename
-system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups
+system.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2921 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename
+system.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 273 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8231 # Type of FU issued
-system.cpu.iq.rate 0.340180 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 150 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8202 # Type of FU issued
+system.cpu.iq.rate 0.249483 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1455 # number of nop insts executed
-system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1335 # Number of branches executed
-system.cpu.iew.exec_stores 1074 # Number of stores executed
-system.cpu.iew.exec_rate 0.323318 # Inst execution rate
-system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7380 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2890 # num instructions producing a value
-system.cpu.iew.wb_consumers 4129 # num instructions consuming a value
+system.cpu.iew.exec_nop 1465 # number of nop insts executed
+system.cpu.iew.exec_refs 3191 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1342 # Number of branches executed
+system.cpu.iew.exec_stores 1076 # Number of stores executed
+system.cpu.iew.exec_rate 0.238168 # Inst execution rate
+system.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7366 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2870 # num instructions producing a value
+system.cpu.iew.wb_consumers 4099 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.224054 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -451,181 +451,181 @@ system.cpu.commit.branches 915 # Nu
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
system.cpu.commit.function_calls 87 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23113 # The number of ROB reads
-system.cpu.rob.rob_writes 21959 # The number of ROB writes
-system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23557 # The number of ROB reads
+system.cpu.rob.rob_writes 21850 # The number of ROB writes
+system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
-system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10646 # number of integer regfile reads
-system.cpu.int_regfile_writes 5184 # number of integer regfile writes
+system.cpu.cpi 6.376261 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.156832 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10643 # number of integer regfile reads
+system.cpu.int_regfile_writes 5150 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
-system.cpu.misc_regfile_reads 155 # number of misc regfile reads
+system.cpu.misc_regfile_reads 154 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
-system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use
-system.cpu.icache.total_refs 1552 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use
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system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 1552 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 427 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency
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+system.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_miss_latency::cpu.data 8029500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 24720500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses)
@@ -720,17 +720,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49235.988201 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59188.888889 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51324.009324 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52990.196078 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52990.196078 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51501.041667 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51501.041667 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -750,17 +750,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480
system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12421544 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4218076 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16639620 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12421544 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6289130 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18710674 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12421544 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6289130 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18710674 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses
@@ -772,17 +772,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 3c312e713..5e0f9ad46 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10184500 # Number of ticks simulated
-final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000014 # Number of seconds simulated
+sim_ticks 14081500 # Number of ticks simulated
+final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98086 # Simulator instruction rate (inst/s)
-host_op_rate 98064 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 172399568 # Simulator tick rate (ticks/s)
-host_mem_usage 213936 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 87308 # Simulator instruction rate (inst/s)
+host_op_rate 87279 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 212126284 # Simulator tick rate (ticks/s)
+host_mem_usage 214180 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory
-system.physmem.bytes_read::total 29056 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 454 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 454 # Total number of read requests seen
+system.physmem.num_reads::total 453 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 453 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 29056 # Total number of bytes read from memory
+system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28992 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -42,7 +42,7 @@ system.physmem.perBankRdReqs::2 49 # Tr
system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 10067000 # Total gap between requests
+system.physmem.totGap 13946000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 454 # Categorize read packet sizes
+system.physmem.readPktSize::6 453 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2091454 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests
-system.physmem.totBusLat 1816000 # Total cycles spent in databus access
-system.physmem.totBankLat 7406000 # Total cycles spent in bank access
-system.physmem.avgQLat 4606.73 # Average queueing delay per request
-system.physmem.avgBankLat 16312.78 # Average bank access latency per request
+system.physmem.totQLat 1940453 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests
+system.physmem.totBusLat 1812000 # Total cycles spent in databus access
+system.physmem.totBankLat 7462000 # Total cycles spent in bank access
+system.physmem.avgQLat 4283.56 # Average queueing delay per request
+system.physmem.avgBankLat 16472.41 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24919.50 # Average memory access latency
-system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24755.97 # Average memory access latency
+system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 17.83 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.11 # Average read queue length over time
+system.physmem.busUtil 12.87 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.80 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 377 # Number of row buffer hits during reads
+system.physmem.readRowHits 376 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 22174.01 # Average gap between requests
+system.physmem.avgGap 30785.87 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -204,243 +204,244 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
-system.cpu.numCycles 20370 # number of cpu cycles simulated
+system.cpu.numCycles 28164 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2504 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups
+system.cpu.BPredUnit.lookups 2468 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2237 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2090 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2216 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2079 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer
+system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 9314 # Type of FU issued
-system.cpu.iq.rate 0.457241 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 9281 # Type of FU issued
+system.cpu.iq.rate 0.329534 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes
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system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly
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+system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3293 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1392 # Number of branches executed
+system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
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system.cpu.iew.exec_stores 1577 # Number of stores executed
-system.cpu.iew.exec_rate 0.432351 # Inst execution rate
-system.cpu.iew.wb_sent 8605 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8444 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4397 # num instructions producing a value
-system.cpu.iew.wb_consumers 7138 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.312314 # Inst execution rate
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+system.cpu.iew.wb_count 8425 # cumulative count of insts written-back
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.414531 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.615999 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5240 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::stdev 1.355880 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 623 5.91% 92.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 255 2.42% 95.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 41 0.39% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 107 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -451,180 +452,180 @@ system.cpu.commit.branches 1037 # Nu
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.rob.rob_writes 22869 # The number of ROB writes
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-system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 21870 # The number of ROB reads
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+system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
-system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2768500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2768500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16645000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 5785500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22430500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16645000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 5785500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22430500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 412 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 357 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 459 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 357 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 459 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985994 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.987864 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985994 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.989107 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985994 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.989107 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 29803.977273 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37809.090909 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 30885.749386 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42989.361702 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42989.361702 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 32138.766520 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 32138.766520 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47421.652422 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54854.545455 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48428.571429 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58904.255319 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58904.255319 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 49515.452539 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 49515.452539 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -738,50 +739,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 352 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 352 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 352 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9262482 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1897546 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11160028 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1863544 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1863544 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9262482 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3761090 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 13023572 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9262482 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3761090 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 13023572 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12250512 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2337054 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14587566 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2189544 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2189544 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12250512 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4526598 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16777110 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12250512 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4526598 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16777110 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987864 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.989107 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.989107 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 26313.869318 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34500.836364 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 27420.216216 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39649.872340 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39649.872340 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34901.743590 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42491.890909 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35929.965517 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46586.042553 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46586.042553 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 8df237734..0f666ffe1 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000018 # Number of seconds simulated
-sim_ticks 17991500 # Number of ticks simulated
-final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 16282500 # Number of ticks simulated
+final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44971 # Simulator instruction rate (inst/s)
-host_op_rate 44961 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 151823718 # Simulator tick rate (ticks/s)
-host_mem_usage 222708 # Number of bytes of host memory used
+host_inst_rate 46082 # Simulator instruction rate (inst/s)
+host_op_rate 46072 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 140796560 # Simulator tick rate (ticks/s)
+host_mem_usage 222960 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 17940000 # Total gap between requests
+system.physmem.totGap 16231000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -164,48 +164,48 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1964422 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests
+system.physmem.totQLat 2301921 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests
system.physmem.totBusLat 1692000 # Total cycles spent in databus access
-system.physmem.totBankLat 7700000 # Total cycles spent in bank access
-system.physmem.avgQLat 4644.02 # Average queueing delay per request
-system.physmem.avgBankLat 18203.31 # Average bank access latency per request
+system.physmem.totBankLat 7308000 # Total cycles spent in bank access
+system.physmem.avgQLat 5441.89 # Average queueing delay per request
+system.physmem.avgBankLat 17276.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26847.33 # Average memory access latency
-system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26718.49 # Average memory access latency
+system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.40 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.63 # Average read queue length over time
+system.physmem.busUtil 10.39 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.69 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 336 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42411.35 # Average gap between requests
+system.physmem.avgGap 38371.16 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 35984 # number of cpu cycles simulated
+system.cpu.numCycles 32566 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1634 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 1483 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
@@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6224 # Number of cycles cpu stages are processed.
-system.cpu.activity 17.296576 # Percentage of cycles cpu is active
+system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself
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+system.cpu.activity 19.044402 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
@@ -233,144 +233,144 @@ system.cpu.committedInsts 5327 # Nu
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
-system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads
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+system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads
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-system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts).
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-system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts).
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-system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts).
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@@ -381,36 +381,36 @@ system.cpu.dcache.overall_accesses::cpu.data 1388
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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@@ -419,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
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@@ -435,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
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@@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 91efbc873..272509d41 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12009000 # Number of ticks simulated
-final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000015 # Number of seconds simulated
+sim_ticks 15249000 # Number of ticks simulated
+final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 10920 # Simulator instruction rate (inst/s)
-host_op_rate 19780 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24373770 # Simulator tick rate (ticks/s)
-host_mem_usage 225464 # Number of bytes of host memory used
-host_seconds 0.49 # Real time elapsed on the host
+host_inst_rate 41998 # Simulator instruction rate (inst/s)
+host_op_rate 76065 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 119014725 # Simulator tick rate (ticks/s)
+host_mem_usage 225728 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
system.physmem.num_reads::total 450 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 451 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
@@ -46,9 +46,9 @@ system.physmem.perBankRdReqs::6 16 # Tr
system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 11990500 # Total gap between requests
+system.physmem.totGap 15226500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -164,264 +164,265 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3096951 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests
+system.physmem.totQLat 1663951 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests
system.physmem.totBusLat 1804000 # Total cycles spent in databus access
-system.physmem.totBankLat 8540000 # Total cycles spent in bank access
-system.physmem.avgQLat 6866.85 # Average queueing delay per request
-system.physmem.avgBankLat 18935.70 # Average bank access latency per request
+system.physmem.totBankLat 8526000 # Total cycles spent in bank access
+system.physmem.avgQLat 3689.47 # Average queueing delay per request
+system.physmem.avgBankLat 18904.66 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29802.55 # Average memory access latency
-system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26594.13 # Average memory access latency
+system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 14.99 # Data bus utilization in percentage
-system.physmem.avgRdQLen 1.12 # Average read queue length over time
+system.physmem.busUtil 11.80 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 353 # Number of row buffer hits during reads
+system.physmem.readRowHits 354 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 26586.47 # Average gap between requests
+system.physmem.avgGap 33761.64 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 24019 # number of cpu cycles simulated
+system.cpu.numCycles 30499 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3185 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups
+system.cpu.BPredUnit.lookups 3124 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3768 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3665 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3439 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 18260 # Type of FU issued
-system.cpu.iq.rate 0.760231 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 195 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 17998 # Type of FU issued
+system.cpu.iq.rate 0.590118 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 838 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 21339 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1772 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts 717 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 17023 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1944 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 975 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3340 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1687 # Number of branches executed
-system.cpu.iew.exec_stores 1410 # Number of stores executed
-system.cpu.iew.exec_rate 0.716058 # Inst execution rate
-system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 16726 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10734 # num instructions producing a value
-system.cpu.iew.wb_consumers 16630 # num instructions consuming a value
+system.cpu.iew.exec_refs 3334 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1674 # Number of branches executed
+system.cpu.iew.exec_stores 1390 # Number of stores executed
+system.cpu.iew.exec_rate 0.558149 # Inst execution rate
+system.cpu.iew.wb_sent 16747 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 16518 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10593 # num instructions producing a value
+system.cpu.iew.wb_consumers 16382 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.541592 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.646624 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 11593 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 17112 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.569483 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.430880 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 13541 79.13% 79.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1338 7.82% 86.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 619 3.62% 90.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 703 4.11% 94.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 373 2.18% 96.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 140 0.82% 97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 121 0.71% 98.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 74 0.43% 98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 17112 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -432,124 +433,124 @@ system.cpu.commit.branches 1208 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 36753 # The number of ROB reads
-system.cpu.rob.rob_writes 45519 # The number of ROB writes
-system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 38247 # The number of ROB reads
+system.cpu.rob.rob_writes 44659 # The number of ROB writes
+system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.600000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
@@ -612,42 +613,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2981000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6259500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6259500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6259500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6259500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040674 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040674 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3696500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3696500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4079000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4079000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7775500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7775500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7775500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7775500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041667 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.054991 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.054991 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46835.714286 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46835.714286 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39223.684211 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39223.684211 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.055853 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.055853 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52807.142857 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52807.142857 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53671.052632 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53671.052632 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 182.959089 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 179.176449 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002674 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 149.880234 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 33.078855 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004574 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001009 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005583 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 146.139957 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 33.036492 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004460 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005468 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -665,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 451 # nu
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
system.cpu.l2cache.overall_misses::total 451 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10319000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3209500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 13528500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2905000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2905000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 10319000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6114500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 16433500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 10319000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6114500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 16433500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15152000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3773500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18925500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4003000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4003000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 15152000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7776500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22928500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 15152000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7776500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22928500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses)
@@ -698,17 +699,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997788 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49678.688525 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53907.142857 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 50468 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52671.052632 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52671.052632 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50839.246120 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50839.246120 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -728,17 +729,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11317954 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2918074 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14236028 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3040610 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3040610 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11317954 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5958684 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17276638 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11317954 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5958684 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17276638 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
@@ -750,17 +751,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 9ebeed2de..6142b96e8 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 16578000 # Number of ticks simulated
-final_tick 16578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000020 # Number of seconds simulated
+sim_ticks 20334000 # Number of ticks simulated
+final_tick 20334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76899 # Simulator instruction rate (inst/s)
-host_op_rate 76894 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 100012302 # Simulator tick rate (ticks/s)
-host_mem_usage 217664 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 80964 # Simulator instruction rate (inst/s)
+host_op_rate 80958 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 129154883 # Simulator tick rate (ticks/s)
+host_mem_usage 217900 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2412836289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1351188322 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3764024611 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2412836289 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2412836289 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2412836289 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1351188322 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3764024611 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 975 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62656 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 356 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 979 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1960853743 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1120487853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3081341595 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1960853743 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1960853743 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1960853743 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1120487853 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3081341595 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 979 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 62400 # Total number of bytes read from memory
+system.physmem.cpureqs 979 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 62656 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 62656 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -40,15 +40,15 @@ system.physmem.perBankRdReqs::0 73 # Tr
system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 81 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 75 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 76 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 98 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 99 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 76 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16446000 # Total gap between requests
+system.physmem.totGap 20181000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 975 # Categorize read packet sizes
+system.physmem.readPktSize::6 979 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 237 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 340 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 122 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 49 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
@@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 16512475 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 38892475 # Sum of mem lat for all requests
-system.physmem.totBusLat 3900000 # Total cycles spent in databus access
-system.physmem.totBankLat 18480000 # Total cycles spent in bank access
-system.physmem.avgQLat 16935.87 # Average queueing delay per request
-system.physmem.avgBankLat 18953.85 # Average bank access latency per request
+system.physmem.totQLat 11431477 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 34163477 # Sum of mem lat for all requests
+system.physmem.totBusLat 3916000 # Total cycles spent in databus access
+system.physmem.totBankLat 18816000 # Total cycles spent in bank access
+system.physmem.avgQLat 11676.69 # Average queueing delay per request
+system.physmem.avgBankLat 19219.61 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 39889.72 # Average memory access latency
-system.physmem.avgRdBW 3764.02 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 34896.30 # Average memory access latency
+system.physmem.avgRdBW 3081.34 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3764.02 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3081.34 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 23.53 # Data bus utilization in percentage
-system.physmem.avgRdQLen 2.35 # Average read queue length over time
+system.physmem.busUtil 19.26 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.68 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 738 # Number of row buffer hits during reads
+system.physmem.readRowHits 740 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.59 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 16867.69 # Average gap between requests
+system.physmem.avgGap 20613.89 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4074 # DTB read hits
-system.cpu.dtb.read_misses 101 # DTB read misses
+system.cpu.dtb.read_hits 4607 # DTB read hits
+system.cpu.dtb.read_misses 109 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4175 # DTB read accesses
-system.cpu.dtb.write_hits 2120 # DTB write hits
-system.cpu.dtb.write_misses 61 # DTB write misses
+system.cpu.dtb.read_accesses 4716 # DTB read accesses
+system.cpu.dtb.write_hits 2105 # DTB write hits
+system.cpu.dtb.write_misses 77 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2181 # DTB write accesses
-system.cpu.dtb.data_hits 6194 # DTB hits
-system.cpu.dtb.data_misses 162 # DTB misses
+system.cpu.dtb.write_accesses 2182 # DTB write accesses
+system.cpu.dtb.data_hits 6712 # DTB hits
+system.cpu.dtb.data_misses 186 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6356 # DTB accesses
-system.cpu.itb.fetch_hits 5134 # ITB hits
-system.cpu.itb.fetch_misses 54 # ITB misses
+system.cpu.dtb.data_accesses 6898 # DTB accesses
+system.cpu.itb.fetch_hits 5687 # ITB hits
+system.cpu.itb.fetch_misses 59 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5188 # ITB accesses
+system.cpu.itb.fetch_accesses 5746 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -219,359 +219,358 @@ system.cpu.itb.data_acv 0 # DT
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 33157 # number of cpu cycles simulated
+system.cpu.numCycles 40669 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6335 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3524 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1643 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4675 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 824 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6981 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3954 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1690 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 5146 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 870 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 962 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 181 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 1485 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 35462 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6335 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1786 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 5973 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1719 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5134 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 754 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 24653 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.438446 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.812361 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 937 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 1717 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 38666 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6981 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1807 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 6508 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2004 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 376 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5687 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 27168 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.423218 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.808405 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18680 75.77% 75.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 457 1.85% 77.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 358 1.45% 79.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 502 2.04% 81.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 454 1.84% 82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 361 1.46% 84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 481 1.95% 86.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 604 2.45% 88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2756 11.18% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 20660 76.05% 76.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 537 1.98% 78.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 399 1.47% 79.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 504 1.86% 81.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 464 1.71% 83.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 436 1.60% 84.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 485 1.79% 86.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 591 2.18% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3092 11.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 24653 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.191061 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.069518 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34329 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 6707 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5019 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 579 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2403 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 637 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 388 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 30928 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 701 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2403 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34978 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3976 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 854 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4893 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1933 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 28789 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1945 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 21557 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 36008 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 35974 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 27168 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.171654 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.950749 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38149 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6961 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5575 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2929 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 646 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 395 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 33907 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2929 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 38897 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 984 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 5237 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2250 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 31157 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents 2290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 23416 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 38564 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 38530 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 12417 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 55 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5160 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2607 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1348 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 14276 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 53 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 6217 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3020 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1445 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2616 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1346 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads 2972 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1380 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25414 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21500 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11650 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6459 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 24653 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.872105 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.460410 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 27184 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 71 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 22298 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 13301 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8222 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 27168 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.820745 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.402255 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15812 64.14% 64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3038 12.32% 76.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2340 9.49% 85.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1493 6.06% 92.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1014 4.11% 96.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 592 2.40% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 274 1.11% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 77 0.31% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17752 65.34% 65.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3320 12.22% 77.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2545 9.37% 86.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1596 5.87% 92.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1085 3.99% 96.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 559 2.06% 98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 231 0.85% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 61 0.22% 99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 19 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 24653 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 27168 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 26 13.83% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available
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-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 101 53.72% 67.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 61 32.45% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 13 6.70% 6.70% # attempts to use FU when none available
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+system.cpu.iq.fu_full::MemRead 118 60.82% 67.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7329 68.16% 68.18% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2278 21.19% 89.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1140 10.60% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7510 66.63% 66.65% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2596 23.03% 89.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1160 10.29% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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-system.cpu.iq.FU_type_0::total 10752 # Type of FU issued
+system.cpu.iq.FU_type_0::total 11271 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7287 67.80% 67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.83% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2302 21.42% 89.26% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1154 10.74% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7311 66.30% 66.32% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.33% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.33% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.35% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2558 23.20% 89.54% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1153 10.46% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10748 # Type of FU issued
+system.cpu.iq.FU_type_1::total 11027 # Type of FU issued
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 14616 67.98% 68.00% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 68.01% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 68.01% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.03% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 4580 21.30% 89.33% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2294 10.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu 14821 66.47% 66.49% # Type of FU issued
+system.cpu.iq.FU_type::IntMult 2 0.01% 66.49% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv 0 0.00% 66.49% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
+system.cpu.iq.FU_type::MemRead 5154 23.11% 89.63% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite 2313 10.37% 100.00% # Type of FU issued
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 21500 # Type of FU issued
-system.cpu.iq.rate 0.648430 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 92 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 96 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 188 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.004279 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.004465 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.008744 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 67911 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 37122 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19235 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type::total 22298 # Type of FU issued
+system.cpu.iq.rate 0.548280 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 100 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 94 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.004485 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004216 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.008700 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 72061 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 40564 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19339 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21662 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 22466 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1424 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1837 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 483 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 580 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 295 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 77 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1433 # Number of loads squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1789 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 481 # Number of stores squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 515 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2403 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2077 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25609 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 858 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5223 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2694 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1462 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20081 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2080 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2108 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4188 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1419 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2929 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 685 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 27441 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 749 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5992 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2825 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 71 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 275 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1233 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1508 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20701 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2373 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2359 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4732 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1597 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 75 # number of nop insts executed
-system.cpu.iew.exec_nop::1 69 # number of nop insts executed
-system.cpu.iew.exec_nop::total 144 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3173 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3212 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6385 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1610 # Number of branches executed
-system.cpu.iew.exec_branches::1 1659 # Number of branches executed
-system.cpu.iew.exec_branches::total 3269 # Number of branches executed
-system.cpu.iew.exec_stores::0 1093 # Number of stores executed
-system.cpu.iew.exec_stores::1 1104 # Number of stores executed
-system.cpu.iew.exec_stores::total 2197 # Number of stores executed
-system.cpu.iew.exec_rate 0.605634 # Inst execution rate
-system.cpu.iew.wb_sent::0 9747 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9790 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19537 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9617 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9638 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19255 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5071 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5050 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10121 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6666 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6567 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13233 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 114 # number of nop insts executed
+system.cpu.iew.exec_nop::1 72 # number of nop insts executed
+system.cpu.iew.exec_nop::total 186 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3487 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3445 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6932 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1642 # Number of branches executed
+system.cpu.iew.exec_branches::1 1642 # Number of branches executed
+system.cpu.iew.exec_branches::total 3284 # Number of branches executed
+system.cpu.iew.exec_stores::0 1114 # Number of stores executed
+system.cpu.iew.exec_stores::1 1086 # Number of stores executed
+system.cpu.iew.exec_stores::total 2200 # Number of stores executed
+system.cpu.iew.exec_rate 0.509012 # Inst execution rate
+system.cpu.iew.wb_sent::0 9936 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9721 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19657 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9778 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19359 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5047 # num instructions producing a value
+system.cpu.iew.wb_producers::1 4925 # num instructions producing a value
+system.cpu.iew.wb_producers::total 9972 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6570 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6411 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 12981 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.290044 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.290678 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.580722 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.760726 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.768996 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.764830 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.240429 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.235585 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.476014 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.768189 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.768211 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.768200 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 12822 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 14694 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1273 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 24601 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.519450 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.331680 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1316 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 27077 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.251708 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19177 77.95% 77.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2699 10.97% 88.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1115 4.53% 93.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 469 1.91% 95.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 340 1.38% 96.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 279 1.13% 97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 190 0.77% 98.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 108 0.44% 99.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 224 0.91% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 21479 79.33% 79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2818 10.41% 89.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1191 4.40% 94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 503 1.86% 95.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 353 1.30% 97.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 251 0.93% 98.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 184 0.68% 98.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 85 0.31% 99.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 213 0.79% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 24601 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 27077 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
@@ -602,27 +601,27 @@ system.cpu.commit.int_insts::total 12614 # Nu
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 224 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 119315 # The number of ROB reads
-system.cpu.rob.rob_writes 53622 # The number of ROB writes
-system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8504 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 129384 # The number of ROB reads
+system.cpu.rob.rob_writes 57896 # The number of ROB writes
+system.cpu.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13501 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
-system.cpu.cpi::0 5.203547 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 5.202730 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.601569 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.192177 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.192207 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.384383 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25429 # number of integer regfile reads
-system.cpu.int_regfile_writes 14534 # number of integer regfile writes
+system.cpu.cpi::0 6.382454 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 6.381453 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.190977 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.156680 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.156704 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.313384 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 26029 # number of integer regfile reads
+system.cpu.int_regfile_writes 14619 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
@@ -630,323 +629,323 @@ system.cpu.misc_regfile_writes 2 # nu
system.cpu.icache.replacements::0 6 # number of replacements
system.cpu.icache.replacements::1 0 # number of replacements
system.cpu.icache.replacements::total 6 # number of replacements
-system.cpu.icache.tagsinuse 313.964791 # Cycle average of tags in use
-system.cpu.icache.total_refs 4270 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6.810207 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 309.378150 # Cycle average of tags in use
+system.cpu.icache.total_refs 4652 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7.443200 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 313.964791 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.153303 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.153303 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 4270 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4270 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 4270 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 4270 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 4270 # number of overall hits
-system.cpu.icache.overall_hits::total 4270 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 864 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 864 # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42891.974400 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64873.264706 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48301.121834 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42192.520548 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42192.520548 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47345.353130 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54931.761905 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49257.893157 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 47134.575342 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 47134.575342 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 9c26db577..165716ee5 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000024 # Number of seconds simulated
-sim_ticks 24110500 # Number of ticks simulated
-final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000023 # Number of seconds simulated
+sim_ticks 22522500 # Number of ticks simulated
+final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94813 # Simulator instruction rate (inst/s)
-host_op_rate 94805 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 150747979 # Simulator tick rate (ticks/s)
-host_mem_usage 222632 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 65265 # Simulator instruction rate (inst/s)
+host_op_rate 65259 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 96930117 # Simulator tick rate (ticks/s)
+host_mem_usage 222888 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 24077000 # Total gap between requests
+system.physmem.totGap 22489000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -164,49 +164,49 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1670434 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests
+system.physmem.totQLat 1783436 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
-system.physmem.totBankLat 7602000 # Total cycles spent in bank access
-system.physmem.avgQLat 3831.27 # Average queueing delay per request
-system.physmem.avgBankLat 17435.78 # Average bank access latency per request
+system.physmem.totBankLat 7252000 # Total cycles spent in bank access
+system.physmem.avgQLat 4090.45 # Average queueing delay per request
+system.physmem.avgBankLat 16633.03 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25267.05 # Average memory access latency
-system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24723.48 # Average memory access latency
+system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 7.23 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.46 # Average read queue length over time
+system.physmem.busUtil 7.74 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.48 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 359 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 55222.48 # Average gap between requests
+system.physmem.avgGap 51580.28 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 48222 # number of cpu cycles simulated
+system.cpu.numCycles 45046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 5021 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups 5017 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 3931 # Number of Address Generations
+system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 3932 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted
@@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 17356 # Number of cycles cpu stages are processed.
-system.cpu.activity 35.991871 # Percentage of cycles cpu is active
+system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 17365 # Number of cycles cpu stages are processed.
+system.cpu.activity 38.549483 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
@@ -233,146 +233,146 @@ system.cpu.committedInsts 15162 # Nu
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
-system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use
-system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use
+system.cpu.icache.total_refs 2584 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits
-system.cpu.icache.overall_hits::total 2586 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
-system.cpu.icache.overall_misses::total 369 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits
+system.cpu.icache.overall_hits::total 2584 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses
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system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@@ -385,36 +385,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3667
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
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@@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
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@@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.005051 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006195 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14500500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 4241500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 14500500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7027500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 21528000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4425000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 14317500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7270500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 21588000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 14317500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7270500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 21588000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
@@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 49109.375000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49900 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49900 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 49263.157895 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 49263.157895 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47884.615385 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 49400.457666 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10728482 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2122568 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12851050 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
@@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index a830552cf..39a395968 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19778500 # Number of ticks simulated
-final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000023 # Number of seconds simulated
+sim_ticks 23428500 # Number of ticks simulated
+final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52882 # Simulator instruction rate (inst/s)
-host_op_rate 52877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72439157 # Simulator tick rate (ticks/s)
-host_mem_usage 223656 # Number of bytes of host memory used
+host_inst_rate 53742 # Simulator instruction rate (inst/s)
+host_op_rate 53738 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87205048 # Simulator tick rate (ticks/s)
+host_mem_usage 223912 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 472432186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1562909220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 483 # Total number of read requests seen
+system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 482 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30912 # Total number of bytes read from memory
+system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30848 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -40,7 +40,7 @@ system.physmem.perBankRdReqs::0 70 # Tr
system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19726000 # Total gap between requests
+system.physmem.totGap 23376000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 483 # Categorize read packet sizes
+system.physmem.readPktSize::6 482 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -164,262 +164,262 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3361480 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests
-system.physmem.totBusLat 1932000 # Total cycles spent in databus access
-system.physmem.totBankLat 7938000 # Total cycles spent in bank access
-system.physmem.avgQLat 6959.59 # Average queueing delay per request
-system.physmem.avgBankLat 16434.78 # Average bank access latency per request
+system.physmem.totQLat 2488982 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests
+system.physmem.totBusLat 1928000 # Total cycles spent in databus access
+system.physmem.totBankLat 7980000 # Total cycles spent in bank access
+system.physmem.avgQLat 5163.86 # Average queueing delay per request
+system.physmem.avgBankLat 16556.02 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27394.37 # Average memory access latency
-system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25719.88 # Average memory access latency
+system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.77 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.67 # Average read queue length over time
+system.physmem.busUtil 8.23 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.53 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 394 # Number of row buffer hits during reads
+system.physmem.readRowHits 393 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 40840.58 # Average gap between requests
+system.physmem.avgGap 48497.93 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 39558 # number of cpu cycles simulated
+system.cpu.numCycles 46858 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6961 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6941 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched
+system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8793 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 8338 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8780 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 8329 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 696 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21740 # Type of FU issued
-system.cpu.iq.rate 0.549573 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 21674 # Type of FU issued
+system.cpu.iq.rate 0.462546 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 174 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1182 # number of nop insts executed
-system.cpu.iew.exec_refs 5396 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4297 # Number of branches executed
-system.cpu.iew.exec_stores 2136 # Number of stores executed
-system.cpu.iew.exec_rate 0.518833 # Inst execution rate
-system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19938 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9248 # num instructions producing a value
-system.cpu.iew.wb_consumers 11357 # num instructions consuming a value
+system.cpu.iew.exec_nop 1177 # number of nop insts executed
+system.cpu.iew.exec_refs 5386 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4289 # Number of branches executed
+system.cpu.iew.exec_stores 2124 # Number of stores executed
+system.cpu.iew.exec_rate 0.437001 # Inst execution rate
+system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19887 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9217 # num instructions producing a value
+system.cpu.iew.wb_consumers 11299 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -430,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 53907 # The number of ROB reads
-system.cpu.rob.rob_writes 51935 # The number of ROB writes
-system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 55155 # The number of ROB reads
+system.cpu.rob.rob_writes 51753 # The number of ROB writes
+system.cpu.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13716 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
-system.cpu.cpi 2.740233 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.740233 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.364933 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.364933 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 32646 # number of integer regfile reads
-system.cpu.int_regfile_writes 18155 # number of integer regfile writes
-system.cpu.misc_regfile_reads 7050 # number of misc regfile reads
+system.cpu.cpi 3.245913 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.245913 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.308080 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.308080 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 32584 # number of integer regfile reads
+system.cpu.int_regfile_writes 18115 # number of integer regfile writes
+system.cpu.misc_regfile_reads 7035 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 200.987114 # Cycle average of tags in use
-system.cpu.icache.total_refs 5096 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 15.032448 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 194.443697 # Cycle average of tags in use
+system.cpu.icache.total_refs 5086 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 15.047337 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 200.987114 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.098138 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.098138 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 5096 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5096 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5096 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5096 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5096 # number of overall hits
-system.cpu.icache.overall_hits::total 5096 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 465 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 465 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 465 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 465 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 465 # number of overall misses
-system.cpu.icache.overall_misses::total 465 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14626000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14626000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14626000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14626000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14626000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14626000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5561 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5561 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5561 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5561 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5561 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5561 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.083618 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.083618 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.083618 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.083618 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.083618 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.083618 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31453.763441 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31453.763441 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 194.443697 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.094943 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.094943 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 5086 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5086 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 5086 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 5086 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses
+system.cpu.icache.overall_misses::total 478 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 21903000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 21903000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 21903000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 21903000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 21903000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 21903000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5564 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5564 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5564 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5564 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5564 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5564 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085909 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.085909 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.085909 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.085909 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.085909 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.085909 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45822.175732 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 45822.175732 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 45822.175732 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 45822.175732 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -500,114 +500,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 126 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 126 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 126 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 126 # number of overall MSHR hits
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 46904.761905 # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37204.819277 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37204.819277 # average ReadExReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -721,50 +721,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index a86401b30..e69de29bb 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,730 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000088 # Number of seconds simulated
-sim_ticks 87707000 # Number of ticks simulated
-final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1518076 # Simulator instruction rate (inst/s)
-host_op_rate 1518015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 196560583 # Simulator tick rate (ticks/s)
-host_mem_usage 1157868 # Number of bytes of host memory used
-host_seconds 0.45 # Real time elapsed on the host
-sim_insts 677327 # Number of instructions simulated
-sim_ops 677327 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
-system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 175415 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 175326 # Number of instructions committed
-system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 120376 # number of integer instructions
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-system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
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-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 82397 # number of memory refs
-system.cpu0.num_load_insts 54591 # Number of load instructions
-system.cpu0.num_store_insts 27806 # Number of store instructions
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-system.cpu0.num_busy_cycles 175415 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.icache.replacements 215 # number of replacements
-system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use
-system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
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-system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
-system.cpu0.icache.overall_hits::total 174921 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
-system.cpu0.icache.overall_misses::total 467 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
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-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 2 # number of replacements
-system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
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-system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
-system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
-system.cpu0.dcache.overall_misses::total 328 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
-system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 173295 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 167398 # Number of instructions committed
-system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 633 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 109926 # number of integer instructions
-system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 53394 # number of memory refs
-system.cpu1.num_load_insts 40652 # Number of load instructions
-system.cpu1.num_store_insts 12742 # Number of store instructions
-system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
-system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
-system.cpu1.icache.replacements 278 # number of replacements
-system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use
-system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
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-system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
-system.cpu1.icache.overall_hits::total 167072 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
-system.cpu1.icache.overall_misses::total 358 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 0 # number of replacements
-system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
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-system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
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-system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
-system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
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-system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
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-system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
-system.cpu1.dcache.overall_misses::total 280 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
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-system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
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-system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
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-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 167334 # Number of instructions committed
-system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu2.num_func_calls 633 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 113333 # number of integer instructions
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-system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu2.num_mem_refs 58537 # number of memory refs
-system.cpu2.num_load_insts 42362 # Number of load instructions
-system.cpu2.num_store_insts 16175 # Number of store instructions
-system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
-system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
-system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
-system.cpu2.icache.replacements 278 # number of replacements
-system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use
-system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
-system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
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-system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
-system.cpu2.icache.overall_hits::total 167008 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
-system.cpu2.icache.overall_misses::total 358 # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
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-system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
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-system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
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-system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
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-system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks.
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-system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
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-system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
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-system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
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-system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
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-system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
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-system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
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-system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
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-system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
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-system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
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-system.cpu2.dcache.overall_misses::total 269 # number of overall misses
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-system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
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-system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
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-system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
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-system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
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-system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
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-system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
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-system.cpu3.icache.overall_hits::total 166942 # number of overall hits
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-system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
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-system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
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-system.cpu3.icache.overall_misses::total 359 # number of overall misses
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-system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
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-system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
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-system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
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-system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
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-system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
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-system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
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-system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
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-system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
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-system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
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-system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
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-system.cpu3.dcache.overall_misses::total 259 # number of overall misses
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-system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
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-system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
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-system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
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-system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
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-system.l2c.overall_misses::cpu1.data 20 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
-system.l2c.overall_misses::cpu2.data 13 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
-system.l2c.overall_misses::cpu3.data 13 # number of overall misses
-system.l2c.overall_misses::total 559 # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 9268efa23..cd5a28936 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,634 +1,634 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000753 # Number of seconds simulated
-sim_ticks 753126500 # Number of ticks simulated
-final_tick 753126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000759 # Number of seconds simulated
+sim_ticks 758619000 # Number of ticks simulated
+final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 111238456 # Simulator tick rate (ticks/s)
-host_mem_usage 391924 # Number of bytes of host memory used
-host_seconds 6.77 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 90167 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 90714 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 93247 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 94741 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 86405 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 91776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 89783 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 85071 # Number of bytes read from this memory
-system.physmem.bytes_read::total 721904 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 471360 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5341 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5232 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5319 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5446 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5378 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5389 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5299 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5260 # Number of bytes written to this memory
-system.physmem.bytes_written::total 514024 # Number of bytes written to this memory
+host_tick_rate 151805189 # Simulator tick rate (ticks/s)
+host_mem_usage 345224 # Number of bytes of host memory used
+host_seconds 5.00 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory
+system.physmem.bytes_read::total 738527 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory
+system.physmem.bytes_written::total 528067 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11019 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11284 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11077 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10805 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11199 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10970 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11109 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88502 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 7365 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5341 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5232 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5319 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5446 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5378 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5389 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5299 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5260 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50029 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 119723579 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 120449885 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 123813197 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 125796928 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 114728402 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 121860006 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 119213704 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 112957119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 958542821 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 625870953 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7091770 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6947040 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7062559 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 7231189 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7140899 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 7155504 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7036003 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 6984218 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 682520134 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 625870953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 126815349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 127396925 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 130875756 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 133028117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 121869301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 129015511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 126249707 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 119941338 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1641062956 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 15498 # number of replacements
-system.l2c.tagsinuse 803.451409 # Cycle average of tags in use
-system.l2c.total_refs 150823 # Total number of references to valid blocks.
-system.l2c.sampled_refs 16301 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.252377 # Average number of references to valid blocks.
+system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 15559 # number of replacements
+system.l2c.tagsinuse 800.707629 # Cycle average of tags in use
+system.l2c.total_refs 151038 # Total number of references to valid blocks.
+system.l2c.sampled_refs 16357 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.233845 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 740.977974 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0 7.980396 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1 7.585151 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2 8.326366 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3 7.791550 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu4 7.277354 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu5 7.805973 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6 7.956689 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu7 7.749957 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.723611 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0 0.007793 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1 0.007407 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2 0.008131 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3 0.007609 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu4 0.007107 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu5 0.007623 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu6 0.007770 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu7 0.007568 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.784621 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0 10718 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1 10624 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2 10900 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10791 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10648 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10876 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 10598 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10892 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 86047 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 76684 # number of Writeback hits
-system.l2c.Writeback_hits::total 76684 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 327 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 379 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 347 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 352 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 359 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 389 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 362 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2869 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 2022 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1993 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 2049 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 2057 # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::cpu7 2058 # number of ReadExReq hits
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-system.l2c.Writeback_accesses::total 76684 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.830501 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu3 0.843556 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu5 0.828180 # miss rate for UpgradeReq accesses
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-system.l2c.blocked_cycles::no_mshrs 205 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
@@ -657,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
@@ -772,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.num_copies 0 # number of copy accesses completed
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system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu1.l1c.overall_mshr_miss_rate::total 0.856792 # mshr miss rate for overall accesses
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-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency
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+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency
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+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
@@ -887,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu2.num_copies 0 # number of copy accesses completed
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-system.cpu2.l1c.tagsinuse 393.105668 # Cycle average of tags in use
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-system.cpu2.l1c.sampled_refs 23291 # Sample count of references to valid blocks.
-system.cpu2.l1c.avg_refs 0.575587 # Average number of references to valid blocks.
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
@@ -1002,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu3.num_copies 0 # number of copy accesses completed
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system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2297665794 # number of overall MSHR uncacheable cycles
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
@@ -1117,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu4.num_reads 100000 # number of read accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
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-system.cpu4.l1c.avg_refs 0.574888 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22068 # number of replacements
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+system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
@@ -1232,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu5.num_copies 0 # number of copy accesses completed
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system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses
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+system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 63640 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9848 # number of writebacks
-system.cpu5.l1c.writebacks::total 9848 # number of writebacks
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-system.cpu5.l1c.overall_mshr_misses::total 58736 # number of overall MSHR misses
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-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4481994386 # number of ReadReq MSHR miss cycles
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-system.cpu5.l1c.demand_mshr_miss_latency::total 7555865539 # number of demand (read+write) MSHR miss cycles
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-system.cpu5.l1c.overall_mshr_miss_latency::total 7555865539 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1395127827 # number of ReadReq MSHR uncacheable cycles
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-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2335466746 # number of overall MSHR uncacheable cycles
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-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802750 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952480 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952480 # mshr miss rate for WriteReq accesses
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-system.cpu5.l1c.demand_mshr_miss_rate::total 0.855138 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.855138 # mshr miss rate for overall accesses
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+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
@@ -1347,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 52397 # number of write accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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-system.cpu6.l1c.tagsinuse 389.740766 # Cycle average of tags in use
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-system.cpu6.l1c.sampled_refs 22153 # Sample count of references to valid blocks.
-system.cpu6.l1c.avg_refs 0.586873 # Average number of references to valid blocks.
+system.cpu6.l1c.replacements 21915 # number of replacements
+system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use
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+system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.ReadReq_avg_miss_latency::total 129554.212565 # average ReadReq miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
@@ -1462,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu7.num_copies 0 # number of copy accesses completed
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system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805608 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953964 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953964 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.857266 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.857266 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 124664.959714 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 124664.959714 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134429.897112 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134429.897112 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks
+system.cpu7.l1c.writebacks::total 9733 # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency