diff options
Diffstat (limited to 'tests/quick')
81 files changed, 19158 insertions, 23034 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index f712efbf6..588a2547e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,114 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +181,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +191,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +209,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,138 +222,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 0defa99bd..347214713 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 13:57:44 +Real time: Aug/05/2010 10:23:43 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.95 -Virtual_time_in_minutes: 0.0158333 -Virtual_time_in_hours: 0.000263889 -Virtual_time_in_days: 1.09954e-05 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 275313 Ruby_start_time: 0 Ruby_cycles: 275313 -mbytes_resident: 34.4609 -mbytes_total: 34.4688 +mbytes_resident: 34.8867 +mbytes_total: 34.8945 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 275314 [ 275314 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 275314 ] Busy Controller Counts: L1Cache-0:0 @@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7392 -page_faults: 2212 +page_reclaims: 7576 +page_faults: 2166 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 8850 70800 +total_msg_count_Request_Control: 3123 24984 +total_msg_count_Response_Data: 9681 697032 +total_msg_count_Response_Control: 14286 114288 +total_msg_count_Writeback_Data: 864 62208 +total_msg_count_Writeback_Control: 867 6936 +total_msgs: 37671 total_bytes: 976248 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.0889147 @@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246247 outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -Inv 1041 -L1_Replacement 1354 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 583 -DataS_fromL1 0 -Data_all_Acks 907 -Ack 0 -Ack_all 0 -WB_Ack 436 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Inv [1041 ] 1041 +L1_Replacement [1354 ] 1354 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [583 ] 583 +DataS_fromL1 [0 ] 0 +Data_all_Acks [907 ] 907 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [436 ] 436 - Transitions - -NP Load 525 -NP Ifetch 646 -NP Store 191 -NP Inv 356 -NP L1_Replacement 0 <-- - -I Load 58 -I Ifetch 45 -I Store 25 -I Inv 0 <-- -I L1_Replacement 556 - -S Load 0 <-- -S Ifetch 5723 -S Store 0 <-- -S Inv 325 -S L1_Replacement 362 - -E Load 454 -E Ifetch 0 <-- -E Store 71 -E Inv 219 -E L1_Replacement 291 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 148 -M Ifetch 0 <-- -M Store 578 -M Inv 141 -M L1_Replacement 145 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 0 <-- -IS Data_Exclusive 583 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 691 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 0 <-- -IM Data_all_Acks 216 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 436 - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Inv [356 ] 356 +NP L1_Replacement [0 ] 0 + +I Load [58 ] 58 +I Ifetch [45 ] 45 +I Store [25 ] 25 +I Inv [0 ] 0 +I L1_Replacement [556 ] 556 + +S Load [0 ] 0 +S Ifetch [5723 ] 5723 +S Store [0 ] 0 +S Inv [325 ] 325 +S L1_Replacement [362 ] 362 + +E Load [454 ] 454 +E Ifetch [0 ] 0 +E Store [71 ] 71 +E Inv [219 ] 219 +E L1_Replacement [291 ] 291 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [148 ] 148 +M Ifetch [0 ] 0 +M Store [578 ] 578 +M Inv [141 ] 141 +M L1_Replacement [145 ] 145 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [583 ] 583 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [691 ] 691 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [216 ] 216 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 + +M_I Load [0 ] 0 +M_I Ifetch [0 ] 0 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [436 ] 436 + +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GET_INSTR 691 -L1_GETS 592 -L1_GETX 220 -L1_UPGRADE 0 -L1_PUTX 436 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 142 -L2_Replacement_clean 1310 -Mem_Data 1460 -Mem_Ack 1452 -WB_Data 141 -WB_Data_clean 0 -Ack 0 -Ack_all 900 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 799 -MEM_Inv 0 +L1_GET_INSTR [691 ] 691 +L1_GETS [592 ] 592 +L1_GETX [220 ] 220 +L1_UPGRADE [0 ] 0 +L1_PUTX [436 ] 436 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [142 ] 142 +L2_Replacement_clean [1310 ] 1310 +Mem_Data [1460 ] 1460 +Mem_Ack [1452 ] 1452 +WB_Data [141 ] 141 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [900 ] 900 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [799 ] 799 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 686 -NP L1_GETS 570 -NP L1_GETX 204 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- - -SS L1_GET_INSTR 5 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 681 -SS MEM_Inv 0 <-- - -M L1_GET_INSTR 0 <-- -M L1_GETS 13 -M L1_GETX 12 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 134 -M L2_Replacement_clean 277 -M MEM_Inv 0 <-- - -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 436 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 8 -MT L2_Replacement_clean 352 -MT MEM_Inv 0 <-- - -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 9 -M_I L1_GETX 4 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 1452 -M_I MEM_Inv 0 <-- - -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 6 -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 2 -MT_I MEM_Inv 0 <-- - -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 135 -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 217 - -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 681 - -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- - -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 570 -ISS MEM_Inv 0 <-- - -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 686 -IS MEM_Inv 0 <-- - -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 204 -IM MEM_Inv 0 <-- - -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- - -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 799 -MT_MB MEM_Inv 0 <-- - -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- - -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- - -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- - -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +NP L1_GET_INSTR [686 ] 686 +NP L1_GETS [570 ] 570 +NP L1_GETX [204 ] 204 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 + +SS L1_GET_INSTR [5 ] 5 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [681 ] 681 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [0 ] 0 +M L1_GETS [13 ] 13 +M L1_GETX [12 ] 12 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [134 ] 134 +M L2_Replacement_clean [277 ] 277 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [436 ] 436 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [8 ] 8 +MT L2_Replacement_clean [352 ] 352 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [9 ] 9 +M_I L1_GETX [4 ] 4 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [1452 ] 1452 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [6 ] 6 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [2 ] 2 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [135 ] 135 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [217 ] 217 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [681 ] 681 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [570 ] 570 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [686 ] 686 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [204 ] 204 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [0 ] 0 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [799 ] 799 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1737 memory_reads: 1460 memory_writes: 277 @@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 1460 -Data 277 -Memory_Data 1460 -Memory_Ack 277 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 1175 +Fetch [1460 ] 1460 +Data [277 ] 277 +Memory_Data [1460 ] 1460 +Memory_Ack [277 ] 277 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [1175 ] 1175 - Transitions - -I Fetch 1460 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- - -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- - -M Data 277 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 1175 - -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 1460 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- - -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 277 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- - -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- - -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- - -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +I Fetch [1460 ] 1460 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [277 ] 277 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [1175 ] 1175 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [1460 ] 1460 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [277 ] 277 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 37377ab3d..513747fae 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 13:54:58 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 13:57:42 -M5 executing on svvint03 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:23:42 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index edabafa0b..d792ca5ac 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8106 # Simulator instruction rate (inst/s) -host_mem_usage 215916 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 348501 # Simulator tick rate (ticks/s) +host_inst_rate 24630 # Simulator instruction rate (inst/s) +host_mem_usage 212388 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +host_tick_rate 1058851 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000275 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index aceab6a24..756bebd28 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,110 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +177,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +187,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +205,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,134 +218,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 89d0c3194..c3c1c36bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,40 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:08:14 +Real time: Aug/05/2010 10:35:39 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.8 -Virtual_time_in_minutes: 0.0133333 -Virtual_time_in_hours: 0.000222222 -Virtual_time_in_days: 9.25926e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 223854 Ruby_start_time: 0 Ruby_cycles: 223854 -mbytes_resident: 34.6055 -mbytes_total: 34.6133 +mbytes_resident: 34.9609 +mbytes_total: 34.9688 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 223855 [ 223855 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 223855 ] Busy Controller Counts: L2Cache-0:0 @@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7397 -page_faults: 2249 +page_reclaims: 7630 +page_faults: 2184 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 7428 59424 +total_msg_count_Response_Data: 6684 481248 +total_msg_count_ResponseL2hit_Data: 744 53568 +total_msg_count_Writeback_Data: 4644 334368 +total_msg_count_Writeback_Control: 17424 139392 +total_msg_count_Unblock_Control: 7428 59424 +total_msgs: 44352 total_bytes: 1127424 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.219641 @@ -190,972 +201,966 @@ links_utilized_percent_switch_3: 0.349752 outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -L1_Replacement 1379 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 1362 -Writeback_Ack 0 -Writeback_Ack_Data 1354 -Writeback_Nack 0 -All_acks 191 -Use_Timeout 1361 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +L1_Replacement [1379 ] 1379 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [1362 ] 1362 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [1354 ] 1354 +Writeback_Nack [0 ] 0 +All_acks [191 ] 191 +Use_Timeout [1361 ] 1361 - Transitions - -I Load 525 -I Ifetch 646 -I Store 191 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- - -M Load 308 -M Ifetch 3484 -M Store 51 -M L1_Replacement 1086 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- - -M_W Load 111 -M_W Ifetch 2284 -M_W Store 27 -M_W L1_Replacement 17 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 1143 - -MM Load 234 -MM Ifetch 0 <-- -MM Store 339 -MM L1_Replacement 268 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- - -MM_W Load 7 -MM_W Ifetch 0 <-- -MM_W Store 257 -MM_W L1_Replacement 8 -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 218 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 191 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 191 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 1171 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 1354 -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +I Load [525 ] 525 +I Ifetch [646 ] 646 +I Store [191 ] 191 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [308 ] 308 +M Ifetch [3484 ] 3484 +M Store [51 ] 51 +M L1_Replacement [1086 ] 1086 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [111 ] 111 +M_W Ifetch [2284 ] 2284 +M_W Store [27 ] 27 +M_W L1_Replacement [17 ] 17 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [1143 ] 1143 + +MM Load [234 ] 234 +MM Ifetch [0 ] 0 +MM Store [339 ] 339 +MM L1_Replacement [268 ] 268 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [7 ] 7 +MM_W Ifetch [0 ] 0 +MM_W Store [257 ] 257 +MM_W L1_Replacement [8 ] 8 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [218 ] 218 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [191 ] 191 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [191 ] 191 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [1171 ] 1171 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [1354 ] 1354 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GETS 1171 -L1_GETX 191 -L1_PUTO 0 -L1_PUTX 1354 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 131 -Data 131 -Data_Exclusive 983 -L1_WBCLEANDATA 1059 -L1_WBDIRTYDATA 295 -Writeback_Ack 1098 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 1362 -L2_Replacement 1098 +L1_GETS [1171 ] 1171 +L1_GETX [191 ] 191 +L1_PUTO [0 ] 0 +L1_PUTX [1354 ] 1354 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [131 ] 131 +Data [131 ] 131 +Data_Exclusive [983 ] 983 +L1_WBCLEANDATA [1059 ] 1059 +L1_WBDIRTYDATA [295 ] 295 +Writeback_Ack [1098 ] 1098 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [1362 ] 1362 +L2_Replacement [1098 ] 1098 - Transitions - -NP L1_GETS 983 -NP L1_GETX 131 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 1354 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 188 -M L1_GETX 60 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 1098 - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 1059 -ILXW L1_WBDIRTYDATA 295 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 983 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 983 -IGS L2_Replacement 0 <-- - -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 131 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 131 -IGMO Exclusive_Unblock 131 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 60 -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 188 -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 0 <-- -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 1098 -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +NP L1_GETS [983 ] 983 +NP L1_GETX [131 ] 131 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [1354 ] 1354 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [188 ] 188 +M L1_GETX [60 ] 60 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [1098 ] 1098 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [1059 ] 1059 +ILXW L1_WBDIRTYDATA [295 ] 295 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [983 ] 983 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [983 ] 983 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [131 ] 131 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [131 ] 131 +IGMO Exclusive_Unblock [131 ] 131 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [60 ] 60 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [188 ] 188 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [1098 ] 1098 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1308 memory_reads: 1114 memory_writes: 194 @@ -1175,201 +1180,200 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 131 -GETS 983 -PUTX 1098 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 1114 -Clean_Writeback 904 -Dirty_Writeback 194 -Memory_Data 1114 -Memory_Ack 194 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [131 ] 131 +GETS [983 ] 983 +PUTX [1098 ] 1098 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [1114 ] 1114 +Clean_Writeback [904 ] 904 +Dirty_Writeback [194 ] 194 +Memory_Data [1114 ] 1114 +Memory_Ack [194 ] 194 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 131 -I GETS 983 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 191 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -M GETX 0 <-- -M GETS 0 <-- -M PUTX 1098 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 983 -IS Memory_Data 983 -IS Memory_Ack 2 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- - -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- - -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- - -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- - -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 131 -MM Memory_Data 131 -MM Memory_Ack 1 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- - - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 904 -MI Dirty_Writeback 194 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- - -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- - -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- - -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- - -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- - -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +I GETX [131 ] 131 +I GETS [983 ] 983 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [191 ] 191 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [1098 ] 1098 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [983 ] 983 +IS Memory_Data [983 ] 983 +IS Memory_Ack [2 ] 2 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [131 ] 131 +MM Memory_Data [131 ] 131 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [904 ] 904 +MI Dirty_Writeback [194 ] 194 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index a5c547a14..7e21d792f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 14:49:51 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:08:13 -M5 executing on svvint05 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:35:39 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f1675ef82..add084384 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11859 # Simulator instruction rate (inst/s) -host_mem_usage 216064 # Number of bytes of host memory used -host_seconds 0.55 # Real time elapsed on the host -host_tick_rate 407003 # Simulator tick rate (ticks/s) +host_inst_rate 23717 # Simulator instruction rate (inst/s) +host_mem_usage 212528 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 829037 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000224 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 1658b1622..d5555ef31 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,121 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +188,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +198,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +216,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,144 +229,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index ae58be613..39236835d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -13,12 +13,12 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered -virtual_net_2: active, ordered -virtual_net_3: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered virtual_net_4: active, unordered virtual_net_5: active, ordered virtual_net_6: inactive @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:55:45 +Real time: Aug/05/2010 10:42:35 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.43 -Virtual_time_in_minutes: 0.00716667 -Virtual_time_in_hours: 0.000119444 -Virtual_time_in_days: 4.97685e-06 +Virtual_time_in_seconds: 0.27 +Virtual_time_in_minutes: 0.0045 +Virtual_time_in_hours: 7.5e-05 +Virtual_time_in_days: 3.125e-06 -Ruby_current_time: 236654 +Ruby_current_time: 243131 Ruby_start_time: 0 -Ruby_cycles: 236654 +Ruby_cycles: 243131 -mbytes_resident: 34.4141 -mbytes_total: 34.4219 +mbytes_resident: 34.8711 +mbytes_total: 34.8789 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 236655 [ 236655 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 243132 ] Busy Controller Counts: L1Cache-0:0 @@ -81,10 +70,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ] +miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ] +miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1300 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ] +miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ] +miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +127,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7348 -page_faults: 2239 +page_reclaims: 7568 +page_faults: 2181 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,788 +136,900 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 8046 64368 +total_msg_count_Response_Data: 3903 281016 +total_msg_count_ResponseL2hit_Data: 237 17064 +total_msg_count_Response_Control: 3 24 +total_msg_count_Writeback_Data: 4785 344520 +total_msg_count_Writeback_Control: 3222 25776 +total_msgs: 20196 total_bytes: 732768 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.164956 - links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.171423 + links_utilized_percent_switch_0_link_0: 0.0638596 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.278985 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0968503 - links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0889284 + links_utilized_percent_switch_1_link_0: 0.0697464 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.10811 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.12111 - links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.132082 + links_utilized_percent_switch_2_link_0: 0.023367 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.240796 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.204222 - links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_3: 0.209297 + links_utilized_percent_switch_3_link_0: 0.255438 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.278985 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0934681 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 646 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 734 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100% + + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -L1_Replacement 1375 -Data_Shared 154 -Data_Owner 0 -Data_All_Tokens 1228 -Ack 38 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 -Request_Timeout 0 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 1227 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Atomic [0 ] 0 +L1_Replacement [1384 ] 1384 +Data_Shared [48 ] 48 +Data_Owner [0 ] 0 +Data_All_Tokens [1332 ] 1332 +Ack [1 ] 1 +Ack_All_Tokens [0 ] 0 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Request_Timeout [0 ] 0 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [1331 ] 1331 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 525 -NP Ifetch 646 -NP Store 191 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S Load 166 -S Ifetch 314 -S Store 20 -S L1_Replacement 134 -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M Load 184 -M Ifetch 3447 -M Store 33 -M L1_Replacement 952 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -MM Load 221 -MM Ifetch 0 <-- -MM Store 333 -MM L1_Replacement 268 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 0 <-- - -M_W Load 69 -M_W Ifetch 2007 -M_W Store 25 -M_W L1_Replacement 14 -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 991 - -MM_W Load 20 -MM_W Ifetch 0 <-- -MM_W Store 263 -MM_W L1_Replacement 7 -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 236 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 191 -IM Ack 7 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 0 <-- -IM Request_Timeout 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 20 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 154 -IS Data_Owner 0 <-- -IS Data_All_Tokens 1017 -IS Ack 31 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 0 <-- -IS Request_Timeout 0 <-- - -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S Load [95 ] 95 +S Ifetch [64 ] 64 +S Store [18 ] 18 +S Atomic [0 ] 0 +S L1_Replacement [30 ] 30 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M Load [222 ] 222 +M Ifetch [3433 ] 3433 +M Store [35 ] 35 +M Atomic [0 ] 0 +M L1_Replacement [1056 ] 1056 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +MM Load [220 ] 220 +MM Ifetch [0 ] 0 +MM Store [331 ] 331 +MM Atomic [0 ] 0 +MM L1_Replacement [268 ] 268 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [0 ] 0 + +M_W Load [102 ] 102 +M_W Ifetch [2271 ] 2271 +M_W Store [25 ] 25 +M_W Atomic [0 ] 0 +M_W L1_Replacement [21 ] 21 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [0 ] 0 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [1097 ] 1097 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +MM_W Load [21 ] 21 +MM_W Ifetch [0 ] 0 +MM_W Store [265 ] 265 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [9 ] 9 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [0 ] 0 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [234 ] 234 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data_Shared [0 ] 0 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [191 ] 191 +IM Ack [1 ] 1 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [0 ] 0 +IM Request_Timeout [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [18 ] 18 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [0 ] 0 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Shared [48 ] 48 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [1123 ] 1123 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [0 ] 0 +IS Request_Timeout [0 ] 0 + +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 + +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 + +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 1302 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1302 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 86.2519% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.7481% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1302 100% + + --- L2Cache --- - Event Counts - -L1_GETS 1140 -L1_GETS_Last_Token 31 -L1_GETX 211 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 1276 -Writeback_Tokens 82 -Writeback_Shared_Data 0 -Writeback_All_Tokens 1272 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 +L1_GETS [1168 ] 1168 +L1_GETS_Last_Token [3 ] 3 +L1_GETX [209 ] 209 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [1349 ] 1349 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [28 ] 28 +Writeback_All_Tokens [1326 ] 1326 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 - Transitions - -NP L1_GETS 986 -NP L1_GETX 138 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 82 -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 1202 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I L1_GETS 0 <-- -I L1_GETS_Last_Token 31 -I L1_GETX 7 -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 130 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 18 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 18 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 84 -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 52 -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M L1_GETS 154 -M L1_GETX 48 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 1062 -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1369 - memory_reads: 1162 - memory_writes: 207 - memory_refreshes: 493 - memory_total_request_delays: 529 - memory_delays_per_request: 0.386413 - memory_delays_in_input_queue: 185 +NP L1_GETS [1123 ] 1123 +NP L1_GETX [177 ] 177 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [28 ] 28 +NP Writeback_All_Tokens [1323 ] 1323 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [34 ] 34 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [1 ] 1 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [3 ] 3 +S L1_GETX [1 ] 1 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [24 ] 24 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [42 ] 42 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [2 ] 2 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [45 ] 45 +M L1_GETX [30 ] 30 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [1249 ] 1249 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1542 + memory_reads: 1301 + memory_writes: 241 + memory_refreshes: 507 + memory_total_request_delays: 714 + memory_delays_per_request: 0.463035 + memory_delays_in_input_queue: 240 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 344 - memory_stalls_for_bank_busy: 101 + memory_delays_stalled_at_head_of_bank_queue: 474 + memory_stalls_for_bank_busy: 148 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 19 - memory_stalls_for_bus: 222 + memory_stalls_for_arbitration: 30 + memory_stalls_for_bus: 278 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2 + memory_stalls_for_read_write_turnaround: 18 memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53 + accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 163 -GETS 1017 -Lockdown 0 -Unlockdown 0 -Own_Lock_or_Unlock 0 -Data_Owner 19 -Data_All_Tokens 188 -Ack_Owner 65 -Ack_Owner_All_Tokens 874 -Tokens 0 -Ack_All_Tokens 44 -Request_Timeout 0 -Memory_Data 1162 -Memory_Ack 207 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [179 ] 179 +GETS [1123 ] 1123 +Lockdown [0 ] 0 +Unlockdown [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [21 ] 21 +Data_All_Tokens [220 ] 220 +Ack_Owner [21 ] 21 +Ack_Owner_All_Tokens [1029 ] 1029 +Tokens [0 ] 0 +Ack_All_Tokens [24 ] 24 +Request_Timeout [0 ] 0 +Memory_Data [1301 ] 1301 +Memory_Ack [241 ] 241 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 145 -O GETS 1017 -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 44 -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- - -NO GETX 18 -NO GETS 0 <-- -NO Lockdown 0 <-- -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 19 -NO Data_All_Tokens 188 -NO Ack_Owner 65 -NO Ack_Owner_All_Tokens 874 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -L GETX 0 <-- -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 0 <-- -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 207 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- - -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- - -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- - -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 1162 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- - -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- - -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- - -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- - -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- - -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- - -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- - -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- - +O GETX [178 ] 178 +O GETS [1123 ] 1123 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [24 ] 24 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [1 ] 1 +NO GETS [0 ] 0 +NO Lockdown [0 ] 0 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [21 ] 21 +NO Data_All_Tokens [220 ] 220 +NO Ack_Owner [21 ] 21 +NO Ack_Owner_All_Tokens [1029 ] 1029 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [0 ] 0 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [241 ] 241 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [1301 ] 1301 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 9f63d9c39..bfe534678 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 15:54:34 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:55:45 -M5 executing on svvint04 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:42:35 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 236654 because target called exit() +Exiting @ tick 243131 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 717c91c49..4330907be 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 35577 # Simulator instruction rate (inst/s) -host_mem_usage 215884 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 1314701 # Simulator tick rate (ticks/s) +host_inst_rate 45740 # Simulator instruction rate (inst/s) +host_mem_usage 212336 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 1736538 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000237 # Number of seconds simulated -sim_ticks 236654 # Number of ticks simulated +sim_seconds 0.000243 # Number of seconds simulated +sim_ticks 243131 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 236654 # number of cpu cycles simulated +system.cpu.numCycles 243131 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 2f4078396..a5602ce6c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -65,6 +65,110 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +177,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +187,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +205,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,114 +218,26 @@ type=Topology children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index b64bafefe..422144bd2 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -13,14 +13,14 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar -virtual_net_0: active, unordered -virtual_net_1: active, unordered +virtual_net_0: active, ordered +virtual_net_1: active, ordered virtual_net_2: active, unordered virtual_net_3: active, unordered -virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 11:55:11 +Real time: Aug/05/2010 11:09:30 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.39 -Virtual_time_in_minutes: 0.0065 -Virtual_time_in_hours: 0.000108333 -Virtual_time_in_days: 4.51389e-06 +Virtual_time_in_seconds: 0.61 +Virtual_time_in_minutes: 0.0101667 +Virtual_time_in_hours: 0.000169444 +Virtual_time_in_days: 7.06019e-06 -Ruby_current_time: 215528 +Ruby_current_time: 207970 Ruby_start_time: 0 -Ruby_cycles: 215528 +Ruby_cycles: 207970 -mbytes_resident: 33.1406 -mbytes_total: 33.1484 -resident_ratio: 1 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 215529 [ 215529 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 34.3633 +mbytes_total: 206.125 +resident_ratio: 0.166768 +ruby_cycles_executed: [ 207971 ] Busy Controller Counts: L1Cache-0:0 @@ -80,10 +69,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ] +miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ] +miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +imcomplete_dir_Times: 1158 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ] +miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ] +miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7120 -page_faults: 2128 +page_reclaims: 9927 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -124,453 +135,665 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 3477 27816 +total_msg_count_Response_Data: 3477 250344 +total_msg_count_Writeback_Data: 660 47520 +total_msg_count_Writeback_Control: 9627 77016 +total_msg_count_Unblock_Control: 3477 27816 +total_msgs: 20718 total_bytes: 430512 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.107382 - links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.111284 + links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152706 - links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.158256 + links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.20807 - links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_2: 0.215632 + links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 646 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 716 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 1159 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100% + + --- L1Cache --- - Event Counts - -Load 1209 -Ifetch 6447 -Store 946 -L2_Replacement 1143 -L1_to_L2 1354 -L2_to_L1D 138 -L2_to_L1I 65 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 1159 -Writeback_Ack 1143 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 1159 +Load [1201 ] 1201 +Ifetch [6436 ] 6436 +Store [919 ] 919 +L2_Replacement [1143 ] 1143 +L1_to_L2 [1354 ] 1354 +Trigger_L2_to_L1D [138 ] 138 +Trigger_L2_to_L1I [65 ] 65 +Complete_L2_to_L1 [203 ] 203 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [1159 ] 1159 +Writeback_Ack [1143 ] 1143 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [1159 ] 1159 - Transitions - -I Load 420 -I Ifetch 581 -I Store 158 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- - -M Load 368 -M Ifetch 5833 -M Store 66 -M L2_Replacement 923 -M L1_to_L2 1061 -M L2_to_L1D 68 -M L2_to_L1I 65 -M Other_GETX 0 <-- -M Other_GETS 0 <-- - -MM Load 397 -MM Ifetch 0 <-- -MM Store 641 -MM L2_Replacement 220 -MM L1_to_L2 293 -MM L2_to_L1D 70 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 158 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 0 <-- -M_W All_acks_no_sharers 1001 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 158 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 1001 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 24 -MI Ifetch 33 -MI Store 81 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 1143 - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +I Load [420 ] 420 +I Ifetch [581 ] 581 +I Store [158 ] 158 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 + +M Load [368 ] 368 +M Ifetch [5833 ] 5833 +M Store [66 ] 66 +M L2_Replacement [923 ] 923 +M L1_to_L2 [1061 ] 1061 +M Trigger_L2_to_L1D [68 ] 68 +M Trigger_L2_to_L1I [65 ] 65 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 + +MM Load [397 ] 397 +MM Ifetch [0 ] 0 +MM Store [641 ] 641 +MM L2_Replacement [220 ] 220 +MM L1_to_L2 [293 ] 293 +MM Trigger_L2_to_L1D [70 ] 70 +MM Trigger_L2_to_L1I [0 ] 0 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [0 ] 0 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [158 ] 158 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 + +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [0 ] 0 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [1001 ] 1001 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [0 ] 0 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [0 ] 0 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [158 ] 158 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [0 ] 0 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [1001 ] 1001 + +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 + +MI Load [16 ] 16 +MI Ifetch [22 ] 22 +MI Store [54 ] 54 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [1143 ] 1143 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 + +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [0 ] 0 +MT Complete_L2_to_L1 [133 ] 133 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [0 ] 0 +MMT Store [0 ] 0 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [0 ] 0 +MMT Complete_L2_to_L1 [70 ] 70 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1379 memory_reads: 1159 memory_writes: 220 - memory_refreshes: 449 - memory_total_request_delays: 342 - memory_delays_per_request: 0.248006 - memory_delays_in_input_queue: 1 + memory_refreshes: 434 + memory_total_request_delays: 471 + memory_delays_per_request: 0.341552 + memory_delays_in_input_queue: 15 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 341 - memory_stalls_for_bank_busy: 167 + memory_delays_stalled_at_head_of_bank_queue: 456 + memory_stalls_for_bank_busy: 86 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 19 - memory_stalls_for_bus: 57 + memory_stalls_for_arbitration: 30 + memory_stalls_for_bus: 78 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 98 + memory_stalls_for_read_write_turnaround: 262 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 519 -GETS 1114 -PUT 1143 -Unblock 1159 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 923 -Writeback_Exclusive_Dirty 220 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 1159 -Memory_Ack 220 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [189 ] 189 +GETS [1027 ] 1027 +PUT [1143 ] 1143 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [1159 ] 1159 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [923 ] 923 +Writeback_Exclusive_Dirty [220 ] 220 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1159 ] 1159 +Memory_Ack [220 ] 220 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 1143 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -E GETX 158 -E GETS 1001 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- - -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 0 <-- -NO_B Unblock 1159 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- - -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- - -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 1159 - -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- - -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- - -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- - -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- - -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- - -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- - -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- - -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- - -WB GETX 27 -WB GETS 20 -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 923 -WB Writeback_Exclusive_Dirty 220 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- - -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- - -WB_E_W GETX 334 -WB_E_W GETS 93 -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 220 - +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 + +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [1143 ] 1143 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +E GETX [158 ] 158 +E GETS [1001 ] 1001 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 + +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [1159 ] 1159 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 + +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 + +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 + +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 + +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [1159 ] 1159 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [27 ] 27 +WB GETS [19 ] 19 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [923 ] 923 +WB Writeback_Exclusive_Dirty [220 ] 220 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [4 ] 4 +WB_E_W GETS [7 ] 7 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 8dfe8bf7b..01467c4b7 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 11:30:01 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 11:55:11 -M5 executing on svvint06 +M5 compiled Aug 5 2010 11:09:13 +M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates +M5 started Aug 5 2010 11:09:30 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 215528 because target called exit() +Exiting @ tick 207970 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 67cd72f19..8112f9791 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45742 # Simulator instruction rate (inst/s) -host_mem_usage 213100 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 1539442 # Simulator tick rate (ticks/s) +host_inst_rate 31390 # Simulator instruction rate (inst/s) +host_mem_usage 211076 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 1018487 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000216 # Number of seconds simulated -sim_ticks 215528 # Number of ticks simulated +sim_seconds 0.000208 # Number of seconds simulated +sim_ticks 207970 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 215528 # number of cpu cycles simulated +system.cpu.numCycles 207970 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 401021812..1a58721d4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,114 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +181,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +191,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +209,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,138 +222,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index e13eebd85..f8968612d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 13:57:45 +Real time: Aug/05/2010 10:31:34 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.45 -Virtual_time_in_minutes: 0.0075 -Virtual_time_in_hours: 0.000125 -Virtual_time_in_days: 5.20833e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 103637 Ruby_start_time: 0 Ruby_cycles: 103637 -mbytes_resident: 33.0938 -mbytes_total: 33.1016 +mbytes_resident: 33.5703 +mbytes_total: 33.5781 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 103638 [ 103638 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 103638 ] Busy Controller Counts: L1Cache-0:0 @@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] -miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] +miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] +miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7156 -page_faults: 2112 +page_reclaims: 7325 +page_faults: 2071 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 3357 26856 +total_msg_count_Request_Control: 1293 10344 +total_msg_count_Response_Data: 3666 263952 +total_msg_count_Response_Control: 5220 41760 +total_msg_count_Writeback_Data: 327 23544 +total_msg_count_Writeback_Control: 231 1848 +total_msgs: 14094 total_bytes: 368304 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.0891754 @@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246791 outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -Inv 431 -L1_Replacement 502 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 204 -DataS_fromL1 0 -Data_all_Acks 368 -Ack 0 -Ack_all 0 -WB_Ack 124 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Inv [431 ] 431 +L1_Replacement [502 ] 502 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [204 ] 204 +DataS_fromL1 [0 ] 0 +Data_all_Acks [368 ] 368 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [124 ] 124 - Transitions - -NP Load 182 -NP Ifetch 270 -NP Store 58 -NP Inv 162 -NP L1_Replacement 0 <-- - -I Load 22 -I Ifetch 30 -I Store 10 -I Inv 0 <-- -I L1_Replacement 206 - -S Load 0 <-- -S Ifetch 2285 -S Store 0 <-- -S Inv 124 -S L1_Replacement 172 - -E Load 140 -E Ifetch 0 <-- -E Store 41 -E Inv 83 -E L1_Replacement 79 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 71 -M Ifetch 0 <-- -M Store 185 -M Inv 62 -M L1_Replacement 45 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 0 <-- -IS Data_Exclusive 204 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 300 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 0 <-- -IM Data_all_Acks 68 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 124 - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [182 ] 182 +NP Ifetch [270 ] 270 +NP Store [58 ] 58 +NP Inv [162 ] 162 +NP L1_Replacement [0 ] 0 + +I Load [22 ] 22 +I Ifetch [30 ] 30 +I Store [10 ] 10 +I Inv [0 ] 0 +I L1_Replacement [206 ] 206 + +S Load [0 ] 0 +S Ifetch [2285 ] 2285 +S Store [0 ] 0 +S Inv [124 ] 124 +S L1_Replacement [172 ] 172 + +E Load [140 ] 140 +E Ifetch [0 ] 0 +E Store [41 ] 41 +E Inv [83 ] 83 +E L1_Replacement [79 ] 79 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [71 ] 71 +M Ifetch [0 ] 0 +M Store [185 ] 185 +M Inv [62 ] 62 +M L1_Replacement [45 ] 45 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [204 ] 204 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [300 ] 300 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [68 ] 68 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 + +M_I Load [0 ] 0 +M_I Ifetch [0 ] 0 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [124 ] 124 + +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GET_INSTR 300 -L1_GETS 209 -L1_GETX 71 -L1_UPGRADE 0 -L1_PUTX 124 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 43 -L2_Replacement_clean 496 -Mem_Data 547 -Mem_Ack 539 -WB_Data 62 -WB_Data_clean 0 -Ack 0 -Ack_all 369 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 272 -MEM_Inv 0 +L1_GET_INSTR [300 ] 300 +L1_GETS [209 ] 209 +L1_GETX [71 ] 71 +L1_UPGRADE [0 ] 0 +L1_PUTX [124 ] 124 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [43 ] 43 +L2_Replacement_clean [496 ] 496 +Mem_Data [547 ] 547 +Mem_Ack [539 ] 539 +WB_Data [62 ] 62 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [369 ] 369 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [272 ] 272 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 291 -NP L1_GETS 192 -NP L1_GETX 64 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- - -SS L1_GET_INSTR 9 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 286 -SS MEM_Inv 0 <-- - -M L1_GET_INSTR 0 <-- -M L1_GETS 12 -M L1_GETX 4 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 39 -M L2_Replacement_clean 69 -M MEM_Inv 0 <-- - -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 124 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 4 -MT L2_Replacement_clean 141 -MT MEM_Inv 0 <-- - -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 5 -M_I L1_GETX 3 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 539 -M_I MEM_Inv 0 <-- - -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 2 -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 2 -MT_I MEM_Inv 0 <-- - -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 60 -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 81 - -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 286 - -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- - -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 192 -ISS MEM_Inv 0 <-- - -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 291 -IS MEM_Inv 0 <-- - -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 64 -IM MEM_Inv 0 <-- - -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- - -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 272 -MT_MB MEM_Inv 0 <-- - -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- - -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- - -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- - -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +NP L1_GET_INSTR [291 ] 291 +NP L1_GETS [192 ] 192 +NP L1_GETX [64 ] 64 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 + +SS L1_GET_INSTR [9 ] 9 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [286 ] 286 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [0 ] 0 +M L1_GETS [12 ] 12 +M L1_GETX [4 ] 4 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [39 ] 39 +M L2_Replacement_clean [69 ] 69 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [124 ] 124 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [4 ] 4 +MT L2_Replacement_clean [141 ] 141 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [5 ] 5 +M_I L1_GETX [3 ] 3 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [539 ] 539 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [2 ] 2 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [2 ] 2 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [60 ] 60 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [81 ] 81 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [286 ] 286 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [192 ] 192 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [291 ] 291 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [64 ] 64 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [0 ] 0 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [272 ] 272 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 650 memory_reads: 547 memory_writes: 103 @@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 547 -Data 103 -Memory_Data 547 -Memory_Ack 103 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 436 +Fetch [547 ] 547 +Data [103 ] 103 +Memory_Data [547 ] 547 +Memory_Ack [103 ] 103 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [436 ] 436 - Transitions - -I Fetch 547 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- - -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- - -M Data 103 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 436 - -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 547 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- - -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 103 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- - -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- - -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- - -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +I Fetch [547 ] 547 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [103 ] 103 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [436 ] 436 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [547 ] 547 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [103 ] 103 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index b009b1ffa..243aba647 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 13:54:58 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 13:57:44 -M5 executing on svvint03 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:31:34 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index f42778f42..dd48ee784 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21475 # Simulator instruction rate (inst/s) -host_mem_usage 214848 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 863649 # Simulator tick rate (ticks/s) +host_inst_rate 25769 # Simulator instruction rate (inst/s) +host_mem_usage 211408 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 1036329 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000104 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 7f9336521..59f975e1e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,110 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +177,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +187,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +205,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,134 +218,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 6d22cb60b..86aa94fb6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:08:15 +Real time: Aug/05/2010 10:37:10 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.41 +Virtual_time_in_minutes: 0.00683333 +Virtual_time_in_hours: 0.000113889 +Virtual_time_in_days: 4.74537e-06 Ruby_current_time: 85988 Ruby_start_time: 0 Ruby_cycles: 85988 -mbytes_resident: 33.25 -mbytes_total: 33.2578 +mbytes_resident: 33.6484 +mbytes_total: 33.6562 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 85989 [ 85989 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 85989 ] Busy Controller Counts: L2Cache-0:0 @@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7143 -page_faults: 2153 +page_reclaims: 7386 +page_faults: 2090 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 2811 22488 +total_msg_count_Response_Data: 2562 184464 +total_msg_count_ResponseL2hit_Data: 249 17928 +total_msg_count_Writeback_Data: 1737 125064 +total_msg_count_Writeback_Control: 6480 51840 +total_msg_count_Unblock_Control: 2810 22480 +total_msgs: 16649 total_bytes: 424264 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.212617 @@ -190,972 +201,966 @@ links_utilized_percent_switch_3: 0.342645 outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -L1_Replacement 506 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 510 -Writeback_Ack 0 -Writeback_Ack_Data 502 -Writeback_Nack 0 -All_acks 58 -Use_Timeout 509 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +L1_Replacement [506 ] 506 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [510 ] 510 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [502 ] 502 +Writeback_Nack [0 ] 0 +All_acks [58 ] 58 +Use_Timeout [509 ] 509 - Transitions - -I Load 182 -I Ifetch 270 -I Store 58 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- - -M Load 82 -M Ifetch 1224 -M Store 33 -M L1_Replacement 406 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- - -M_W Load 49 -M_W Ifetch 1091 -M_W Store 7 -M_W L1_Replacement 4 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 444 - -MM Load 99 -MM Ifetch 0 <-- -MM Store 114 -MM L1_Replacement 96 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- - -MM_W Load 3 -MM_W Ifetch 0 <-- -MM_W Store 82 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 65 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 58 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 58 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 452 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 502 -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +I Load [182 ] 182 +I Ifetch [270 ] 270 +I Store [58 ] 58 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [82 ] 82 +M Ifetch [1224 ] 1224 +M Store [33 ] 33 +M L1_Replacement [406 ] 406 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [49 ] 49 +M_W Ifetch [1091 ] 1091 +M_W Store [7 ] 7 +M_W L1_Replacement [4 ] 4 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [444 ] 444 + +MM Load [99 ] 99 +MM Ifetch [0 ] 0 +MM Store [114 ] 114 +MM L1_Replacement [96 ] 96 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [3 ] 3 +MM_W Ifetch [0 ] 0 +MM_W Store [82 ] 82 +MM_W L1_Replacement [0 ] 0 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [65 ] 65 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [58 ] 58 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [58 ] 58 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [452 ] 452 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [502 ] 502 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GETS 455 -L1_GETX 58 -L1_PUTO 0 -L1_PUTX 502 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 44 -Data 44 -Data_Exclusive 383 -L1_WBCLEANDATA 396 -L1_WBDIRTYDATA 106 -Writeback_Ack 411 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 510 -L2_Replacement 411 +L1_GETS [455 ] 455 +L1_GETX [58 ] 58 +L1_PUTO [0 ] 0 +L1_PUTX [502 ] 502 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [44 ] 44 +Data [44 ] 44 +Data_Exclusive [383 ] 383 +L1_WBCLEANDATA [396 ] 396 +L1_WBDIRTYDATA [106 ] 106 +Writeback_Ack [411 ] 411 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [510 ] 510 +L2_Replacement [411 ] 411 - Transitions - -NP L1_GETS 383 -NP L1_GETX 44 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 502 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 69 -M L1_GETX 14 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 411 - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 396 -ILXW L1_WBDIRTYDATA 106 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 383 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 383 -IGS L2_Replacement 0 <-- - -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 44 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 44 -IGMO Exclusive_Unblock 44 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 14 -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 69 -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 3 -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 411 -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +NP L1_GETS [383 ] 383 +NP L1_GETX [44 ] 44 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [502 ] 502 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [69 ] 69 +M L1_GETX [14 ] 14 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [411 ] 411 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [396 ] 396 +ILXW L1_WBDIRTYDATA [106 ] 106 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [383 ] 383 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [383 ] 383 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [44 ] 44 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [44 ] 44 +IGMO Exclusive_Unblock [44 ] 44 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [14 ] 14 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [69 ] 69 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [3 ] 3 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [411 ] 411 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 504 memory_reads: 427 memory_writes: 77 @@ -1175,201 +1180,200 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 35 20 20 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 16 5 5 12 12 18 14 58 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 44 -GETS 383 -PUTX 411 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 426 -Clean_Writeback 334 -Dirty_Writeback 77 -Memory_Data 427 -Memory_Ack 77 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [44 ] 44 +GETS [383 ] 383 +PUTX [411 ] 411 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [426 ] 426 +Clean_Writeback [334 ] 334 +Dirty_Writeback [77 ] 77 +Memory_Data [427 ] 427 +Memory_Ack [77 ] 77 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 44 -I GETS 383 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 75 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -M GETX 0 <-- -M GETS 0 <-- -M PUTX 411 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 382 -IS Memory_Data 383 -IS Memory_Ack 1 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- - -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- - -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- - -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- - -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 44 -MM Memory_Data 44 -MM Memory_Ack 1 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- - - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 334 -MI Dirty_Writeback 77 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- - -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- - -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- - -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- - -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- - -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +I GETX [44 ] 44 +I GETS [383 ] 383 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [75 ] 75 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [411 ] 411 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [382 ] 382 +IS Memory_Data [383 ] 383 +IS Memory_Ack [1 ] 1 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [44 ] 44 +MM Memory_Data [44 ] 44 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [334 ] 334 +MI Dirty_Writeback [77 ] 77 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 52848bd4a..c8e6b0646 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 14:49:51 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:08:15 -M5 executing on svvint05 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:37:10 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index b9dc234c1..bc9801bf7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 14317 # Simulator instruction rate (inst/s) -host_mem_usage 214996 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 477706 # Simulator tick rate (ticks/s) +host_inst_rate 19822 # Simulator instruction rate (inst/s) +host_mem_usage 211548 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 661411 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000086 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 2b037e55f..1971d2a44 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,121 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +188,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +198,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +216,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,144 +229,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 3eaa7bb2f..dbdcc6601 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -13,12 +13,12 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered -virtual_net_2: active, ordered -virtual_net_3: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered virtual_net_4: active, unordered virtual_net_5: active, ordered virtual_net_6: inactive @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:55:46 +Real time: Aug/05/2010 10:43:25 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.25 +Virtual_time_in_minutes: 0.00416667 +Virtual_time_in_hours: 6.94444e-05 +Virtual_time_in_days: 2.89352e-06 -Ruby_current_time: 90308 +Ruby_current_time: 92099 Ruby_start_time: 0 -Ruby_cycles: 90308 +Ruby_cycles: 92099 -mbytes_resident: 33.1172 -mbytes_total: 33.125 +mbytes_resident: 33.5859 +mbytes_total: 33.5938 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 90309 [ 90309 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 92100 ] Busy Controller Counts: L1Cache-0:0 @@ -81,10 +70,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 283 count: 3294 average: 26.4159 | standard deviation: 58.1846 | 0 2776 0 0 0 0 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89 61 81 78 45 5 4 1 0 2 20 13 13 11 10 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 283 count: 2585 average: 19.2785 | standard deviation: 49.8133 | 0 2315 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 38 49 22 3 4 0 0 0 9 11 3 8 6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 273 count: 415 average: 66.3494 | standard deviation: 81.4668 | 0 233 0 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 34 18 20 1 0 1 0 2 6 2 10 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 259 count: 294 average: 32.8027 | standard deviation: 63.5503 | 0 228 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 9 11 3 1 0 0 0 0 5 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 293 count: 3294 average: 26.9596 | standard deviation: 59.7209 | 0 2781 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 293 count: 2585 average: 18.7741 | standard deviation: 50.0281 | 0 2315 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 72.1108 | standard deviation: 82.9193 | 0 233 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 277 count: 294 average: 35.1973 | standard deviation: 68.9222 | 0 233 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 2781 average: 2 | standard deviation: 0 | 0 0 2781 ] +miss_latency_L2Cache: [binsize: 1 max: 21 count: 23 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ] +miss_latency_Directory: [binsize: 2 max: 293 count: 490 average: 168.898 | standard deviation: 16.9003 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 489 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 293 count: 261 average: 167.479 | standard deviation: 13.0564 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ] +miss_latency_LD_Directory: [binsize: 2 max: 277 count: 173 average: 169.197 | standard deviation: 16.5371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 5 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 ] +miss_latency_ST_Directory: [binsize: 2 max: 277 count: 56 average: 174.589 | standard deviation: 28.9061 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +127,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7136 -page_faults: 2141 +page_reclaims: 7341 +page_faults: 2084 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,788 +136,896 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 3012 24096 +total_msg_count_Response_Data: 1470 105840 +total_msg_count_ResponseL2hit_Data: 69 4968 +total_msg_count_Writeback_Data: 1782 128304 +total_msg_count_Writeback_Control: 1206 9648 +total_msgs: 7539 total_bytes: 272856 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.160659 - links_utilized_percent_switch_0_link_0: 0.0646399 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.256677 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.167897 + links_utilized_percent_switch_0_link_0: 0.0626635 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.27313 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0939286 - links_utilized_percent_switch_1_link_0: 0.0641693 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.123688 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0864762 + links_utilized_percent_switch_1_link_0: 0.0682825 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.10467 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.120795 - links_utilized_percent_switch_2_link_0: 0.0213436 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.220246 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.131387 + links_utilized_percent_switch_2_link_0: 0.023358 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.239416 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.200204 - links_utilized_percent_switch_3_link_0: 0.25856 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.256677 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.0853745 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_3: 0.205739 + links_utilized_percent_switch_3_link_0: 0.250654 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.27313 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0934321 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 270 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 243 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100% + + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -L1_Replacement 502 -Data_Shared 59 -Data_Owner 0 -Data_All_Tokens 459 -Ack 8 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 -Request_Timeout 0 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 458 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Atomic [0 ] 0 +L1_Replacement [506 ] 506 +Data_Shared [18 ] 18 +Data_Owner [0 ] 0 +Data_All_Tokens [495 ] 495 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Request_Timeout [0 ] 0 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [494 ] 494 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 182 -NP Ifetch 270 -NP Store 58 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S Load 30 -S Ifetch 188 -S Store 8 -S L1_Replacement 50 -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M Load 67 -M Ifetch 1196 -M Store 29 -M L1_Replacement 356 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -MM Load 96 -MM Ifetch 0 <-- -MM Store 111 -MM L1_Replacement 96 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 0 <-- - -M_W Load 34 -M_W Ifetch 931 -M_W Store 3 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 389 - -MM_W Load 6 -MM_W Ifetch 0 <-- -MM_W Store 85 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 69 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 58 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 0 <-- -IM Request_Timeout 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 8 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 59 -IS Data_Owner 0 <-- -IS Data_All_Tokens 393 -IS Ack 7 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 0 <-- -IS Request_Timeout 0 <-- - -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [182 ] 182 +NP Ifetch [270 ] 270 +NP Store [58 ] 58 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S Load [6 ] 6 +S Ifetch [44 ] 44 +S Store [3 ] 3 +S Atomic [0 ] 0 +S L1_Replacement [15 ] 15 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M Load [78 ] 78 +M Ifetch [1233 ] 1233 +M Store [31 ] 31 +M Atomic [0 ] 0 +M L1_Replacement [391 ] 391 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +MM Load [98 ] 98 +MM Ifetch [0 ] 0 +MM Store [107 ] 107 +MM Atomic [0 ] 0 +MM L1_Replacement [96 ] 96 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [0 ] 0 + +M_W Load [47 ] 47 +M_W Ifetch [1038 ] 1038 +M_W Store [6 ] 6 +M_W Atomic [0 ] 0 +M_W L1_Replacement [4 ] 4 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [0 ] 0 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [427 ] 427 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +MM_W Load [4 ] 4 +MM_W Ifetch [0 ] 0 +MM_W Store [89 ] 89 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [0 ] 0 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [0 ] 0 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [67 ] 67 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data_Shared [0 ] 0 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [58 ] 58 +IM Ack [0 ] 0 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [0 ] 0 +IM Request_Timeout [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [3 ] 3 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [0 ] 0 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Shared [18 ] 18 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [434 ] 434 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [0 ] 0 +IS Request_Timeout [0 ] 0 + +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 + +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 + +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 491 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 491 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 88.391% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.609% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 491 100% + + --- L2Cache --- - Event Counts - -L1_GETS 445 -L1_GETS_Last_Token 7 -L1_GETX 66 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 463 -Writeback_Tokens 27 -Writeback_Shared_Data 0 -Writeback_All_Tokens 475 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 +L1_GETS [451 ] 451 +L1_GETS_Last_Token [1 ] 1 +L1_GETX [61 ] 61 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [500 ] 500 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [15 ] 15 +Writeback_All_Tokens [487 ] 487 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 - Transitions - -NP L1_GETS 386 -NP L1_GETX 48 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 27 -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 444 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I L1_GETS 0 <-- -I L1_GETS_Last_Token 7 -I L1_GETX 1 -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 34 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 8 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 5 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 31 -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 23 -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M L1_GETS 59 -M L1_GETX 12 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 398 -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 523 - memory_reads: 442 - memory_writes: 81 - memory_refreshes: 189 - memory_total_request_delays: 199 - memory_delays_per_request: 0.380497 - memory_delays_in_input_queue: 67 +NP L1_GETS [434 ] 434 +NP L1_GETX [56 ] 56 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [15 ] 15 +NP Writeback_All_Tokens [487 ] 487 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [6 ] 6 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [0 ] 0 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [1 ] 1 +S L1_GETX [0 ] 0 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [14 ] 14 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [16 ] 16 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [17 ] 17 +M L1_GETX [4 ] 4 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [464 ] 464 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 582 + memory_reads: 490 + memory_writes: 92 + memory_refreshes: 192 + memory_total_request_delays: 314 + memory_delays_per_request: 0.539519 + memory_delays_in_input_queue: 90 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 132 - memory_stalls_for_bank_busy: 41 + memory_delays_stalled_at_head_of_bank_queue: 224 + memory_stalls_for_bank_busy: 106 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 7 - memory_stalls_for_bus: 80 + memory_stalls_for_arbitration: 8 + memory_stalls_for_bus: 104 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 + memory_stalls_for_read_write_turnaround: 6 memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 19 10 0 41 20 19 31 22 5 3 6 4 21 40 20 3 4 6 7 14 10 16 14 41 16 5 5 12 12 18 14 65 + accesses_per_bank: 20 13 0 46 20 20 38 23 5 5 7 4 24 42 25 3 4 6 7 14 10 21 14 46 16 5 5 12 14 18 16 79 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 63 -GETS 409 -Lockdown 0 -Unlockdown 0 -Own_Lock_or_Unlock 0 -Data_Owner 6 -Data_All_Tokens 75 -Ack_Owner 25 -Ack_Owner_All_Tokens 323 -Tokens 0 -Ack_All_Tokens 18 -Request_Timeout 0 -Memory_Data 442 -Memory_Ack 81 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [57 ] 57 +GETS [434 ] 434 +Lockdown [0 ] 0 +Unlockdown [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [2 ] 2 +Data_All_Tokens [90 ] 90 +Ack_Owner [14 ] 14 +Ack_Owner_All_Tokens [374 ] 374 +Tokens [0 ] 0 +Ack_All_Tokens [14 ] 14 +Request_Timeout [0 ] 0 +Memory_Data [490 ] 490 +Memory_Ack [92 ] 92 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 49 -O GETS 393 -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 18 -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- - -NO GETX 5 -NO GETS 0 <-- -NO Lockdown 0 <-- -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 6 -NO Data_All_Tokens 75 -NO Ack_Owner 25 -NO Ack_Owner_All_Tokens 323 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -L GETX 0 <-- -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 0 <-- -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- - -O_W GETX 9 -O_W GETS 16 -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 81 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- - -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- - -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- - -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 442 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- - -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- - -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- - -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- - -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- - -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- - -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- - -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- - +O GETX [56 ] 56 +O GETS [434 ] 434 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [14 ] 14 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [1 ] 1 +NO GETS [0 ] 0 +NO Lockdown [0 ] 0 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [2 ] 2 +NO Data_All_Tokens [90 ] 90 +NO Ack_Owner [14 ] 14 +NO Ack_Owner_All_Tokens [374 ] 374 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [0 ] 0 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [92 ] 92 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [490 ] 490 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 5cc182def..9cf458143 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 15:54:34 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:55:46 -M5 executing on svvint04 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:43:25 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 90308 because target called exit() +Exiting @ tick 92099 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index d8ff49b26..e8b218502 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 18406 # Simulator instruction rate (inst/s) -host_mem_usage 214900 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 602029 # Simulator tick rate (ticks/s) +host_inst_rate 42948 # Simulator instruction rate (inst/s) +host_mem_usage 211392 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1534907 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000090 # Number of seconds simulated -sim_ticks 90308 # Number of ticks simulated +sim_seconds 0.000092 # Number of seconds simulated +sim_ticks 92099 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 90308 # number of cpu cycles simulated +system.cpu.numCycles 92099 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 14740fd64..4d36728d7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +65,110 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -73,7 +177,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -83,6 +187,7 @@ clock=1 debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false @@ -100,7 +205,7 @@ verbosity_string=none [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -113,114 +218,26 @@ type=Topology children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 9db9e0aa2..6e53a933a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -13,14 +13,14 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar -virtual_net_0: active, unordered -virtual_net_1: active, unordered +virtual_net_0: active, ordered +virtual_net_1: active, ordered virtual_net_2: active, unordered virtual_net_3: active, unordered -virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 11:48:25 +Real time: Aug/05/2010 14:44:19 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.33 -Virtual_time_in_minutes: 0.0055 -Virtual_time_in_hours: 9.16667e-05 -Virtual_time_in_days: 3.81944e-06 +Virtual_time_in_seconds: 0.21 +Virtual_time_in_minutes: 0.0035 +Virtual_time_in_hours: 5.83333e-05 +Virtual_time_in_days: 2.43056e-06 -Ruby_current_time: 81672 +Ruby_current_time: 78408 Ruby_start_time: 0 -Ruby_cycles: 81672 +Ruby_cycles: 78408 -mbytes_resident: 31.8555 -mbytes_total: 31.8633 +mbytes_resident: 33.3242 +mbytes_total: 33.332 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 81673 [ 81673 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 78409 ] Busy Controller Counts: L1Cache-0:0 @@ -80,10 +69,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 333 count: 3294 average: 23.7942 | standard deviation: 53.6415 | 0 2853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 74 46 111 83 4 0 4 2 0 2 2 0 0 1 1 2 0 0 0 2 2 2 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 243 count: 2585 average: 17.6507 | standard deviation: 45.0947 | 0 2337 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 47 26 56 63 2 0 2 1 0 1 2 0 0 0 1 1 0 0 0 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 333 count: 415 average: 57.9108 | standard deviation: 76.4181 | 0 269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 16 18 39 18 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 333 count: 294 average: 29.6531 | standard deviation: 64.3241 | 0 247 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 11 2 16 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 ] +miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] +miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ] +miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +imcomplete_dir_Times: 440 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ] +miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ] +miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 6878 -page_faults: 2029 +page_reclaims: 7298 +page_faults: 2071 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -124,453 +135,665 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 1323 10584 +total_msg_count_Response_Data: 1323 95256 +total_msg_count_Writeback_Data: 243 17496 +total_msg_count_Writeback_Control: 3582 28656 +total_msg_count_Unblock_Control: 1320 10560 +total_msgs: 7791 total_bytes: 162552 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.106447 - links_utilized_percent_switch_0_link_0: 0.0672507 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.145644 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.110878 + links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152707 - links_utilized_percent_switch_1_link_0: 0.0364109 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.269003 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.159064 + links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.207323 - links_utilized_percent_switch_2_link_0: 0.269003 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.145644 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 248 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 248 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 248 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 248 average: 4 | standard deviation: 0 | 0 0 0 0 248 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 193 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 193 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 75.6477% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 24.3523% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 193 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 193 average: 7.25389 | standard deviation: 1.56292 | 0 0 0 0 36 0 0 0 157 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_2: 0.215954 + links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 270 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 240 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100% + + --- L1Cache --- - Event Counts - -Load 437 -Ifetch 2603 -Store 306 -L2_Replacement 425 -L1_to_L2 502 -L2_to_L1D 47 -L2_to_L1I 22 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 441 -Writeback_Ack 425 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 441 +Load [428 ] 428 +Ifetch [2597 ] 2597 +Store [302 ] 302 +L2_Replacement [425 ] 425 +L1_to_L2 [502 ] 502 +Trigger_L2_to_L1D [47 ] 47 +Trigger_L2_to_L1I [22 ] 22 +Complete_L2_to_L1 [69 ] 69 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [441 ] 441 +Writeback_Ack [425 ] 425 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [441 ] 441 - Transitions - -I Load 146 -I Ifetch 248 -I Store 47 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- - -M Load 131 -M Ifetch 2337 -M Store 36 -M L2_Replacement 344 -M L1_to_L2 397 -M L2_to_L1D 23 -M L2_to_L1I 22 -M Other_GETX 0 <-- -M Other_GETS 0 <-- - -MM Load 138 -MM Ifetch 0 <-- -MM Store 211 -MM L2_Replacement 81 -MM L1_to_L2 105 -MM L2_to_L1D 24 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 47 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 0 <-- -M_W All_acks_no_sharers 394 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 47 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 394 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 22 -MI Ifetch 18 -MI Store 12 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 425 - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +I Load [146 ] 146 +I Ifetch [248 ] 248 +I Store [47 ] 47 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 + +M Load [131 ] 131 +M Ifetch [2337 ] 2337 +M Store [36 ] 36 +M L2_Replacement [344 ] 344 +M L1_to_L2 [397 ] 397 +M Trigger_L2_to_L1D [23 ] 23 +M Trigger_L2_to_L1I [22 ] 22 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 + +MM Load [138 ] 138 +MM Ifetch [0 ] 0 +MM Store [211 ] 211 +MM L2_Replacement [81 ] 81 +MM L1_to_L2 [105 ] 105 +MM Trigger_L2_to_L1D [24 ] 24 +MM Trigger_L2_to_L1I [0 ] 0 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [0 ] 0 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [47 ] 47 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 + +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [0 ] 0 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [394 ] 394 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [0 ] 0 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [0 ] 0 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [47 ] 47 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [0 ] 0 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [394 ] 394 + +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 + +MI Load [13 ] 13 +MI Ifetch [12 ] 12 +MI Store [8 ] 8 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [425 ] 425 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 + +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [0 ] 0 +MT Complete_L2_to_L1 [45 ] 45 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [0 ] 0 +MMT Store [0 ] 0 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [0 ] 0 +MMT Complete_L2_to_L1 [24 ] 24 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 522 memory_reads: 441 memory_writes: 81 - memory_refreshes: 171 - memory_total_request_delays: 124 - memory_delays_per_request: 0.237548 + memory_refreshes: 164 + memory_total_request_delays: 147 + memory_delays_per_request: 0.281609 memory_delays_in_input_queue: 2 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 122 - memory_stalls_for_bank_busy: 45 + memory_delays_stalled_at_head_of_bank_queue: 145 + memory_stalls_for_bank_busy: 27 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 8 + memory_stalls_for_arbitration: 6 memory_stalls_for_bus: 23 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 46 + memory_stalls_for_read_write_turnaround: 89 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 106 -GETS 464 -PUT 425 -Unblock 440 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 344 -Writeback_Exclusive_Dirty 81 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 441 -Memory_Ack 81 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [53 ] 53 +GETS [410 ] 410 +PUT [425 ] 425 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [440 ] 440 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [344 ] 344 +Writeback_Exclusive_Dirty [81 ] 81 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [441 ] 441 +Memory_Ack [81 ] 81 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 425 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -E GETX 47 -E GETS 394 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- - -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 0 <-- -NO_B Unblock 440 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- - -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- - -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 441 - -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- - -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- - -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- - -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- - -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- - -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- - -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- - -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- - -WB GETX 4 -WB GETS 15 -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 344 -WB Writeback_Exclusive_Dirty 81 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- - -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- - -WB_E_W GETX 55 -WB_E_W GETS 55 -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 81 - +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 + +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [425 ] 425 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +E GETX [47 ] 47 +E GETS [394 ] 394 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 + +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [440 ] 440 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 + +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 + +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 + +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 + +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [441 ] 441 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [4 ] 4 +WB GETS [14 ] 14 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [344 ] 344 +WB Writeback_Exclusive_Dirty [81 ] 81 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [2 ] 2 +WB_E_W GETS [2 ] 2 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 275f04f5f..76a97a409 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 28 2010 11:30:01 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 11:48:25 -M5 executing on svvint06 +M5 compiled Aug 5 2010 14:43:33 +M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates +M5 started Aug 5 2010 14:44:19 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 81672 because target called exit() +Exiting @ tick 78408 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 82f130963..58de899ed 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32212 # Simulator instruction rate (inst/s) -host_mem_usage 212236 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 1020887 # Simulator tick rate (ticks/s) +host_inst_rate 42947 # Simulator instruction rate (inst/s) +host_mem_usage 211060 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1306713 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000082 # Number of seconds simulated -sim_ticks 81672 # Number of ticks simulated +sim_seconds 0.000078 # Number of seconds simulated +sim_ticks 78408 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 81672 # number of cpu cycles simulated +system.cpu.numCycles 78408 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini index e8166d3de..82062647f 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini @@ -5,13 +5,14 @@ dummy=0 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -129,6 +137,48 @@ trace_addr=0 functional=system.funcmem.port[7] test=system.ruby.cpu_ruby_ports7.port[0] +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + [system.funcmem] type=PhysicalMemory file= @@ -139,168 +189,11 @@ range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort - -[system.ruby] -type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports0] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.cpu_ruby_ports1] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.cpu_ruby_ports2] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.cpu_ruby_ports3] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.cpu_ruby_ports4] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.cpu_ruby_ports5] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.cpu_ruby_ports6] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.cpu_ruby_ports7] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 -num_int_nodes=11 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] +[system.l1_cntrl0] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -312,34 +205,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] +[system.l1_cntrl1] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -351,34 +237,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] +[system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] +[system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.l1_cntrl2] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -390,34 +269,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] +[system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] +[system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node -int_node=3 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links3.ext_node] +[system.l1_cntrl3] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -429,34 +301,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] +[system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] +[system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node -int_node=4 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links4.ext_node] +[system.l1_cntrl4] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -468,34 +333,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] +[system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] +[system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node -int_node=5 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links5.ext_node] +[system.l1_cntrl5] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -507,34 +365,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] +[system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] +[system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node -int_node=6 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links6.ext_node] +[system.l1_cntrl6] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -546,34 +397,27 @@ to_l2_latency=1 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] +[system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] +[system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node -int_node=7 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links7.ext_node] +[system.l1_cntrl7] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 @@ -585,33 +429,26 @@ to_l2_latency=1 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] +[system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] +[system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links8] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node -int_node=8 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links8.ext_node] +[system.l2_cntrl0] type=L2Cache_Controller children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory buffer_size=0 l2_request_latency=2 l2_response_latency=2 @@ -621,63 +458,242 @@ to_l1_latency=1 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] +[system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 latency=15 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links9] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.l1_cntrl1.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.l1_cntrl2.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.l1_cntrl3.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.l1_cntrl4.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl4.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.l1_cntrl5.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl5.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.l1_cntrl6.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl6.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.l1_cntrl7.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl7.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +num_int_nodes=11 +print_config=false + +[system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node -int_node=9 +ext_node=system.l1_cntrl0 +int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl1 +int_node=1 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl2 +int_node=2 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 +[system.ruby.network.topology.ext_links3] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl3 +int_node=3 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl4 +int_node=4 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links5] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl5 +int_node=5 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links6] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl6 +int_node=6 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links7] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl7 +int_node=7 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links8] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=8 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links9] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=9 +latency=1 +weight=1 [system.ruby.network.topology.int_links0] type=IntLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 813d40bbf..7bfbcb96e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/01/2010 14:40:21 +Real time: Aug/20/2010 12:05:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 36 -Elapsed_time_in_minutes: 0.6 -Elapsed_time_in_hours: 0.01 -Elapsed_time_in_days: 0.000416667 +Elapsed_time_in_seconds: 39 +Elapsed_time_in_minutes: 0.65 +Elapsed_time_in_hours: 0.0108333 +Elapsed_time_in_days: 0.000451389 -Virtual_time_in_seconds: 35.01 -Virtual_time_in_minutes: 0.5835 -Virtual_time_in_hours: 0.009725 -Virtual_time_in_days: 0.000405208 +Virtual_time_in_seconds: 39.83 +Virtual_time_in_minutes: 0.663833 +Virtual_time_in_hours: 0.0110639 +Virtual_time_in_days: 0.000460995 -Ruby_current_time: 3725190 +Ruby_current_time: 3750455 Ruby_start_time: 0 -Ruby_cycles: 3725190 +Ruby_cycles: 3750455 -mbytes_resident: 32.2461 -mbytes_total: 324.797 -resident_ratio: 0.0992928 +mbytes_resident: 32.6211 +mbytes_total: 333.473 +resident_ratio: 0.0978341 -ruby_cycles_executed: [ 3725191 3725191 3725191 3725191 3725191 3725191 3725191 3725191 ] +ruby_cycles_executed: [ 3750456 3750456 3750456 3750456 3750456 3750456 3750456 3750456 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,26 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1208922 average: 1.94905 | standard deviation: 0.219893 | 0 61593 1147329 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1214418 average: 1.94809 | standard deviation: 0.221842 | 0 63038 1151380 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1236 count: 1208906 average: 47.2964 | standard deviation: 87.6519 | 820562 0 0 12801 11531 8846 17926 41165 25176 42518 9192 3581 16689 9654 11109 15654 179 11470 19382 8928 12543 981 6769 7960 7766 3717 2229 8680 5114 7916 3472 918 5454 4144 3683 4067 204 2886 3913 2437 2740 403 2323 2099 2111 1159 428 1944 1349 1530 988 155 1089 1034 847 865 77 656 640 552 475 81 515 444 389 282 37 336 235 215 200 29 194 171 135 105 16 91 109 70 51 12 63 49 53 38 4 44 29 26 30 3 26 26 25 12 1 4 10 9 7 0 6 7 5 2 0 6 0 5 2 0 1 2 2 0 0 4 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 1236 count: 786532 average: 30.7984 | standard deviation: 72.1119 | 626837 0 0 2820 2557 350 17926 15549 10430 19240 248 3575 7162 2230 5155 5701 177 5572 8288 3522 5103 977 2062 3583 2648 426 2229 3471 2058 3348 603 916 2377 1392 1591 1434 204 1177 1674 955 944 403 807 863 826 242 427 778 533 622 262 154 497 367 346 296 77 256 272 197 140 81 186 164 136 73 37 145 91 95 67 29 71 72 56 30 16 38 34 35 14 12 23 17 19 10 4 17 9 7 8 3 13 8 9 4 1 0 4 1 1 0 1 3 2 2 0 2 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 1156 count: 422374 average: 78.0186 | standard deviation: 104.189 | 193725 0 0 9981 8974 8496 0 25616 14746 23278 8944 6 9527 7424 5954 9953 2 5898 11094 5406 7440 4 4707 4377 5118 3291 0 5209 3056 4568 2869 2 3077 2752 2092 2633 0 1709 2239 1482 1796 0 1516 1236 1285 917 1 1166 816 908 726 1 592 667 501 569 0 400 368 355 335 0 329 280 253 209 0 191 144 120 133 0 123 99 79 75 0 53 75 35 37 0 40 32 34 28 0 27 20 19 22 0 13 18 16 8 0 4 6 8 6 0 5 4 3 0 0 4 0 4 2 0 0 2 1 0 0 3 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -87,12 +100,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1210 count: 1905105 average: 23.6634 | standard deviation: 66.5532 | 1608990 76937 36796 50533 28576 31102 16782 13165 11810 7909 7836 4054 2949 2343 1644 1494 693 507 326 210 185 91 78 27 23 21 7 5 5 2 0 2 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1194440 average: 0.00238773 | standard deviation: 0.054808 | 1191946 2149 332 13 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1210 count: 710665 average: 63.4314 | standard deviation: 96.7027 | 414550 76937 36796 50533 28576 31102 16782 13165 11810 7909 7836 4054 2949 2343 1644 1494 693 507 326 210 185 91 78 27 23 21 7 5 5 2 0 2 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 32 max: 1060 count: 1913633 average: 23.7314 | standard deviation: 66.6438 | 1615818 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603 | standard deviation: 0.057655 | 1196518 2179 404 22 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 1060 count: 714510 average: 63.5543 | standard deviation: 96.7696 | 416695 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 470535 average: 0.00501132 | standard deviation: 0.0808664 | 468529 1667 326 13 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 723905 average: 0.00068241 | standard deviation: 0.0264384 | 723417 482 6 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 472614 average: 0.0053257 | standard deviation: 0.0852408 | 470540 1653 399 22 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 726509 average: 0.000737775 | standard deviation: 0.0274142 | 725978 526 5 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -103,1391 +116,645 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1194440 average: 0.00238773 Resource Usage -------------- page_size: 4096 -user_time: 34 +user_time: 39 system_time: 0 -page_reclaims: 8476 +page_reclaims: 9465 page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 88 +block_inputs: 56 +block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 1169847 9358776 +total_msg_count_Request_Control: 1269806 10158448 +total_msg_count_Response_Data: 1417845 102084840 +total_msg_count_Response_Control: 1735406 13883248 +total_msgs: 5592904 total_bytes: 135485312 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.416862 - links_utilized_percent_switch_0_link_0: 0.175057 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.658668 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.416004 + links_utilized_percent_switch_0_link_0: 0.17421 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.657799 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Request_Control: 59786 478288 [ 59786 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 47776 3439872 [ 0 47776 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 31925 255400 [ 0 31925 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 49209 393672 [ 49209 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 41091 2958552 [ 0 41091 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 71705 573640 [ 0 30706 40999 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 49369 394952 [ 49369 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 41367 2978424 [ 0 41367 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 71737 573896 [ 0 30695 41042 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.417081 - links_utilized_percent_switch_1_link_0: 0.174646 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.659515 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.412969 + links_utilized_percent_switch_1_link_0: 0.173819 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.65212 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 59730 477840 [ 59730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 47651 3430872 [ 0 47651 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 31883 255064 [ 0 31883 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 49127 393016 [ 49127 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 41190 2965680 [ 0 41190 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 71527 572216 [ 0 30620 40907 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 49257 394056 [ 49257 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 40912 2945664 [ 0 40912 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 71684 573472 [ 0 30672 41012 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.411516 - links_utilized_percent_switch_2_link_0: 0.173509 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.649523 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.4136 + links_utilized_percent_switch_2_link_0: 0.173041 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.654158 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 59117 472936 [ 59117 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 47372 3410784 [ 0 47372 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 48775 390200 [ 48775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 40476 2914272 [ 0 40476 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 70860 566880 [ 0 30387 40473 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 49047 392376 [ 49047 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 41125 2961000 [ 0 41125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 71506 572048 [ 0 30453 41053 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.41051 - links_utilized_percent_switch_3_link_0: 0.172967 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.648053 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.410067 + links_utilized_percent_switch_3_link_0: 0.172661 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.647473 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Request_Control: 58969 471752 [ 58969 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 47235 3400920 [ 0 47235 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 31383 251064 [ 0 31383 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 48705 389640 [ 48705 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 40369 2906568 [ 0 40369 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 70798 566384 [ 0 30334 40464 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 48856 390848 [ 48856 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 40642 2926224 [ 0 40642 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 71030 568240 [ 0 30194 40836 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.409606 - links_utilized_percent_switch_4_link_0: 0.172646 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.646567 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.407326 + links_utilized_percent_switch_4_link_0: 0.17208 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.642573 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Request_Control: 58775 470200 [ 58775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 47067 3388824 [ 0 47067 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 32132 257056 [ 0 32132 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 48558 388464 [ 48558 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 40298 2901456 [ 0 40298 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 70477 563816 [ 0 30185 40292 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 48686 389488 [ 48686 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 40277 2899944 [ 0 40277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 70809 566472 [ 0 30317 40492 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.405919 - links_utilized_percent_switch_5_link_0: 0.171186 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.640652 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.408786 + links_utilized_percent_switch_5_link_0: 0.171315 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.646256 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 58294 466352 [ 58294 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 46694 3361968 [ 0 46694 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 48108 384864 [ 48108 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 39921 2874312 [ 0 39921 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 69913 559304 [ 0 29973 39940 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 48502 388016 [ 48502 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 40634 2925648 [ 0 40634 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 70543 564344 [ 0 30139 40404 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.403773 - links_utilized_percent_switch_6_link_0: 0.170945 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.636601 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.405763 + links_utilized_percent_switch_6_link_0: 0.170848 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.640678 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Request_Control: 58092 464736 [ 58092 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 46651 3358872 [ 0 46651 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 48107 384856 [ 48107 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 39615 2852280 [ 0 39615 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 69650 557200 [ 0 29918 39732 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 48385 387080 [ 48385 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 40226 2896272 [ 0 40226 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 70148 561184 [ 0 30034 40114 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.401324 - links_utilized_percent_switch_7_link_0: 0.17008 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.632569 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.399042 + links_utilized_percent_switch_7_link_0: 0.169071 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.629013 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Request_Control: 57772 462176 [ 57772 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 46420 3342240 [ 0 46420 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 31312 250496 [ 0 31312 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 47770 382160 [ 47770 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 39360 2833920 [ 0 39360 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 69278 554224 [ 0 29764 39514 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 47845 382760 [ 47845 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 39394 2836368 [ 0 39394 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 69426 555408 [ 0 29802 39624 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 1.37991 - links_utilized_percent_switch_8_link_0: 0.521364 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 2.23846 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 1.37261 + links_utilized_percent_switch_8_link_0: 0.520924 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 2.22429 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 388358 3106864 [ 388358 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 93674 6744528 [ 0 93674 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 322320 2578560 [ 0 0 322320 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 324576 2596608 [ 0 0 324576 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 322321 2578568 [ 322321 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 148215 10671480 [ 0 148215 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 11479 91832 [ 0 11479 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 324578 2596624 [ 324578 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 148028 10658016 [ 0 148028 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 11586 92688 [ 0 11586 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.24155e-05 - links_utilized_percent_switch_9_link_0: 6.71107e-07 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.41598e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.23318e-05 + links_utilized_percent_switch_9_link_0: 6.66586e-07 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.39971e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.76096 - links_utilized_percent_switch_10_link_0: 0.700226 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.698585 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.694037 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.691867 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.690582 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.684742 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.683781 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.68032 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 2.08546 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 2.68443e-06 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 59786 478288 [ 59786 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 47776 3439872 [ 0 47776 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 31925 255400 [ 0 31925 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 59730 477840 [ 59730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 47651 3430872 [ 0 47651 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 31883 255064 [ 0 31883 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 59117 472936 [ 59117 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 47372 3410784 [ 0 47372 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 58969 471752 [ 58969 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 47235 3400920 [ 0 47235 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 31383 251064 [ 0 31383 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 58775 470200 [ 58775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 47067 3388824 [ 0 47067 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 32132 257056 [ 0 32132 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 58294 466352 [ 58294 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 46694 3361968 [ 0 46694 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 58092 464736 [ 58092 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 46651 3358872 [ 0 46651 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 57772 462176 [ 57772 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 46420 3342240 [ 0 46420 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 31312 250496 [ 0 31312 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 388359 3106872 [ 388359 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 93674 6744528 [ 0 93674 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 322321 2578568 [ 0 0 322321 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.759188 + links_utilized_percent_switch_10_link_0: 0.696839 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.695276 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.692165 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.690646 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.68832 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.68526 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.683393 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.676283 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 2.0837 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 2.66634e-06 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 324577 2596616 [ 0 0 324577 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 100001 -Ifetch 0 -Store 53802 -Inv 30706 -L1_Replacement 0 -Fwd_GETX 17069 -Fwd_GETS 12011 -Fwd_GET_INSTR 0 -Data 10461 -Data_Exclusive 0 -DataS_fromL1 11918 -Data_all_Acks 25397 -Ack 20032 -Ack_all 11893 -WB_Ack 0 +Load [98631 98244 97407 96638 100000 99918 99521 98787 ] 789146 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [52748 52924 52660 51759 54108 53759 53950 53363 ] 425271 +Inv [30317 30139 30034 29802 30695 30672 30453 30194 ] 242306 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039 +Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269 +Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 +Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684 +Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268 +Data_all_Acks [24963 25105 25087 24473 25787 25589 25330 25061 ] 201395 +Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622 +Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270 +WB_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 20126 -I Ifetch 0 <-- -I Store 10788 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 34065 -S Ifetch 0 <-- -S Store 18293 -S Inv 11715 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45808 -M Ifetch 0 <-- -M Store 24721 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 17069 -M Fwd_GETS 12011 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2130 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11918 -IS Data_all_Acks 6079 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10461 -IM Data_all_Acks 17188 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16861 -SM L1_Replacement 0 <-- -SM Ack 20032 -SM Ack_all 11893 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2130 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 1 --- - - Event Counts - -Load 99730 -Ifetch 0 -Store 53653 -Inv 30620 -L1_Replacement 0 -Fwd_GETX 17030 -Fwd_GETS 12080 -Fwd_GET_INSTR 0 -Data 10364 -Data_Exclusive 0 -DataS_fromL1 11797 -Data_all_Acks 25490 -Ack 20045 -Ack_all 11838 -WB_Ack 0 +NP Load [2 2 1 2 2 2 2 1 ] 14 +NP Ifetch [0 0 0 0 0 0 0 0 ] 0 +NP Store [0 0 1 0 0 0 0 1 ] 2 +NP Inv [0 0 0 0 0 0 0 0 ] 0 +NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 + +I Load [20055 19731 19824 19834 20085 20223 19939 19922 ] 159613 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [10642 10737 10713 10485 10952 10852 10710 10852 ] 85943 +I Inv [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 + +S Load [33152 33048 32637 32620 33721 34023 33841 33185 ] 266227 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [17987 18032 17846 17524 18330 18180 18396 18080 ] 144375 +S Inv [11616 11475 11582 11602 11637 11749 11468 11453 ] 92582 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 + +E Load [0 0 0 0 0 0 0 0 ] 0 +E Ifetch [0 0 0 0 0 0 0 0 ] 0 +E Store [0 0 0 0 0 0 0 0 ] 0 +E Inv [0 0 0 0 0 0 0 0 ] 0 +E L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 + +M Load [45422 45463 44945 44182 46192 45670 45739 45679 ] 363292 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [24119 24155 24100 23750 24826 24727 24844 24430 ] 194951 +M Inv [0 0 0 0 0 0 0 0 ] 0 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039 +M Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269 +M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 + +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS Inv [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +IS DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268 +IS Data_all_Acks [6088 6007 6204 6122 6122 6065 5894 5919 ] 48421 + +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM Inv [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684 +IM Data_all_Acks [16771 17009 16818 16254 17460 17346 17338 17043 ] 136039 +IM Ack [0 0 0 0 0 0 0 0 ] 0 + +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM Inv [16597 16575 16387 16103 16853 16745 16887 16642 ] 132789 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622 +SM Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270 + +IS_I Load [0 0 0 0 0 0 0 0 ] 0 +IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS_I Store [0 0 0 0 0 0 0 0 ] 0 +IS_I Inv [0 0 0 0 0 0 0 0 ] 0 +IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 +IS_I Data_all_Acks [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935 + +M_I Load [0 0 0 0 0 0 0 0 ] 0 +M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_I Store [0 0 0 0 0 0 0 0 ] 0 +M_I Inv [0 0 0 0 0 0 0 0 ] 0 +M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 +M_I WB_Ack [0 0 0 0 0 0 0 0 ] 0 + +E_I Load [0 0 0 0 0 0 0 0 ] 0 +E_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +E_I Store [0 0 0 0 0 0 0 0 ] 0 +E_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 + +Cache Stats: system.l1_cntrl1.L1IcacheMemory + system.l1_cntrl1.L1IcacheMemory_total_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl1.L1DcacheMemory + system.l1_cntrl1.L1DcacheMemory_total_misses: 0 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1IcacheMemory + system.l1_cntrl2.L1IcacheMemory_total_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1DcacheMemory + system.l1_cntrl2.L1DcacheMemory_total_misses: 0 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1IcacheMemory + system.l1_cntrl3.L1IcacheMemory_total_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1DcacheMemory + system.l1_cntrl3.L1DcacheMemory_total_misses: 0 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.L1IcacheMemory + system.l1_cntrl4.L1IcacheMemory_total_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.L1DcacheMemory + system.l1_cntrl4.L1DcacheMemory_total_misses: 0 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1IcacheMemory + system.l1_cntrl5.L1IcacheMemory_total_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1DcacheMemory + system.l1_cntrl5.L1DcacheMemory_total_misses: 0 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.L1IcacheMemory + system.l1_cntrl6.L1IcacheMemory_total_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.L1DcacheMemory + system.l1_cntrl6.L1DcacheMemory_total_misses: 0 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 20015 -I Ifetch 0 <-- -I Store 10764 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33729 -S Ifetch 0 <-- -S Store 18346 -S Inv 11564 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45986 -M Ifetch 0 <-- -M Store 24541 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 17030 -M Fwd_GETS 12080 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2185 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11797 -IS Data_all_Acks 6033 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10364 -IM Data_all_Acks 17272 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16871 -SM L1_Replacement 0 <-- -SM Ack 20045 -SM Ack_all 11838 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2185 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 2 --- - - Event Counts - -Load 99194 -Ifetch 0 -Store 53073 -Inv 30387 -L1_Replacement 0 -Fwd_GETX 16984 -Fwd_GETS 11746 -Fwd_GET_INSTR 0 -Data 10273 -Data_Exclusive 0 -DataS_fromL1 11743 -Data_all_Acks 25356 -Ack 19945 -Ack_all 11674 -WB_Ack 0 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 20042 -I Ifetch 0 <-- -I Store 10810 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33640 -S Ifetch 0 <-- -S Store 17921 -S Inv 11754 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45511 -M Ifetch 0 <-- -M Store 24341 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16984 -M Fwd_GETS 11746 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2114 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11743 -IS Data_all_Acks 6186 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10273 -IM Data_all_Acks 17056 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16519 -SM L1_Replacement 0 <-- -SM Ack 19945 -SM Ack_all 11674 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2114 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 3 --- - - Event Counts - -Load 98276 -Ifetch 0 -Store 53109 -Inv 30334 -L1_Replacement 0 -Fwd_GETX 16901 -Fwd_GETS 11734 -Fwd_GET_INSTR 0 -Data 10144 -Data_Exclusive 0 -DataS_fromL1 11829 -Data_all_Acks 25262 -Ack 19771 -Ack_all 11612 -WB_Ack 0 +Cache Stats: system.l1_cntrl7.L1IcacheMemory + system.l1_cntrl7.L1IcacheMemory_total_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 20068 -I Ifetch 0 <-- -I Store 10669 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33256 -S Ifetch 0 <-- -S Store 17966 -S Inv 11705 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44951 -M Ifetch 0 <-- -M Store 24473 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16901 -M Fwd_GETS 11734 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2131 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11829 -IS Data_all_Acks 6108 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10144 -IM Data_all_Acks 17023 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16498 -SM L1_Replacement 0 <-- -SM Ack 19771 -SM Ack_all 11612 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2131 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 4 --- - - Event Counts - -Load 98292 -Ifetch 0 -Store 52852 -Inv 30185 -L1_Replacement 0 -Fwd_GETX 16882 -Fwd_GETS 11708 -Fwd_GET_INSTR 0 -Data 10341 -Data_Exclusive 0 -DataS_fromL1 11702 -Data_all_Acks 25024 -Ack 20302 -Ack_all 11830 -WB_Ack 0 - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19965 -I Ifetch 0 <-- -I Store 10757 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33223 -S Ifetch 0 <-- -S Store 17834 -S Inv 11737 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45102 -M Ifetch 0 <-- -M Store 24261 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16882 -M Fwd_GETS 11708 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2103 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11702 -IS Data_all_Acks 6161 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10341 -IM Data_all_Acks 16760 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16345 -SM L1_Replacement 0 <-- -SM Ack 20302 -SM Ack_all 11830 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2103 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 97731 -Ifetch 0 -Store 52263 -Inv 29973 -L1_Replacement 0 -Fwd_GETX 16721 -Fwd_GETS 11600 -Fwd_GET_INSTR 0 -Data 10293 -Data_Exclusive 0 -DataS_fromL1 11619 -Data_all_Acks 24782 -Ack 19914 -Ack_all 11705 -WB_Ack 0 +Cache Stats: system.l1_cntrl7.L1DcacheMemory + system.l1_cntrl7.L1DcacheMemory_total_misses: 0 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19786 -I Ifetch 0 <-- -I Store 10688 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33197 -S Ifetch 0 <-- -S Store 17632 -S Inv 11674 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44747 -M Ifetch 0 <-- -M Store 23942 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16721 -M Fwd_GETS 11600 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2079 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11619 -IS Data_all_Acks 6087 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10293 -IM Data_all_Acks 16616 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16220 -SM L1_Replacement 0 <-- -SM Ack 19914 -SM Ack_all 11705 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2079 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 97203 -Ifetch 0 -Store 51898 -Inv 29918 -L1_Replacement 0 -Fwd_GETX 16733 -Fwd_GETS 11441 -Fwd_GET_INSTR 0 -Data 10195 -Data_Exclusive 0 -DataS_fromL1 11558 -Data_all_Acks 24898 -Ack 19843 -Ack_all 11649 -WB_Ack 0 - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19932 -I Ifetch 0 <-- -I Store 10583 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 32522 -S Ifetch 0 <-- -S Store 17590 -S Inv 11601 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44749 -M Ifetch 0 <-- -M Store 23723 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16733 -M Fwd_GETS 11441 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2181 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11558 -IS Data_all_Acks 6192 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10195 -IM Data_all_Acks 16525 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16136 -SM L1_Replacement 0 <-- -SM Ack 19843 -SM Ack_all 11649 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2181 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 96112 -Ifetch 0 -Store 51732 -Inv 29764 -L1_Replacement 0 -Fwd_GETX 16656 -Fwd_GETS 11352 -Fwd_GET_INSTR 0 -Data 10123 -Data_Exclusive 0 -DataS_fromL1 11506 -Data_all_Acks 24791 -Ack 19841 -Ack_all 11471 -WB_Ack 0 +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19760 -I Ifetch 0 <-- -I Store 10518 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 32094 -S Ifetch 0 <-- -S Store 17490 -S Inv 11509 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44257 -M Ifetch 0 <-- -M Store 23723 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16656 -M Fwd_GETS 11352 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2113 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11506 -IS Data_all_Acks 6141 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10123 -IM Data_all_Acks 16537 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16142 -SM L1_Replacement 0 <-- -SM Ack 19841 -SM Ack_all 11471 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2113 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- + + --- L2Cache --- - Event Counts - -L1_GET_INSTR 0 -L1_GETS 2024976 -L1_GETX 2555360 -L1_UPGRADE 315967 -L1_PUTX 0 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 0 -L2_Replacement_clean 0 -Mem_Data 2 -Mem_Ack 0 -WB_Data 93672 -WB_Data_clean 0 -Ack 0 -Ack_all 0 -Unblock 93672 -Unblock_Cancel 0 -Exclusive_Unblock 228648 -MEM_Inv 0 +L1_GET_INSTR [0 ] 0 +L1_GETS [2029346 ] 2029346 +L1_GETX [2583035 ] 2583035 +L1_UPGRADE [318717 ] 318717 +L1_PUTX [0 ] 0 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [0 ] 0 +L2_Replacement_clean [0 ] 0 +Mem_Data [2 ] 2 +Mem_Ack [0 ] 0 +WB_Data [94268 ] 94268 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [0 ] 0 +Unblock [94268 ] 94268 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [230308 ] 230308 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 0 <-- -NP L1_GETS 1 -NP L1_GETX 1 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- - -SS L1_GET_INSTR 0 <-- -SS L1_GETS 66019 -SS L1_GETX 82194 -SS L1_UPGRADE 11479 -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 0 <-- -SS MEM_Inv 0 <-- - -M L1_GET_INSTR 0 <-- -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 0 <-- -M L2_Replacement_clean 0 <-- -M MEM_Inv 0 <-- - -MT L1_GET_INSTR 0 <-- -MT L1_GETS 93672 -MT L1_GETX 134976 -MT L1_PUTX 0 <-- -MT L1_PUTX_old 0 <-- -MT L2_Replacement 0 <-- -MT L2_Replacement_clean 0 <-- -MT MEM_Inv 0 <-- - -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 0 <-- -M_I L1_GETX 0 <-- -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 0 <-- -M_I MEM_Inv 0 <-- - -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 0 <-- -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 0 <-- -MT_I MEM_Inv 0 <-- - -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 0 <-- -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 0 <-- - -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 0 <-- - -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- - -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 1 -ISS L1_GETX 1 -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 0 <-- -ISS MEM_Inv 0 <-- - -IS L1_GET_INSTR 0 <-- -IS L1_GETS 2 -IS L1_GETX 99 -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 1 -IS MEM_Inv 0 <-- - -IM L1_GET_INSTR 0 <-- -IM L1_GETS 144 -IM L1_GETX 108 -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 1 -IM MEM_Inv 0 <-- - -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 469780 -SS_MB L1_GETX 567094 -SS_MB L1_UPGRADE 263602 -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 93671 -SS_MB MEM_Inv 0 <-- - -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 856977 -MT_MB L1_GETX 1064404 -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 134977 -MT_MB MEM_Inv 0 <-- - -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- - -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 384472 -MT_IIB L1_GETX 500985 -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 93672 -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- - -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- - -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 153908 -MT_SB L1_GETX 205498 -MT_SB L1_UPGRADE 40886 -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 93672 -MT_SB MEM_Inv 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +NP L1_GET_INSTR [0 ] 0 +NP L1_GETS [2 ] 2 +NP L1_GETX [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 + +SS L1_GET_INSTR [0 ] 0 +SS L1_GETS [65342 ] 65342 +SS L1_GETX [82684 ] 82684 +SS L1_UPGRADE [11586 ] 11586 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [0 ] 0 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [0 ] 0 +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [0 ] 0 +M L2_Replacement_clean [0 ] 0 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [94269 ] 94269 +MT L1_GETX [136039 ] 136039 +MT L1_PUTX [0 ] 0 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L2_Replacement_clean [0 ] 0 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [0 ] 0 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [0 ] 0 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [0 ] 0 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [0 ] 0 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [0 ] 0 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [0 ] 0 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [2 ] 2 +ISS L1_GETX [1 ] 1 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [0 ] 0 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [10 ] 10 +IS L1_GETX [60 ] 60 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [2 ] 2 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [0 ] 0 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [471755 ] 471755 +SS_MB L1_GETX [572825 ] 572825 +SS_MB L1_UPGRADE [265946 ] 265946 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [94269 ] 94269 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [858796 ] 858796 +MT_MB L1_GETX [1078050 ] 1078050 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [136039 ] 136039 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [384618 ] 384618 +MT_IIB L1_GETX [506028 ] 506028 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [94268 ] 94268 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [154552 ] 154552 +MT_SB L1_GETX [207348 ] 207348 +MT_SB L1_UPGRADE [41185 ] 41185 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [94268 ] 94268 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -1507,67 +774,66 @@ Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 2 -Data 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 0 +Fetch [2 ] 2 +Data [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [0 ] 0 - Transitions - -I Fetch 2 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- - -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- - -M Data 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 0 <-- - -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 2 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- - -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- - -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- - -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- - -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +I Fetch [2 ] 2 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [0 ] 0 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [2 ] 2 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE
\ No newline at end of file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr index a000ce3a0..e36729355 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @370057 -system.cpu1: completed 10000 read accesses @372602 -system.cpu0: completed 10000 read accesses @380072 -system.cpu3: completed 10000 read accesses @380676 -system.cpu4: completed 10000 read accesses @383371 -system.cpu2: completed 10000 read accesses @385679 -system.cpu6: completed 10000 read accesses @386340 -system.cpu7: completed 10000 read accesses @389231 -system.cpu5: completed 20000 read accesses @746317 -system.cpu0: completed 20000 read accesses @748763 -system.cpu3: completed 20000 read accesses @752788 -system.cpu1: completed 20000 read accesses @753263 -system.cpu4: completed 20000 read accesses @763818 -system.cpu6: completed 20000 read accesses @765866 -system.cpu2: completed 20000 read accesses @771677 -system.cpu7: completed 20000 read accesses @772771 -system.cpu0: completed 30000 read accesses @1112242 -system.cpu1: completed 30000 read accesses @1129327 -system.cpu3: completed 30000 read accesses @1129794 -system.cpu5: completed 30000 read accesses @1131833 -system.cpu2: completed 30000 read accesses @1142425 -system.cpu4: completed 30000 read accesses @1144628 -system.cpu6: completed 30000 read accesses @1153431 -system.cpu7: completed 30000 read accesses @1154016 -system.cpu0: completed 40000 read accesses @1484294 -system.cpu1: completed 40000 read accesses @1505996 -system.cpu3: completed 40000 read accesses @1507887 -system.cpu2: completed 40000 read accesses @1512800 -system.cpu4: completed 40000 read accesses @1520410 -system.cpu5: completed 40000 read accesses @1522723 -system.cpu6: completed 40000 read accesses @1538655 -system.cpu7: completed 40000 read accesses @1539216 -system.cpu0: completed 50000 read accesses @1860160 -system.cpu3: completed 50000 read accesses @1882708 -system.cpu1: completed 50000 read accesses @1883329 -system.cpu2: completed 50000 read accesses @1891575 -system.cpu4: completed 50000 read accesses @1896200 -system.cpu5: completed 50000 read accesses @1912575 -system.cpu6: completed 50000 read accesses @1917985 -system.cpu7: completed 50000 read accesses @1929708 -system.cpu0: completed 60000 read accesses @2233080 -system.cpu1: completed 60000 read accesses @2253689 -system.cpu3: completed 60000 read accesses @2259715 -system.cpu2: completed 60000 read accesses @2264515 -system.cpu4: completed 60000 read accesses @2278281 -system.cpu5: completed 60000 read accesses @2291280 -system.cpu6: completed 60000 read accesses @2305718 -system.cpu7: completed 60000 read accesses @2318114 -system.cpu0: completed 70000 read accesses @2615296 -system.cpu1: completed 70000 read accesses @2621479 -system.cpu2: completed 70000 read accesses @2635267 -system.cpu3: completed 70000 read accesses @2642310 -system.cpu4: completed 70000 read accesses @2659144 -system.cpu5: completed 70000 read accesses @2668163 -system.cpu6: completed 70000 read accesses @2691243 -system.cpu7: completed 70000 read accesses @2706192 -system.cpu0: completed 80000 read accesses @2986810 -system.cpu1: completed 80000 read accesses @2994418 -system.cpu2: completed 80000 read accesses @3009400 -system.cpu3: completed 80000 read accesses @3028789 -system.cpu4: completed 80000 read accesses @3033010 -system.cpu5: completed 80000 read accesses @3042800 -system.cpu6: completed 80000 read accesses @3071603 -system.cpu7: completed 80000 read accesses @3108423 -system.cpu0: completed 90000 read accesses @3351259 -system.cpu1: completed 90000 read accesses @3361381 -system.cpu2: completed 90000 read accesses @3381198 -system.cpu4: completed 90000 read accesses @3406636 -system.cpu3: completed 90000 read accesses @3411857 -system.cpu5: completed 90000 read accesses @3424074 -system.cpu6: completed 90000 read accesses @3457139 -system.cpu7: completed 90000 read accesses @3490206 -system.cpu0: completed 100000 read accesses @3725190 +system.cpu0: completed 10000 read accesses @371396 +system.cpu2: completed 10000 read accesses @374647 +system.cpu7: completed 10000 read accesses @377314 +system.cpu1: completed 10000 read accesses @379478 +system.cpu3: completed 10000 read accesses @380787 +system.cpu5: completed 10000 read accesses @386046 +system.cpu4: completed 10000 read accesses @386470 +system.cpu6: completed 10000 read accesses @394077 +system.cpu0: completed 20000 read accesses @748308 +system.cpu2: completed 20000 read accesses @750148 +system.cpu1: completed 20000 read accesses @752701 +system.cpu3: completed 20000 read accesses @761044 +system.cpu5: completed 20000 read accesses @762156 +system.cpu4: completed 20000 read accesses @766351 +system.cpu6: completed 20000 read accesses @775961 +system.cpu7: completed 20000 read accesses @776472 +system.cpu2: completed 30000 read accesses @1125160 +system.cpu1: completed 30000 read accesses @1125369 +system.cpu0: completed 30000 read accesses @1130636 +system.cpu3: completed 30000 read accesses @1139985 +system.cpu5: completed 30000 read accesses @1141453 +system.cpu4: completed 30000 read accesses @1142264 +system.cpu6: completed 30000 read accesses @1154957 +system.cpu7: completed 30000 read accesses @1163543 +system.cpu2: completed 40000 read accesses @1501376 +system.cpu1: completed 40000 read accesses @1506717 +system.cpu0: completed 40000 read accesses @1507617 +system.cpu3: completed 40000 read accesses @1521033 +system.cpu4: completed 40000 read accesses @1523666 +system.cpu5: completed 40000 read accesses @1527373 +system.cpu6: completed 40000 read accesses @1547890 +system.cpu7: completed 40000 read accesses @1551332 +system.cpu2: completed 50000 read accesses @1879261 +system.cpu0: completed 50000 read accesses @1879360 +system.cpu1: completed 50000 read accesses @1885794 +system.cpu3: completed 50000 read accesses @1900931 +system.cpu4: completed 50000 read accesses @1902181 +system.cpu5: completed 50000 read accesses @1910820 +system.cpu6: completed 50000 read accesses @1931247 +system.cpu7: completed 50000 read accesses @1940656 +system.cpu0: completed 60000 read accesses @2246405 +system.cpu1: completed 60000 read accesses @2255112 +system.cpu2: completed 60000 read accesses @2258276 +system.cpu3: completed 60000 read accesses @2284120 +system.cpu4: completed 60000 read accesses @2284604 +system.cpu5: completed 60000 read accesses @2293116 +system.cpu6: completed 60000 read accesses @2311203 +system.cpu7: completed 60000 read accesses @2336896 +system.cpu0: completed 70000 read accesses @2626542 +system.cpu1: completed 70000 read accesses @2633209 +system.cpu2: completed 70000 read accesses @2638509 +system.cpu4: completed 70000 read accesses @2659805 +system.cpu3: completed 70000 read accesses @2663605 +system.cpu5: completed 70000 read accesses @2671213 +system.cpu6: completed 70000 read accesses @2693680 +system.cpu7: completed 70000 read accesses @2725734 +system.cpu0: completed 80000 read accesses @2999116 +system.cpu1: completed 80000 read accesses @3008858 +system.cpu2: completed 80000 read accesses @3014566 +system.cpu3: completed 80000 read accesses @3028069 +system.cpu4: completed 80000 read accesses @3040014 +system.cpu5: completed 80000 read accesses @3055346 +system.cpu6: completed 80000 read accesses @3080851 +system.cpu7: completed 80000 read accesses @3115153 +system.cpu0: completed 90000 read accesses @3374370 +system.cpu1: completed 90000 read accesses @3384044 +system.cpu2: completed 90000 read accesses @3385035 +system.cpu3: completed 90000 read accesses @3412877 +system.cpu4: completed 90000 read accesses @3422171 +system.cpu5: completed 90000 read accesses @3435207 +system.cpu6: completed 90000 read accesses @3466955 +system.cpu7: completed 90000 read accesses @3499833 +system.cpu0: completed 100000 read accesses @3750455 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index d6fbf79bb..9fce5fb80 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:38:07 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:39:45 -M5 executing on phenom -command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory +M5 compiled Aug 20 2010 12:04:46 +M5 revision c4b5df973361 7570 default qtip tip brad/regress_updates +M5 started Aug 20 2010 12:05:10 +M5 executing on SC2B0629 +command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3725190 because maximum number of loads reached +Exiting @ tick 3750455 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index a684f8cc5..e2e446721 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 332596 # Number of bytes of host memory used -host_seconds 35.19 # Real time elapsed on the host -host_tick_rate 105869 # Simulator tick rate (ticks/s) +host_mem_usage 341480 # Number of bytes of host memory used +host_seconds 39.63 # Real time elapsed on the host +host_tick_rate 94625 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003725 # Number of seconds simulated -sim_ticks 3725190 # Number of ticks simulated +sim_seconds 0.003750 # Number of seconds simulated +sim_ticks 3750455 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 53802 # number of write accesses completed +system.cpu0.num_writes 54108 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99730 # number of read accesses completed -system.cpu1.num_writes 53651 # number of write accesses completed +system.cpu1.num_reads 99918 # number of read accesses completed +system.cpu1.num_writes 53757 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99194 # number of read accesses completed -system.cpu2.num_writes 53071 # number of write accesses completed +system.cpu2.num_reads 99521 # number of read accesses completed +system.cpu2.num_writes 53948 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98275 # number of read accesses completed -system.cpu3.num_writes 53108 # number of write accesses completed +system.cpu3.num_reads 98786 # number of read accesses completed +system.cpu3.num_writes 53362 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98291 # number of read accesses completed -system.cpu4.num_writes 52851 # number of write accesses completed +system.cpu4.num_reads 98631 # number of read accesses completed +system.cpu4.num_writes 52746 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97729 # number of read accesses completed -system.cpu5.num_writes 52263 # number of write accesses completed +system.cpu5.num_reads 98242 # number of read accesses completed +system.cpu5.num_writes 52924 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 97202 # number of read accesses completed -system.cpu6.num_writes 51897 # number of write accesses completed +system.cpu6.num_reads 97407 # number of read accesses completed +system.cpu6.num_writes 52658 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 96111 # number of read accesses completed -system.cpu7.num_writes 51731 # number of write accesses completed +system.cpu7.num_reads 96638 # number of read accesses completed +system.cpu7.num_writes 51757 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index 72fa2cdc0..2086e11ae 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -5,13 +5,14 @@ dummy=0 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -129,6 +137,47 @@ trace_addr=0 functional=system.funcmem.port[7] test=system.ruby.cpu_ruby_ports7.port[0] +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + [system.funcmem] type=PhysicalMemory file= @@ -139,168 +188,11 @@ range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort - -[system.ruby] -type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports0] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.cpu_ruby_ports1] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.cpu_ruby_ports2] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.cpu_ruby_ports3] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.cpu_ruby_ports4] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.cpu_ruby_ports5] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.cpu_ruby_ports6] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.cpu_ruby_ports7] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 -num_int_nodes=11 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] +[system.l1_cntrl0] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -310,34 +202,27 @@ sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] +[system.l1_cntrl1] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -347,34 +232,27 @@ sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] +[system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] +[system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.l1_cntrl2] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -384,34 +262,27 @@ sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] +[system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] +[system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node -int_node=3 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links3.ext_node] +[system.l1_cntrl3] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -421,34 +292,27 @@ sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] +[system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] +[system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node -int_node=4 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links4.ext_node] +[system.l1_cntrl4] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -458,34 +322,27 @@ sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] +[system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] +[system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node -int_node=5 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links5.ext_node] +[system.l1_cntrl5] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -495,34 +352,27 @@ sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] +[system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] +[system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node -int_node=6 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links6.ext_node] +[system.l1_cntrl6] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -532,34 +382,27 @@ sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] +[system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] +[system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node -int_node=7 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links7.ext_node] +[system.l1_cntrl7] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 @@ -569,33 +412,26 @@ sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] +[system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] +[system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links8] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node -int_node=8 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links8.ext_node] +[system.l2_cntrl0] type=L2Cache_Controller children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory buffer_size=0 number_of_TBEs=256 recycle_latency=10 @@ -604,62 +440,242 @@ response_latency=2 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] +[system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 latency=15 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links9] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.l1_cntrl1.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.l1_cntrl2.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.l1_cntrl3.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.l1_cntrl4.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl4.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.l1_cntrl5.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl5.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.l1_cntrl6.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl6.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.l1_cntrl7.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl7.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +num_int_nodes=11 +print_config=false + +[system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node -int_node=9 +ext_node=system.l1_cntrl0 +int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl1 +int_node=1 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl2 +int_node=2 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 +[system.ruby.network.topology.ext_links3] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl3 +int_node=3 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl4 +int_node=4 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links5] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl5 +int_node=5 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links6] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl6 +int_node=6 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links7] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl7 +int_node=7 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links8] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=8 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links9] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=9 +latency=1 +weight=1 [system.ruby.network.topology.int_links0] type=IntLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index afc84d0aa..f165c60b3 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/01/2010 14:40:10 +Real time: Aug/20/2010 12:11:08 Profiler Stats -------------- -Elapsed_time_in_seconds: 25 -Elapsed_time_in_minutes: 0.416667 -Elapsed_time_in_hours: 0.00694444 -Elapsed_time_in_days: 0.000289352 +Elapsed_time_in_seconds: 30 +Elapsed_time_in_minutes: 0.5 +Elapsed_time_in_hours: 0.00833333 +Elapsed_time_in_days: 0.000347222 -Virtual_time_in_seconds: 24.36 -Virtual_time_in_minutes: 0.406 -Virtual_time_in_hours: 0.00676667 -Virtual_time_in_days: 0.000281944 +Virtual_time_in_seconds: 29.75 +Virtual_time_in_minutes: 0.495833 +Virtual_time_in_hours: 0.00826389 +Virtual_time_in_days: 0.000344329 -Ruby_current_time: 3358188 +Ruby_current_time: 3377485 Ruby_start_time: 0 -Ruby_cycles: 3358188 +Ruby_cycles: 3377485 -mbytes_resident: 32.3125 -mbytes_total: 325.066 -resident_ratio: 0.0994148 +mbytes_resident: 32.793 +mbytes_total: 333.84 +resident_ratio: 0.0982413 -ruby_cycles_executed: [ 3358189 3358189 3358189 3358189 3358189 3358189 3358189 3358189 ] +ruby_cycles_executed: [ 3377486 3377486 3377486 3377486 3377486 3377486 3377486 3377486 ] Busy Controller Counts: L2Cache-0:0 @@ -67,13 +67,26 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1215398 average: 1.9442 | standard deviation: 0.229541 | 0 67822 1147576 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1222069 average: 1.94291 | standard deviation: 0.23202 | 0 69771 1152298 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 3818 count: 1215384 average: 42.2024 | standard deviation: 176.766 | 1112077 89 18203 264 3632 204 20059 101 4609 316 9477 164 6271 231 4384 203 5321 133 2876 482 3614 199 1795 1183 2274 311 1255 1088 1275 707 917 894 528 1015 642 655 443 760 442 606 299 540 235 520 242 363 176 392 189 294 130 248 95 236 136 162 90 172 87 120 50 105 55 101 50 85 34 40 36 47 31 38 30 27 22 22 15 19 16 16 3 8 11 13 12 10 9 5 3 4 7 4 10 2 4 1 3 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 3747 count: 790225 average: 41.6816 | standard deviation: 175.575 | 723783 1 11782 190 2290 112 13127 39 3042 155 6044 74 4067 176 2753 101 3392 79 2018 104 2293 131 1147 763 1424 189 833 676 1076 268 593 583 350 633 400 406 275 496 347 325 213 346 154 347 144 245 122 253 140 180 89 157 59 165 82 106 64 99 60 68 27 65 34 66 28 49 22 25 27 26 20 22 20 18 12 16 9 12 13 9 1 5 9 8 6 9 6 1 1 3 4 3 6 2 2 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 32 max: 3818 count: 425159 average: 43.1703 | standard deviation: 178.955 | 388294 88 6421 74 1342 92 6932 62 1567 161 3433 90 2204 55 1631 102 1929 54 858 378 1321 68 648 420 850 122 422 412 199 439 324 311 178 382 242 249 168 264 95 281 86 194 81 173 98 118 54 139 49 114 41 91 36 71 54 56 26 73 27 52 23 40 21 35 22 36 12 15 9 21 11 16 10 9 10 6 6 7 3 7 2 3 2 5 6 1 3 4 2 1 3 1 4 0 2 0 2 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,160 +116,169 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 24 +user_time: 29 system_time: 0 -page_reclaims: 8496 +page_reclaims: 9510 page_faults: 0 swaps: 0 block_inputs: 16 -block_outputs: 72 +block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 311844 2494752 +total_msg_count_Response_Data: 12 864 +total_msg_count_ResponseLocal_Data: 311478 22426416 +total_msg_count_Response_Control: 113679 909432 +total_msg_count_Forwarded_Control: 311796 2494368 +total_msg_count_Invalidate_Control: 1988 15904 +total_msg_count_Unblock_Control: 311802 2494416 +total_msgs: 1362599 total_bytes: 30836152 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.129534 - links_utilized_percent_switch_0_link_0: 0.0494002 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.209668 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.130402 + links_utilized_percent_switch_0_link_0: 0.0495676 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.211237 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12797 921384 [ 0 0 12797 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 4642 37136 [ 0 0 4642 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 12801 102408 [ 12801 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 12811 102488 [ 12811 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 12809 102472 [ 0 0 12809 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 12920 103360 [ 12920 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12975 934200 [ 0 0 12975 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 77 616 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 12918 103344 [ 0 0 12918 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.132053 - links_utilized_percent_switch_1_link_0: 0.0504037 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.213702 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13049 939528 [ 0 0 13049 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 4824 38592 [ 0 0 4824 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 13045 104360 [ 13045 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 13062 104496 [ 13062 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13034 938448 [ 0 0 13034 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 13060 104480 [ 0 0 13060 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.130527 + links_utilized_percent_switch_1_link_0: 0.0497582 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.211296 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 12985 103880 [ 12985 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 12962 933264 [ 0 0 12962 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 12983 103864 [ 0 0 12983 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.132003 - links_utilized_percent_switch_2_link_0: 0.0503009 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.213705 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 4741 37928 [ 0 0 4741 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 13054 104432 [ 13054 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 13042 104336 [ 13042 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 13039 938808 [ 0 0 13039 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 13041 104328 [ 0 0 13041 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.130904 + links_utilized_percent_switch_2_link_0: 0.0499306 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.211878 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 13024 104192 [ 13024 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12997 935784 [ 0 0 12997 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 13023 104184 [ 0 0 13023 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.131776 - links_utilized_percent_switch_3_link_0: 0.0501826 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.21337 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 4748 37984 [ 0 0 4748 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 13039 104312 [ 13039 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Invalidate_Control: 94 752 [ 94 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 13013 104104 [ 13013 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13021 937512 [ 0 0 13021 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 94 752 [ 0 0 94 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 13011 104088 [ 0 0 13011 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.131152 + links_utilized_percent_switch_3_link_0: 0.0500739 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.21223 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 13063 104504 [ 13063 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 111 888 [ 0 0 111 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 13061 104488 [ 0 0 13061 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.130943 - links_utilized_percent_switch_4_link_0: 0.0499518 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.211934 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12944 931968 [ 0 0 12944 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 4660 37280 [ 0 0 4660 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 12939 103512 [ 12939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 12958 103664 [ 12958 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12925 930600 [ 0 0 12925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 12957 103656 [ 0 0 12957 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.130608 + links_utilized_percent_switch_4_link_0: 0.0498674 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.21135 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 12995 103960 [ 12995 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 12993 103944 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.128854 - links_utilized_percent_switch_5_link_0: 0.0491307 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.208577 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12722 915984 [ 0 0 12722 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 4664 37312 [ 0 0 4664 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 12737 101896 [ 12737 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Invalidate_Control: 93 744 [ 93 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 12736 101888 [ 12736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12725 916200 [ 0 0 12725 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 93 744 [ 0 0 93 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 12734 101872 [ 0 0 12734 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.129687 + links_utilized_percent_switch_5_link_0: 0.0495006 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.209874 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 12908 103264 [ 12908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12873 926856 [ 0 0 12873 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 12906 103248 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.130398 - links_utilized_percent_switch_6_link_0: 0.0498286 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.210966 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12912 929664 [ 0 0 12912 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4683 37464 [ 0 0 4683 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 12871 102968 [ 12871 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Invalidate_Control: 105 840 [ 105 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 12925 103400 [ 12925 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12860 925920 [ 0 0 12860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 105 840 [ 0 0 105 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 12923 103384 [ 0 0 12923 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.130865 + links_utilized_percent_switch_6_link_0: 0.0499036 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.211826 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12998 935856 [ 0 0 12998 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 13007 104056 [ 0 0 13007 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.129861 - links_utilized_percent_switch_7_link_0: 0.0494162 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.210305 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 4708 37664 [ 0 0 4708 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 12853 102824 [ 12853 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Invalidate_Control: 88 704 [ 88 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 12806 102448 [ 12806 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12839 924408 [ 0 0 12839 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 88 704 [ 0 0 88 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 12804 102432 [ 0 0 12804 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.131276 + links_utilized_percent_switch_7_link_0: 0.0500158 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.212537 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 13043 104344 [ 13043 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 13043 939096 [ 0 0 13043 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 97 776 [ 0 0 97 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 13041 104328 [ 0 0 13041 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 links_utilized_percent_switch_8: 0.143198 - links_utilized_percent_switch_8_link_0: 0.0769425 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.209454 bw: 160000 base_latency: 1 + links_utilized_percent_switch_8_link_0: 0.0769419 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.209455 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 103353 826824 [ 103353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 103339 826712 [ 0 0 103339 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 36896 295168 [ 0 0 36896 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 103339 826712 [ 103339 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Invalidate_Control: 420 3360 [ 420 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 37110 296880 [ 0 0 37110 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Forwarded_Control: 103932 831456 [ 103932 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Invalidate_Control: 422 3376 [ 422 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.41445e-05 - links_utilized_percent_switch_9_link_0: 1.4889e-06 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.68002e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.40637e-05 + links_utilized_percent_switch_9_link_0: 1.48039e-06 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.6647e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 @@ -264,2281 +286,1130 @@ links_utilized_percent_switch_9: 1.41445e-05 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.190223 - links_utilized_percent_switch_10_link_0: 0.197601 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.201615 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.201204 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.20073 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.199807 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.196523 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.199314 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.197665 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.30777 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 5.95559e-06 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.190224 + links_utilized_percent_switch_10_link_0: 0.19827 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.199033 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.199723 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.200295 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.199469 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.198002 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.199615 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.200063 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.307767 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 5.92157e-06 bw: 160000 base_latency: 1 outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12797 921384 [ 0 0 12797 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 4642 37136 [ 0 0 4642 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Forwarded_Control: 12801 102408 [ 12801 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13049 939528 [ 0 0 13049 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 4824 38592 [ 0 0 4824 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Forwarded_Control: 13045 104360 [ 13045 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 4741 37928 [ 0 0 4741 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Forwarded_Control: 13054 104432 [ 13054 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 4748 37984 [ 0 0 4748 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Forwarded_Control: 13039 104312 [ 13039 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Invalidate_Control: 94 752 [ 94 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12944 931968 [ 0 0 12944 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 4660 37280 [ 0 0 4660 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Forwarded_Control: 12939 103512 [ 12939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12722 915984 [ 0 0 12722 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 4664 37312 [ 0 0 4664 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Forwarded_Control: 12737 101896 [ 12737 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Invalidate_Control: 93 744 [ 93 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12912 929664 [ 0 0 12912 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4683 37464 [ 0 0 4683 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Forwarded_Control: 12871 102968 [ 12871 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Invalidate_Control: 105 840 [ 105 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 4708 37664 [ 0 0 4708 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Forwarded_Control: 12853 102824 [ 12853 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Invalidate_Control: 88 704 [ 88 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 103353 826824 [ 103353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Unblock_Control: 103339 826712 [ 0 0 103339 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 98038 -Ifetch 0 -Store 52677 -L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22106 -Fwd_GETS 40419 -Fwd_DMA 0 -Inv 91 -Ack 4642 -Data 101 -Exclusive_Data 12697 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4542 -Use_Timeout 12708 +Load [99188 98347 99157 99646 99118 99153 100001 99634 ] 794244 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [53590 53268 53749 53528 53019 53486 53183 54001 ] 427824 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Own_GETX [12 14 11 13 11 21 9 13 ] 104 +Fwd_GETX [22780 22543 22706 22494 22314 22746 22504 22308 ] 180395 +Fwd_GETS [40560 40358 40695 41058 40851 40579 40962 41289 ] 326352 +Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +Inv [102 98 91 97 77 104 103 111 ] 783 +Ack [4834 4737 4774 4737 4705 4701 4676 4729 ] 37893 +Data [117 113 98 108 88 113 112 122 ] 871 +Exclusive_Data [12864 12779 12898 12920 12819 12849 12902 12926 ] 102957 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110 +Use_Timeout [12876 12793 12908 12933 12830 12870 12910 12939 ] 103059 - Transitions - -I Load 8269 -I Ifetch 0 <-- -I Store 4406 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 152 -S Ifetch 0 <-- -S Store 87 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 14 - -O Load 89 -O Ifetch 0 <-- -O Store 49 -O L1_Replacement 0 <-- -O Fwd_GETX 3 -O Fwd_GETS 3 -O Fwd_DMA 0 <-- - -M Load 108 -M Ifetch 0 <-- -M Store 59 -M L1_Replacement 0 <-- -M Fwd_GETX 24 -M Fwd_GETS 52 -M Fwd_DMA 0 <-- - -M_W Load 14673 -M_W Ifetch 0 <-- -M_W Store 8031 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1325 -M_W Fwd_GETS 2498 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 135 - -MM Load 11534 -MM Ifetch 0 <-- -MM Store 6099 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4465 -MM Fwd_GETS 8167 -MM Fwd_DMA 0 <-- - -MM_W Load 63213 -MM_W Ifetch 0 <-- -MM_W Store 33946 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16251 -MM_W Fwd_GETS 29661 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12573 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4548 -IM Data 0 <-- -IM Exclusive_Data 4521 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 77 -SM Ack 22 -SM Data 0 <-- -SM Exclusive_Data 10 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 38 -OM Fwd_GETS 38 -OM Fwd_DMA 0 <-- -OM Ack 72 -OM All_acks 4542 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 101 -IS Exclusive_Data 8166 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 1 --- - - Event Counts - -Load 99904 -Ifetch 0 -Store 53672 -L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22767 -Fwd_GETS 40844 -Fwd_DMA 0 -Inv 102 -Ack 4824 -Data 113 -Exclusive_Data 12936 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4720 -Use_Timeout 12947 +I Load [8262 8273 8337 8401 8312 8394 8441 8416 ] 66836 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [4573 4492 4542 4491 4468 4437 4447 4499 ] 35949 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I Inv [0 0 0 0 0 0 0 0 ] 0 + +S Load [136 189 149 161 147 187 176 221 ] 1366 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [109 97 80 91 76 95 93 104 ] 745 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +S Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +S Inv [8 16 18 17 12 18 19 18 ] 126 + +O Load [93 105 85 75 124 102 80 82 ] 746 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [51 46 49 60 64 59 43 44 ] 416 +O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +O Fwd_GETX [2 4 2 1 1 1 3 1 ] 15 +O Fwd_GETS [3 5 4 2 6 8 4 3 ] 35 +O Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 + +M Load [116 128 118 133 159 134 127 113 ] 1028 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [57 72 73 65 45 58 84 64 ] 518 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Fwd_GETX [28 33 30 32 33 36 34 34 ] 260 +M Fwd_GETS [53 50 51 61 65 60 46 45 ] 431 +M Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 + +M_W Load [14625 14739 14872 15279 15066 15137 15392 14864 ] 119974 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [8005 8003 8084 8133 8079 8125 8164 8149 ] 64742 +M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 +M_W Fwd_GETX [1364 1363 1417 1394 1416 1389 1476 1364 ] 11183 +M_W Fwd_GETS [2392 2478 2488 2651 2563 2494 2590 2473 ] 20129 +M_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +M_W Inv [0 0 0 0 0 0 0 0 ] 0 +M_W Use_Timeout [138 155 154 158 143 154 164 143 ] 1209 + +MM Load [11570 11359 11558 11408 11540 11529 11698 11455 ] 92117 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [6129 6213 6160 6217 6122 6256 6194 6383 ] 49674 +MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM Fwd_GETX [4600 4549 4589 4547 4500 4586 4546 4502 ] 36419 +MM Fwd_GETS [8195 8161 8238 8293 8232 8188 8284 8358 ] 65949 +MM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 + +MM_W Load [64386 63554 64038 64189 63770 63670 64087 64483 ] 512177 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [34666 34345 34761 34471 34165 34456 34158 34758 ] 275780 +MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 +MM_W Fwd_GETX [16747 16562 16630 16473 16311 16696 16411 16376 ] 132206 +MM_W Fwd_GETS [29873 29625 29868 29991 29900 29784 29992 30370 ] 239403 +MM_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +MM_W Inv [0 0 0 0 0 0 0 0 ] 0 +MM_W Use_Timeout [12738 12638 12754 12775 12687 12716 12746 12796 ] 101850 + +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Inv [0 0 0 0 0 0 0 0 ] 0 +IM Ack [4717 4630 4681 4635 4610 4584 4595 4636 ] 37088 +IM Data [0 0 0 0 0 0 0 0 ] 0 +IM Exclusive_Data [4706 4606 4653 4618 4586 4561 4565 4623 ] 36918 + +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +SM Inv [94 82 73 80 65 86 84 93 ] 657 +SM Ack [33 31 14 16 20 21 15 20 ] 170 +SM Data [0 0 0 0 0 0 0 0 ] 0 +SM Exclusive_Data [15 15 7 11 11 9 9 11 ] 88 + +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM Own_GETX [12 14 11 13 11 21 9 13 ] 104 +OM Fwd_GETX [39 32 38 47 53 38 34 31 ] 312 +OM Fwd_GETS [44 39 46 60 85 45 46 40 ] 405 +OM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +OM Ack [84 76 79 86 75 96 66 73 ] 635 +OM All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110 + +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Inv [0 0 0 0 0 0 0 0 ] 0 +IS Data [117 113 98 108 88 113 112 122 ] 871 +IS Exclusive_Data [8143 8158 8238 8291 8222 8279 8328 8292 ] 65951 + +SI Load [0 0 0 0 0 0 0 0 ] 0 +SI Ifetch [0 0 0 0 0 0 0 0 ] 0 +SI Store [0 0 0 0 0 0 0 0 ] 0 +SI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +SI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +SI Inv [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 + +OI Load [0 0 0 0 0 0 0 0 ] 0 +OI Ifetch [0 0 0 0 0 0 0 0 ] 0 +OI Store [0 0 0 0 0 0 0 0 ] 0 +OI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 + +MI Load [0 0 0 0 0 0 0 0 ] 0 +MI Ifetch [0 0 0 0 0 0 0 0 ] 0 +MI Store [0 0 0 0 0 0 0 0 ] 0 +MI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 + +II Load [0 0 0 0 0 0 0 0 ] 0 +II Ifetch [0 0 0 0 0 0 0 0 ] 0 +II Store [0 0 0 0 0 0 0 0 ] 0 +II L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +II Inv [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 + +Cache Stats: system.l1_cntrl1.L1IcacheMemory + system.l1_cntrl1.L1IcacheMemory_total_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl1.L1DcacheMemory + system.l1_cntrl1.L1DcacheMemory_total_misses: 0 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1IcacheMemory + system.l1_cntrl2.L1IcacheMemory_total_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1DcacheMemory + system.l1_cntrl2.L1DcacheMemory_total_misses: 0 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1IcacheMemory + system.l1_cntrl3.L1IcacheMemory_total_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1DcacheMemory + system.l1_cntrl3.L1DcacheMemory_total_misses: 0 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.L1IcacheMemory + system.l1_cntrl4.L1IcacheMemory_total_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.L1DcacheMemory + system.l1_cntrl4.L1DcacheMemory_total_misses: 0 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1IcacheMemory + system.l1_cntrl5.L1IcacheMemory_total_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1DcacheMemory + system.l1_cntrl5.L1DcacheMemory_total_misses: 0 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.L1IcacheMemory + system.l1_cntrl6.L1IcacheMemory_total_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.L1DcacheMemory + system.l1_cntrl6.L1DcacheMemory_total_misses: 0 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 8341 -I Ifetch 0 <-- -I Store 4582 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 188 -S Ifetch 0 <-- -S Store 97 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 16 - -O Load 103 -O Ifetch 0 <-- -O Store 42 -O L1_Replacement 0 <-- -O Fwd_GETX 3 -O Fwd_GETS 7 -O Fwd_DMA 0 <-- - -M Load 119 -M Ifetch 0 <-- -M Store 47 -M L1_Replacement 0 <-- -M Fwd_GETX 34 -M Fwd_GETS 45 -M Fwd_DMA 0 <-- - -M_W Load 15164 -M_W Ifetch 0 <-- -M_W Store 8101 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1415 -M_W Fwd_GETS 2544 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 126 - -MM Load 11562 -MM Ifetch 0 <-- -MM Store 6213 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4597 -MM Fwd_GETS 8271 -MM Fwd_DMA 0 <-- - -MM_W Load 64427 -MM_W Ifetch 0 <-- -MM_W Store 34590 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16687 -MM_W Fwd_GETS 29931 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12821 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4727 -IM Data 0 <-- -IM Exclusive_Data 4698 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 86 -SM Ack 23 -SM Data 0 <-- -SM Exclusive_Data 11 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 31 -OM Fwd_GETS 46 -OM Fwd_DMA 0 <-- -OM Ack 74 -OM All_acks 4720 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 113 -IS Exclusive_Data 8227 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 2 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 53360 -L1_Replacement 0 -Own_GETX 14 -Fwd_GETX 22353 -Fwd_GETS 41223 -Fwd_DMA 0 -Inv 98 -Ack 4741 -Data 107 -Exclusive_Data 12920 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4660 -Use_Timeout 12933 - - Transitions - -I Load 8382 -I Ifetch 0 <-- -I Store 4515 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 157 -S Ifetch 0 <-- -S Store 92 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 15 - -O Load 104 -O Ifetch 0 <-- -O Store 53 -O L1_Replacement 0 <-- -O Fwd_GETX 3 -O Fwd_GETS 6 -O Fwd_DMA 0 <-- - -M Load 134 -M Ifetch 0 <-- -M Store 74 -M L1_Replacement 0 <-- -M Fwd_GETX 30 -M Fwd_GETS 56 -M Fwd_DMA 0 <-- - -M_W Load 15047 -M_W Ifetch 0 <-- -M_W Store 8113 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1357 -M_W Fwd_GETS 2574 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 160 - -MM Load 11573 -MM Ifetch 0 <-- -MM Store 6155 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4522 -MM Fwd_GETS 8325 -MM Fwd_DMA 0 <-- - -MM_W Load 64604 -MM_W Ifetch 0 <-- -MM_W Store 34358 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16402 -MM_W Fwd_GETS 30204 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12773 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4654 -IM Data 0 <-- -IM Exclusive_Data 4637 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 83 -SM Ack 18 -SM Data 0 <-- -SM Exclusive_Data 9 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 14 -OM Fwd_GETX 39 -OM Fwd_GETS 58 -OM Fwd_DMA 0 <-- -OM Ack 69 -OM All_acks 4660 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 107 -IS Exclusive_Data 8274 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 3 --- - - Event Counts - -Load 99547 -Ifetch 0 -Store 53578 -L1_Replacement 0 -Own_GETX 18 -Fwd_GETX 22394 -Fwd_GETS 41045 -Fwd_DMA 0 -Inv 94 -Ack 4748 -Data 109 -Exclusive_Data 12884 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4636 -Use_Timeout 12902 +Cache Stats: system.l1_cntrl7.L1IcacheMemory + system.l1_cntrl7.L1IcacheMemory_total_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 8377 -I Ifetch 0 <-- -I Store 4474 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 160 -S Ifetch 0 <-- -S Store 96 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 13 - -O Load 137 -O Ifetch 0 <-- -O Store 66 -O L1_Replacement 0 <-- -O Fwd_GETX 3 -O Fwd_GETS 5 -O Fwd_DMA 0 <-- - -M Load 150 -M Ifetch 0 <-- -M Store 62 -M L1_Replacement 0 <-- -M Fwd_GETX 36 -M Fwd_GETS 69 -M Fwd_DMA 0 <-- - -M_W Load 15193 -M_W Ifetch 0 <-- -M_W Store 8099 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1351 -M_W Fwd_GETS 2628 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 167 - -MM Load 11388 -MM Ifetch 0 <-- -MM Store 6298 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4511 -MM Fwd_GETS 8286 -MM Fwd_DMA 0 <-- - -MM_W Load 64142 -MM_W Ifetch 0 <-- -MM_W Store 34483 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16445 -MM_W Fwd_GETS 29994 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12735 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4626 -IM Data 0 <-- -IM Exclusive_Data 4603 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 81 -SM Ack 31 -SM Data 0 <-- -SM Exclusive_Data 15 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 18 -OM Fwd_GETX 48 -OM Fwd_GETS 63 -OM Fwd_DMA 0 <-- -OM Ack 91 -OM All_acks 4636 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 109 -IS Exclusive_Data 8266 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 4 --- - - Event Counts - -Load 99119 -Ifetch 0 -Store 53227 -L1_Replacement 0 -Own_GETX 13 -Fwd_GETX 22967 -Fwd_GETS 40211 -Fwd_DMA 0 -Inv 103 -Ack 4660 -Data 111 -Exclusive_Data 12833 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4559 -Use_Timeout 12845 - - Transitions - -I Load 8399 -I Ifetch 0 <-- -I Store 4426 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 162 -S Ifetch 0 <-- -S Store 91 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 20 - -O Load 44 -O Ifetch 0 <-- -O Store 42 -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 2 -O Fwd_DMA 0 <-- - -M Load 112 -M Ifetch 0 <-- -M Store 68 -M L1_Replacement 0 <-- -M Fwd_GETX 27 -M Fwd_GETS 42 -M Fwd_DMA 0 <-- - -M_W Load 14685 -M_W Ifetch 0 <-- -M_W Store 8150 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1379 -M_W Fwd_GETS 2445 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 137 - -MM Load 11415 -MM Ifetch 0 <-- -MM Store 6224 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4639 -MM Fwd_GETS 8137 -MM Fwd_DMA 0 <-- - -MM_W Load 64302 -MM_W Ifetch 0 <-- -MM_W Store 34226 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16893 -MM_W Fwd_GETS 29536 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12708 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4561 -IM Data 0 <-- -IM Exclusive_Data 4538 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 83 -SM Ack 13 -SM Data 0 <-- -SM Exclusive_Data 8 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 13 -OM Fwd_GETX 29 -OM Fwd_GETS 49 -OM Fwd_DMA 0 <-- -OM Ack 86 -OM All_acks 4559 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 111 -IS Exclusive_Data 8287 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 96993 -Ifetch 0 -Store 52753 -L1_Replacement 0 -Own_GETX 12 -Fwd_GETX 22235 -Fwd_GETS 39902 -Fwd_DMA 0 -Inv 93 -Ack 4664 -Data 99 -Exclusive_Data 12623 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4571 -Use_Timeout 12635 +Cache Stats: system.l1_cntrl7.L1DcacheMemory + system.l1_cntrl7.L1DcacheMemory_total_misses: 0 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 8165 -I Ifetch 0 <-- -I Store 4435 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 169 -S Ifetch 0 <-- -S Store 85 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 14 - -O Load 80 -O Ifetch 0 <-- -O Store 51 -O L1_Replacement 0 <-- -O Fwd_GETX 1 -O Fwd_GETS 2 -O Fwd_DMA 0 <-- - -M Load 113 -M Ifetch 0 <-- -M Store 61 -M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 52 -M Fwd_DMA 0 <-- - -M_W Load 14722 -M_W Ifetch 0 <-- -M_W Store 7919 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1407 -M_W Fwd_GETS 2459 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 145 - -MM Load 11363 -MM Ifetch 0 <-- -MM Store 6174 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4487 -MM Fwd_GETS 8064 -MM Fwd_DMA 0 <-- - -MM_W Load 62381 -MM_W Ifetch 0 <-- -MM_W Store 34028 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16269 -MM_W Fwd_GETS 29277 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12490 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4586 -IM Data 0 <-- -IM Exclusive_Data 4553 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 79 -SM Ack 14 -SM Data 0 <-- -SM Exclusive_Data 6 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 12 -OM Fwd_GETX 39 -OM Fwd_GETS 48 -OM Fwd_DMA 0 <-- -OM Ack 64 -OM All_acks 4571 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 99 -IS Exclusive_Data 8064 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 98714 -Ifetch 0 -Store 52959 -L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22265 -Fwd_GETS 40575 -Fwd_DMA 0 -Inv 105 -Ack 4683 -Data 120 -Exclusive_Data 12792 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4582 -Use_Timeout 12803 - - Transitions - -I Load 8342 -I Ifetch 0 <-- -I Store 4436 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 244 -S Ifetch 0 <-- -S Store 105 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 15 - -O Load 55 -O Ifetch 0 <-- -O Store 42 -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 1 -O Fwd_DMA 0 <-- - -M Load 104 -M Ifetch 0 <-- -M Store 69 -M L1_Replacement 0 <-- -M Fwd_GETX 24 -M Fwd_GETS 42 -M Fwd_DMA 0 <-- - -M_W Load 14705 -M_W Ifetch 0 <-- -M_W Store 8086 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1322 -M_W Fwd_GETS 2502 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 135 - -MM Load 11345 -MM Ifetch 0 <-- -MM Store 6118 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4507 -MM Fwd_GETS 8230 -MM Fwd_DMA 0 <-- - -MM_W Load 63919 -MM_W Ifetch 0 <-- -MM_W Store 34103 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16381 -MM_W Fwd_GETS 29775 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12668 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4577 -IM Data 0 <-- -IM Exclusive_Data 4556 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 90 -SM Ack 34 -SM Data 0 <-- -SM Exclusive_Data 15 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 31 -OM Fwd_GETS 25 -OM Fwd_DMA 0 <-- -OM Ack 72 -OM All_acks 4582 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 120 -IS Exclusive_Data 8221 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 97921 -Ifetch 0 -Store 52935 -L1_Replacement 0 -Own_GETX 14 -Fwd_GETX 22349 -Fwd_GETS 40209 -Fwd_DMA 0 -Inv 88 -Ack 4708 -Data 96 -Exclusive_Data 12694 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4627 -Use_Timeout 12708 +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 8179 -I Ifetch 0 <-- -I Store 4477 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 123 -S Ifetch 0 <-- -S Store 88 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 8 - -O Load 138 -O Ifetch 0 <-- -O Store 62 -O L1_Replacement 0 <-- -O Fwd_GETX 4 -O Fwd_GETS 2 -O Fwd_DMA 0 <-- - -M Load 126 -M Ifetch 0 <-- -M Store 68 -M L1_Replacement 0 <-- -M Fwd_GETX 25 -M Fwd_GETS 66 -M Fwd_DMA 0 <-- - -M_W Load 14685 -M_W Ifetch 0 <-- -M_W Store 7922 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1316 -M_W Fwd_GETS 2538 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 159 - -MM Load 11522 -MM Ifetch 0 <-- -MM Store 6028 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4512 -MM Fwd_GETS 8105 -MM Fwd_DMA 0 <-- - -MM_W Load 63148 -MM_W Ifetch 0 <-- -MM_W Store 34290 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16444 -MM_W Fwd_GETS 29421 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12549 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4621 -IM Data 0 <-- -IM Exclusive_Data 4605 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 80 -SM Ack 16 -SM Data 0 <-- -SM Exclusive_Data 8 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 14 -OM Fwd_GETX 48 -OM Fwd_GETS 77 -OM Fwd_DMA 0 <-- -OM Ack 71 -OM All_acks 4627 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 96 -IS Exclusive_Data 8081 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- + + --- L2Cache --- - Event Counts - -L1_GETS 2706421 -L1_GETX 1509888 -L1_PUTO 0 -L1_PUTX 0 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 1 -Data 1 -Data_Exclusive 1 -L1_WBCLEANDATA 0 -L1_WBDIRTYDATA 0 -Writeback_Ack 0 -Writeback_Nack 0 -Unblock 856 -Exclusive_Unblock 102483 -L2_Replacement 0 +L1_GETS [2715881 ] 2715881 +L1_GETX [1524697 ] 1524697 +L1_PUTO [0 ] 0 +L1_PUTX [0 ] 0 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [0 ] 0 +Data [0 ] 0 +Data_Exclusive [2 ] 2 +L1_WBCLEANDATA [0 ] 0 +L1_WBDIRTYDATA [0 ] 0 +Writeback_Ack [0 ] 0 +Writeback_Nack [0 ] 0 +Unblock [871 ] 871 +Exclusive_Unblock [103061 ] 103061 +L2_Replacement [0 ] 0 - Transitions - -NP L1_GETS 1 -NP L1_GETX 1 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 66011 -ILX L1_GETX 36472 -ILX L1_PUTO 0 <-- -ILX L1_PUTX 0 <-- -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 432 -ILOSX L1_GETX 424 -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 0 <-- - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 0 <-- -ILXW L1_WBDIRTYDATA 0 <-- -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 2633310 -IFLOXX L1_GETX 1464389 -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 424 -IFLOXX Exclusive_Unblock 102057 -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 3100 -IFLOSX L1_GETX 4155 -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 432 -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 3334 -IFLXO L1_GETX 4226 -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 424 -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 81 -IGS L1_GETX 107 -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 1 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 1 -IGS L2_Replacement 0 <-- - -IGM L1_GETS 144 -IGM L1_GETX 108 -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 1 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 8 -IGMO L1_GETX 6 -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 1 -IGMO Exclusive_Unblock 1 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 0 <-- -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 0 <-- -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 0 <-- -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +NP L1_GETS [2 ] 2 +NP L1_GETX [0 ] 0 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [66382 ] 66382 +ILX L1_GETX [36679 ] 36679 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [0 ] 0 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [440 ] 440 +ILOSX L1_GETX [431 ] 431 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [0 ] 0 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [0 ] 0 +ILXW L1_WBDIRTYDATA [0 ] 0 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [2641993 ] 2641993 +IFLOXX L1_GETX [1479034 ] 1479034 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [431 ] 431 +IFLOXX Exclusive_Unblock [102628 ] 102628 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [3247 ] 3247 +IFLOSX L1_GETX [4201 ] 4201 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [440 ] 440 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [3428 ] 3428 +IFLXO L1_GETX [4287 ] 4287 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [431 ] 431 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [389 ] 389 +IGS L1_GETX [65 ] 65 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [2 ] 2 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [2 ] 2 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [0 ] 0 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [0 ] 0 +IGMO Exclusive_Unblock [0 ] 0 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [0 ] 0 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [0 ] 0 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -2558,201 +1429,200 @@ Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1 -GETS 1 -PUTX 0 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 2 -Clean_Writeback 0 -Dirty_Writeback 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [0 ] 0 +GETS [2 ] 2 +PUTX [0 ] 0 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [2 ] 2 +Clean_Writeback [0 ] 0 +Dirty_Writeback [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 1 -I GETS 1 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -M GETX 0 <-- -M GETS 0 <-- -M PUTX 0 <-- -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 1 -IS Memory_Data 1 -IS Memory_Ack 0 <-- -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- - -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- - -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- - -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- - -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 1 -MM Memory_Data 1 -MM Memory_Ack 0 <-- -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- - - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 0 <-- -MI Dirty_Writeback 0 <-- -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- - -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- - -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- - -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- - -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- - -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +I GETX [0 ] 0 +I GETS [2 ] 2 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [0 ] 0 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [2 ] 2 +IS Memory_Data [2 ] 2 +IS Memory_Ack [0 ] 0 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [0 ] 0 +MM Memory_Data [0 ] 0 +MM Memory_Ack [0 ] 0 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [0 ] 0 +MI Dirty_Writeback [0 ] 0 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data
\ No newline at end of file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr index 2f54bd8e2..ac46137f1 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu6: completed 10000 read accesses @325901 -system.cpu4: completed 10000 read accesses @333477 -system.cpu2: completed 10000 read accesses @337264 -system.cpu7: completed 10000 read accesses @338212 -system.cpu0: completed 10000 read accesses @341315 -system.cpu5: completed 10000 read accesses @343794 -system.cpu1: completed 10000 read accesses @347258 -system.cpu3: completed 10000 read accesses @349679 -system.cpu6: completed 20000 read accesses @662679 -system.cpu7: completed 20000 read accesses @663435 -system.cpu4: completed 20000 read accesses @670972 -system.cpu1: completed 20000 read accesses @674886 -system.cpu2: completed 20000 read accesses @675526 -system.cpu0: completed 20000 read accesses @687421 -system.cpu5: completed 20000 read accesses @695852 -system.cpu3: completed 20000 read accesses @698570 -system.cpu6: completed 30000 read accesses @1001408 -system.cpu1: completed 30000 read accesses @1004487 -system.cpu2: completed 30000 read accesses @1007345 -system.cpu4: completed 30000 read accesses @1009967 -system.cpu0: completed 30000 read accesses @1021321 -system.cpu7: completed 30000 read accesses @1025248 -system.cpu3: completed 30000 read accesses @1040400 -system.cpu5: completed 30000 read accesses @1042444 -system.cpu6: completed 40000 read accesses @1335158 -system.cpu1: completed 40000 read accesses @1341837 -system.cpu4: completed 40000 read accesses @1347757 -system.cpu2: completed 40000 read accesses @1348137 -system.cpu3: completed 40000 read accesses @1370930 -system.cpu0: completed 40000 read accesses @1372862 -system.cpu7: completed 40000 read accesses @1374480 -system.cpu5: completed 40000 read accesses @1395059 -system.cpu6: completed 50000 read accesses @1663756 -system.cpu2: completed 50000 read accesses @1676262 -system.cpu1: completed 50000 read accesses @1676376 -system.cpu4: completed 50000 read accesses @1689367 -system.cpu3: completed 50000 read accesses @1707722 -system.cpu7: completed 50000 read accesses @1715376 -system.cpu0: completed 50000 read accesses @1719053 -system.cpu5: completed 50000 read accesses @1756410 -system.cpu2: completed 60000 read accesses @1996507 -system.cpu6: completed 60000 read accesses @2009287 -system.cpu1: completed 60000 read accesses @2021631 -system.cpu4: completed 60000 read accesses @2032125 -system.cpu3: completed 60000 read accesses @2046121 -system.cpu7: completed 60000 read accesses @2054305 -system.cpu0: completed 60000 read accesses @2067865 -system.cpu5: completed 60000 read accesses @2103289 -system.cpu2: completed 70000 read accesses @2336053 -system.cpu6: completed 70000 read accesses @2351727 -system.cpu1: completed 70000 read accesses @2362242 -system.cpu3: completed 70000 read accesses @2365041 -system.cpu4: completed 70000 read accesses @2374894 -system.cpu7: completed 70000 read accesses @2393230 -system.cpu0: completed 70000 read accesses @2409417 -system.cpu5: completed 70000 read accesses @2444673 -system.cpu2: completed 80000 read accesses @2681751 -system.cpu1: completed 80000 read accesses @2695221 -system.cpu6: completed 80000 read accesses @2701603 -system.cpu3: completed 80000 read accesses @2708122 -system.cpu4: completed 80000 read accesses @2715599 -system.cpu7: completed 80000 read accesses @2739434 -system.cpu0: completed 80000 read accesses @2743943 -system.cpu5: completed 80000 read accesses @2780520 -system.cpu2: completed 90000 read accesses @3022424 -system.cpu1: completed 90000 read accesses @3030742 -system.cpu3: completed 90000 read accesses @3042635 -system.cpu6: completed 90000 read accesses @3050919 -system.cpu4: completed 90000 read accesses @3054095 -system.cpu0: completed 90000 read accesses @3084803 -system.cpu7: completed 90000 read accesses @3091274 -system.cpu5: completed 90000 read accesses @3116487 -system.cpu2: completed 100000 read accesses @3358188 +system.cpu3: completed 10000 read accesses @323743 +system.cpu2: completed 10000 read accesses @336402 +system.cpu1: completed 10000 read accesses @338132 +system.cpu0: completed 10000 read accesses @340751 +system.cpu5: completed 10000 read accesses @341263 +system.cpu4: completed 10000 read accesses @346558 +system.cpu7: completed 10000 read accesses @346738 +system.cpu6: completed 10000 read accesses @348135 +system.cpu3: completed 20000 read accesses @670303 +system.cpu0: completed 20000 read accesses @670934 +system.cpu2: completed 20000 read accesses @675651 +system.cpu1: completed 20000 read accesses @679374 +system.cpu6: completed 20000 read accesses @683883 +system.cpu7: completed 20000 read accesses @684999 +system.cpu4: completed 20000 read accesses @688475 +system.cpu5: completed 20000 read accesses @691089 +system.cpu3: completed 30000 read accesses @1012754 +system.cpu2: completed 30000 read accesses @1013014 +system.cpu5: completed 30000 read accesses @1015303 +system.cpu0: completed 30000 read accesses @1018359 +system.cpu1: completed 30000 read accesses @1021563 +system.cpu4: completed 30000 read accesses @1024489 +system.cpu6: completed 30000 read accesses @1024945 +system.cpu7: completed 30000 read accesses @1026805 +system.cpu3: completed 40000 read accesses @1337640 +system.cpu4: completed 40000 read accesses @1353749 +system.cpu5: completed 40000 read accesses @1355921 +system.cpu2: completed 40000 read accesses @1358297 +system.cpu0: completed 40000 read accesses @1365879 +system.cpu7: completed 40000 read accesses @1368402 +system.cpu6: completed 40000 read accesses @1369510 +system.cpu1: completed 40000 read accesses @1372174 +system.cpu3: completed 50000 read accesses @1687319 +system.cpu4: completed 50000 read accesses @1694511 +system.cpu7: completed 50000 read accesses @1696243 +system.cpu2: completed 50000 read accesses @1699794 +system.cpu5: completed 50000 read accesses @1700188 +system.cpu6: completed 50000 read accesses @1703368 +system.cpu0: completed 50000 read accesses @1704599 +system.cpu1: completed 50000 read accesses @1716501 +system.cpu4: completed 60000 read accesses @2030412 +system.cpu3: completed 60000 read accesses @2034929 +system.cpu2: completed 60000 read accesses @2036378 +system.cpu7: completed 60000 read accesses @2036726 +system.cpu0: completed 60000 read accesses @2038738 +system.cpu5: completed 60000 read accesses @2046852 +system.cpu1: completed 60000 read accesses @2050784 +system.cpu6: completed 60000 read accesses @2058109 +system.cpu3: completed 70000 read accesses @2359493 +system.cpu4: completed 70000 read accesses @2365063 +system.cpu2: completed 70000 read accesses @2371739 +system.cpu0: completed 70000 read accesses @2373666 +system.cpu7: completed 70000 read accesses @2373767 +system.cpu5: completed 70000 read accesses @2395804 +system.cpu1: completed 70000 read accesses @2404686 +system.cpu6: completed 70000 read accesses @2406335 +system.cpu2: completed 80000 read accesses @2701352 +system.cpu7: completed 80000 read accesses @2705729 +system.cpu3: completed 80000 read accesses @2707362 +system.cpu4: completed 80000 read accesses @2711169 +system.cpu0: completed 80000 read accesses @2718197 +system.cpu1: completed 80000 read accesses @2736476 +system.cpu6: completed 80000 read accesses @2746379 +system.cpu5: completed 80000 read accesses @2751740 +system.cpu2: completed 90000 read accesses @3041770 +system.cpu3: completed 90000 read accesses @3048359 +system.cpu7: completed 90000 read accesses @3049406 +system.cpu0: completed 90000 read accesses @3052026 +system.cpu4: completed 90000 read accesses @3061142 +system.cpu1: completed 90000 read accesses @3064341 +system.cpu6: completed 90000 read accesses @3079121 +system.cpu5: completed 90000 read accesses @3089679 +system.cpu2: completed 100000 read accesses @3377485 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 45cec6b56..be3549bde 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:38:10 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:39:45 -M5 executing on phenom -command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory +M5 compiled Aug 20 2010 12:10:28 +M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates +M5 started Aug 20 2010 12:10:38 +M5 executing on SC2B0629 +command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3358188 because maximum number of loads reached +Exiting @ tick 3377485 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index f32bc9111..b18cfb37f 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 332872 # Number of bytes of host memory used -host_seconds 24.53 # Real time elapsed on the host -host_tick_rate 136908 # Simulator tick rate (ticks/s) +host_mem_usage 341856 # Number of bytes of host memory used +host_seconds 29.56 # Real time elapsed on the host +host_tick_rate 114257 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003358 # Number of seconds simulated -sim_ticks 3358188 # Number of ticks simulated +sim_seconds 0.003377 # Number of seconds simulated +sim_ticks 3377485 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 98036 # number of read accesses completed -system.cpu0.num_writes 52677 # number of write accesses completed +system.cpu0.num_reads 99116 # number of read accesses completed +system.cpu0.num_writes 53019 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99903 # number of read accesses completed -system.cpu1.num_writes 53671 # number of write accesses completed +system.cpu1.num_reads 99151 # number of read accesses completed +system.cpu1.num_writes 53486 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53360 # number of write accesses completed +system.cpu2.num_writes 53183 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99545 # number of read accesses completed -system.cpu3.num_writes 53578 # number of write accesses completed +system.cpu3.num_reads 99632 # number of read accesses completed +system.cpu3.num_writes 54001 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99118 # number of read accesses completed -system.cpu4.num_writes 53226 # number of write accesses completed +system.cpu4.num_reads 99186 # number of read accesses completed +system.cpu4.num_writes 53590 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 96991 # number of read accesses completed -system.cpu5.num_writes 52753 # number of write accesses completed +system.cpu5.num_reads 98345 # number of read accesses completed +system.cpu5.num_writes 53268 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98713 # number of read accesses completed -system.cpu6.num_writes 52958 # number of write accesses completed +system.cpu6.num_reads 99155 # number of read accesses completed +system.cpu6.num_writes 53749 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97919 # number of read accesses completed -system.cpu7.num_writes 52935 # number of write accesses completed +system.cpu7.num_reads 99644 # number of read accesses completed +system.cpu7.num_writes 53528 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index 460712819..cffe74459 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -5,13 +5,14 @@ dummy=0 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -129,6 +137,50 @@ trace_addr=0 functional=system.funcmem.port[7] test=system.ruby.cpu_ruby_ports7.port[0] +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + [system.funcmem] type=PhysicalMemory file= @@ -139,168 +191,11 @@ range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort - -[system.ruby] -type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports0] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.cpu_ruby_ports1] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.cpu_ruby_ports2] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.cpu_ruby_ports3] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.cpu_ruby_ports4] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.cpu_ruby_ports5] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.cpu_ruby_ports6] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.cpu_ruby_ports7] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 -num_int_nodes=11 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] +[system.l1_cntrl0] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -308,6 +203,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -315,34 +211,27 @@ sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] +[system.l1_cntrl1] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -350,6 +239,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -357,34 +247,27 @@ sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] +[system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] +[system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.l1_cntrl2] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -392,6 +275,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -399,34 +283,27 @@ sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] +[system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] +[system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node -int_node=3 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links3.ext_node] +[system.l1_cntrl3] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -434,6 +311,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -441,34 +319,27 @@ sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] +[system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] +[system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node -int_node=4 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links4.ext_node] +[system.l1_cntrl4] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -476,6 +347,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -483,34 +355,27 @@ sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] +[system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] +[system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node -int_node=5 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links5.ext_node] +[system.l1_cntrl5] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -518,6 +383,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -525,34 +391,27 @@ sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] +[system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] +[system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node -int_node=6 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links6.ext_node] +[system.l1_cntrl6] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -560,6 +419,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -567,34 +427,27 @@ sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] +[system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] +[system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node -int_node=7 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links7.ext_node] +[system.l1_cntrl7] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -602,6 +455,7 @@ fixed_timeout_latency=300 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 @@ -609,102 +463,272 @@ sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] +[system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] +[system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links8] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node -int_node=8 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links8.ext_node] +[system.l2_cntrl0] type=L2Cache_Controller children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory N_tokens=9 buffer_size=0 filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 +l2_request_latency=5 +l2_response_latency=5 number_of_TBEs=256 recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] +[system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=0 -[system.ruby.network.topology.ext_links9] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.l1_cntrl1.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.l1_cntrl2.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.l1_cntrl3.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.l1_cntrl4.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl4.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.l1_cntrl5.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl5.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.l1_cntrl6.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl6.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.l1_cntrl7.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl7.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +num_int_nodes=11 +print_config=false + +[system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node -int_node=9 +ext_node=system.l1_cntrl0 +int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl1 +int_node=1 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl2 +int_node=2 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 +[system.ruby.network.topology.ext_links3] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl3 +int_node=3 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl4 +int_node=4 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links5] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl5 +int_node=5 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links6] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl6 +int_node=6 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links7] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl7 +int_node=7 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links8] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=8 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links9] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=9 +latency=1 +weight=1 [system.ruby.network.topology.int_links0] type=IntLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index 036c1db6a..7b2bdba27 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/01/2010 14:40:39 +Real time: Aug/20/2010 12:14:59 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0.433333 Elapsed_time_in_hours: 0.00722222 Elapsed_time_in_days: 0.000300926 -Virtual_time_in_seconds: 26.08 -Virtual_time_in_minutes: 0.434667 -Virtual_time_in_hours: 0.00724444 -Virtual_time_in_days: 0.000301852 +Virtual_time_in_seconds: 25.78 +Virtual_time_in_minutes: 0.429667 +Virtual_time_in_hours: 0.00716111 +Virtual_time_in_days: 0.00029838 -Ruby_current_time: 3229931 +Ruby_current_time: 2583072 Ruby_start_time: 0 -Ruby_cycles: 3229931 +Ruby_cycles: 2583072 -mbytes_resident: 32.3867 -mbytes_total: 325.047 -resident_ratio: 0.0996491 +mbytes_resident: 32.8789 +mbytes_total: 333.961 +resident_ratio: 0.0984747 -ruby_cycles_executed: [ 3229932 3229932 3229932 3229932 3229932 3229932 3229932 3229932 ] +ruby_cycles_executed: [ 2583073 2583073 2583073 2583073 2583073 2583073 2583073 2583073 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,31 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1209436 average: 1.99443 | standard deviation: 0.0744408 | 0 6739 1202697 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1202451 average: 1.98763 | standard deviation: 0.110552 | 0 14880 1187571 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1074 count: 1209420 average: 40.7265 | standard deviation: 150.859 | 1138116 0 121 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69534 1022 106 161 136 90 74 14 17 8 0 0 0 0 0 6 4 1 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 949 count: 786341 average: 40.6919 | standard deviation: 150.795 | 740099 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45198 631 68 105 94 61 49 6 10 8 0 0 0 0 0 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 1074 count: 423079 average: 40.7906 | standard deviation: 150.976 | 398017 0 121 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24336 391 38 56 42 29 25 8 7 0 0 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1010 count: 1202436 average: 32.3679 | standard deviation: 136.165 | 1145435 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 8 max: 1010 count: 782221 average: 32.3974 | standard deviation: 136.229 | 745119 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 8 max: 825 count: 420215 average: 32.313 | standard deviation: 136.046 | 400316 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 1145435 average: 2 | standard deviation: 0 | 0 0 1145435 ] +miss_latency_Directory: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 8 max: 1010 count: 56999 average: 642.622 | standard deviation: 13.675 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_first_response_to_completion: [binsize: 8 max: 887 count: 6 average: 764.333 | standard deviation: 101.837 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_wCC_Times: 56993 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 745119 average: 2 | standard deviation: 0 | 0 0 745119 ] +miss_latency_LD_Directory: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 8 max: 1010 count: 37100 average: 642.885 | standard deviation: 5.20071 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 400316 average: 2 | standard deviation: 0 | 0 0 400316 ] +miss_latency_ST_L1Cache_wCC: [binsize: 8 max: 825 count: 19899 average: 642.132 | standard deviation: 22.02 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,3081 +121,924 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 26 +user_time: 25 system_time: 0 -page_reclaims: 8508 +page_reclaims: 9519 page_faults: 0 swaps: 0 -block_inputs: 24 -block_outputs: 72 +block_inputs: 16 +block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 342090 2736720 +total_msg_count_Response_Data: 170931 12307032 +total_msg_count_ResponseLocal_Data: 48 3456 +total_msg_count_Response_Control: 170943 1367544 +total_msg_count_Broadcast_Control: 855225 6841800 +total_msg_count_Persistent_Control: 2279000 18232000 +total_msgs: 3818237 total_bytes: 41488552 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.151652 - links_utilized_percent_switch_0_link_0: 0.110271 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.193034 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 62398 499184 [ 0 62398 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 17840 142720 [ 0 17840 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 8902 640944 [ 0 0 0 0 8902 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 8900 71200 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.151672 + links_utilized_percent_switch_0_link_0: 0.110312 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.193032 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151663 - links_utilized_percent_switch_1_link_0: 0.110278 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.193049 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 8901 640872 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 8900 71200 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Persistent_Control: 17796 142368 [ 0 0 0 17796 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.151704 + links_utilized_percent_switch_1_link_0: 0.11032 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.193088 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Persistent_Control: 14242 113936 [ 0 0 0 14242 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.151622 - links_utilized_percent_switch_2_link_0: 0.110265 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.192979 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 8896 640512 [ 0 0 0 0 8896 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 8901 71208 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Persistent_Control: 17795 142360 [ 0 0 0 17795 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.151685 + links_utilized_percent_switch_2_link_0: 0.110312 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.193057 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 7120 512640 [ 0 0 0 0 7120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.151632 - links_utilized_percent_switch_3_link_0: 0.110268 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.192996 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 17832 142656 [ 0 17832 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 8901 71208 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 17795 142360 [ 0 0 0 17795 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.151691 + links_utilized_percent_switch_3_link_0: 0.110313 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.193069 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Broadcast_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.151623 - links_utilized_percent_switch_4_link_0: 0.110263 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.192984 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 8893 640296 [ 0 0 0 0 8893 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 8903 71224 [ 0 0 0 0 8903 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Persistent_Control: 17796 142368 [ 0 0 0 17796 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.1517 + links_utilized_percent_switch_4_link_0: 0.110316 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.193084 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Broadcast_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.151636 - links_utilized_percent_switch_5_link_0: 0.110271 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.193001 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.151686 + links_utilized_percent_switch_5_link_0: 0.110312 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.193059 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 62407 499256 [ 0 62407 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 17822 142576 [ 0 17822 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 8901 640872 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 8897 71176 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 7119 512568 [ 0 0 0 0 7119 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.151646 - links_utilized_percent_switch_6_link_0: 0.110272 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.19302 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 17832 142656 [ 0 17832 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 8900 640800 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 8899 71192 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.151673 + links_utilized_percent_switch_6_link_0: 0.110309 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.193038 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 7125 57000 [ 0 0 0 0 7125 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.151601 - links_utilized_percent_switch_7_link_0: 0.110257 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.192945 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 62408 499264 [ 0 62408 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 17822 142576 [ 0 17822 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 8890 640080 [ 0 0 0 0 8890 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 8902 71216 [ 0 0 0 0 8902 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Persistent_Control: 17798 142384 [ 0 0 0 17798 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.151662 + links_utilized_percent_switch_7_link_0: 0.110309 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.193014 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 7121 512712 [ 0 0 0 0 7121 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.110314 - links_utilized_percent_switch_8_link_0: 0.110225 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.110402 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.110331 + links_utilized_percent_switch_8_link_0: 0.110299 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.110363 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 71318 570544 [ 0 71318 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 71136 569088 [ 0 0 0 0 71136 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 0.0413616 - links_utilized_percent_switch_9_link_0: 0.0826953 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.78644e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.0413841 + links_utilized_percent_switch_9_link_0: 0.0827334 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 3.48422e-05 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.407988 - links_utilized_percent_switch_10_link_0: 0.41354 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.413561 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.413513 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.413526 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.413503 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.413538 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.413541 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.413475 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.440901 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 0.330781 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 62398 499184 [ 0 62398 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Persistent_Control: 124566 996528 [ 0 0 0 124566 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Persistent_Control: 124567 996536 [ 0 0 0 124567 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Persistent_Control: 124567 996536 [ 0 0 0 124567 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Persistent_Control: 124566 996528 [ 0 0 0 124566 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 62407 499256 [ 0 62407 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.408158 + links_utilized_percent_switch_10_link_0: 0.413678 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.413713 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.413678 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.41368 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.413693 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.413678 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.413664 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.413664 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.441198 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 0.330933 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Persistent_Control: 99708 797664 [ 0 0 0 99708 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_5_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 62408 499264 [ 0 62408 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Persistent_Control: 124564 996512 [ 0 0 0 124564 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 71318 570544 [ 0 71318 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 71136 569088 [ 0 0 0 0 71136 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- + outgoing_messages_switch_10_link_5_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 7125 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.9965% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.0035% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + + --- L1Cache --- - Event Counts - -Load 99666 -Ifetch 0 -Store 53551 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 16 -Data_All_Tokens 8891 -Ack 1 -Ack_All_Tokens 11 -Transient_GETX 0 -Transient_Local_GETX 21942 -Transient_GETS 0 -Transient_Local_GETS 40456 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 24652 -Persistent_GETS 45581 -Own_Lock_or_Unlock 72129 -Request_Timeout 9283 -Use_TimeoutStarverX 3 -Use_TimeoutStarverS 4 -Use_TimeoutNoStarvers 8895 +Load [97598 97330 96960 97500 100000 98829 96777 97237 ] 782231 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [52430 52106 52281 52110 53664 53487 51846 52295 ] 420219 +Atomic [0 0 0 0 0 0 0 0 ] 0 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Data_Shared [0 0 0 0 0 0 0 0 ] 0 +Data_Owner [6 6 3 2 1 3 5 4 ] 30 +Data_All_Tokens [7119 7118 7120 7121 7123 7123 7119 7120 ] 56963 +Ack [0 1 1 1 0 0 1 2 ] 6 +Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11 +Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETX [17379 17433 17386 17429 17409 17431 17418 17436 ] 139321 +Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETS [32507 32455 32504 32461 32481 32457 32470 32449 ] 259784 +Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Persistent_GETX [19681 19967 19851 19972 19399 19393 19734 19360 ] 157357 +Persistent_GETS [36732 37056 37006 37152 36090 36049 36638 36016 ] 292739 +Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Own_Lock_or_Unlock [57537 56927 57093 56826 58461 58508 57578 58574 ] 461504 +Request_Timeout [7147 7226 7147 7140 7122 7468 7539 7333 ] 58122 +Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123 +Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177 +Use_TimeoutNoStarvers [7105 7073 7098 7046 7123 7109 6997 7123 ] 56674 +Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 3 -I Ifetch 0 <-- -I Store 4 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 1 - -S Load 3 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 2 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 13 -O Ifetch 0 <-- -O Store 11 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 5 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 15 - -M Load 149 -M Ifetch 0 <-- -M Store 72 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 11 -M Persistent_GETS 14 -M Own_Lock_or_Unlock 72 - -MM Load 39155 -MM Ifetch 0 <-- -MM Store 21046 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3081 -MM Persistent_GETS 5789 -MM Own_Lock_or_Unlock 8681 - -M_W Load 10405 -M_W Ifetch 0 <-- -M_W Store 5678 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1514 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2959 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 11 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 97 - -MM_W Load 44130 -MM_W Ifetch 0 <-- -MM_W Store 23628 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 947 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1674 -MM_W Persistent_GETX 3 -MM_W Persistent_GETS 4 -MM_W Own_Lock_or_Unlock 116 -MM_W Use_TimeoutStarverX 3 -MM_W Use_TimeoutStarverS 4 -MM_W Use_TimeoutNoStarvers 8798 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3107 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 273 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 409 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5555 -IM Persistent_GETS 10291 -IM Own_Lock_or_Unlock 3107 -IM Request_Timeout 2214 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 9 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 3 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 11 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 4 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 1 -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 16 -IS Data_All_Tokens 5775 -IS Ack 1 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 481 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 797 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10383 -IS Persistent_GETS 19203 -IS Own_Lock_or_Unlock 5794 -IS Request_Timeout 4171 - -I_L Load 5788 -I_L Ifetch 0 <-- -I_L Store 3100 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 3 -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 18 -S_L Ifetch 0 <-- -S_L Store 11 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 3 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6467 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12155 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2008 -IM_L Persistent_GETS 3584 -IM_L Own_Lock_or_Unlock 18946 -IM_L Request_Timeout 1024 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 11 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12246 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22461 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3608 -IS_L Persistent_GETS 6696 -IS_L Own_Lock_or_Unlock 35372 -IS_L Request_Timeout 1874 - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 1 --- - - Event Counts - -Load 97849 -Ifetch 0 -Store 52926 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 14 -Data_All_Tokens 8895 -Ack 0 -Ack_All_Tokens 5 -Transient_GETX 0 -Transient_Local_GETX 21897 -Transient_GETS 0 -Transient_Local_GETS 40506 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 24686 -Persistent_GETS 45801 -Own_Lock_or_Unlock 71875 -Request_Timeout 8949 -Use_TimeoutStarverX 3 -Use_TimeoutStarverS 4 -Use_TimeoutNoStarvers 8893 +NP Load [2 2 1 2 2 2 2 1 ] 14 +NP Ifetch [0 0 0 0 0 0 0 0 ] 0 +NP Store [0 0 1 0 0 0 0 1 ] 2 +NP Atomic [0 0 0 0 0 0 0 0 ] 0 +NP Data_Shared [0 0 0 0 0 0 0 0 ] 0 +NP Data_Owner [0 0 0 0 0 0 0 0 ] 0 +NP Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +NP Ack [0 0 0 0 0 0 0 0 ] 0 +NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +NP Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 + +I Load [1 4 1 0 0 2 4 0 ] 12 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [1 1 1 1 1 0 0 0 ] 5 +I Atomic [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I Data_Shared [0 0 0 0 0 0 0 0 ] 0 +I Data_Owner [0 0 0 0 0 0 0 0 ] 0 +I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +I Ack [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Own_Lock_or_Unlock [0 1 0 0 0 1 0 0 ] 2 + +S Load [0 0 4 0 0 2 0 2 ] 8 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [0 0 0 0 1 2 0 1 ] 4 +S Atomic [0 0 0 0 0 0 0 0 ] 0 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S Data_Shared [0 0 0 0 0 0 0 0 ] 0 +S Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +S Ack [0 0 0 0 0 0 0 0 ] 0 +S Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETX [0 0 1 0 0 0 0 0 ] 1 +S Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 + +O Load [7 3 2 5 1 0 9 0 ] 27 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [3 1 1 1 0 0 1 4 ] 11 +O Atomic [0 0 0 0 0 0 0 0 ] 0 +O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +O Data_Shared [0 0 0 0 0 0 0 0 ] 0 +O Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Ack [0 0 0 0 0 0 1 1 ] 2 +O Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETX [2 5 1 1 1 2 4 0 ] 16 +O Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Own_Lock_or_Unlock [4 4 1 2 1 1 4 1 ] 18 + +M Load [28 73 44 39 51 47 48 45 ] 375 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [22 27 20 30 34 31 25 34 ] 223 +M Atomic [0 0 0 0 0 0 0 0 ] 0 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +M Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +M Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +M Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +M Persistent_GETX [2 2 4 1 2 1 3 3 ] 18 +M Persistent_GETS [4 4 3 1 3 5 2 3 ] 25 +M Own_Lock_or_Unlock [19 24 20 17 24 22 19 23 ] 168 + +MM Load [37560 37440 37171 37275 39797 38949 36895 37075 ] 302162 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [20087 19886 19931 20132 21523 20999 19589 20207 ] 162354 +MM Atomic [0 0 0 0 0 0 0 0 ] 0 +MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +MM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +MM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +MM Persistent_GETX [2470 2470 2418 2451 2479 2469 2466 2510 ] 19733 +MM Persistent_GETS [4629 4597 4673 4592 4638 4634 4526 4607 ] 36896 +MM Own_Lock_or_Unlock [6898 6682 6801 6585 7078 6942 6691 7047 ] 54724 + +M_W Load [8494 8681 8359 8508 8736 8655 8348 8688 ] 68469 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [4571 4617 4577 4617 4591 4614 4605 4617 ] 36809 +M_W Atomic [0 0 0 0 0 0 0 0 ] 0 +M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_Local_GETX [1166 1154 1141 1143 1201 1194 1152 1185 ] 9336 +M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_Local_GETS [2166 2212 2154 2181 2163 2167 2179 2189 ] 17411 +M_W Persistent_GETX [0 1 0 1 0 0 4 0 ] 6 +M_W Persistent_GETS [0 1 0 0 0 0 2 0 ] 3 +M_W Own_Lock_or_Unlock [1 0 0 0 2 3 0 1 ] 7 +M_W Use_TimeoutStarverX [0 0 0 0 0 0 0 0 ] 0 +M_W Use_TimeoutStarverS [0 0 0 0 0 0 0 0 ] 0 +M_W Use_TimeoutNoStarvers [28 33 27 32 39 37 30 40 ] 266 +M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 + +MM_W Load [46901 46467 46766 47022 46777 46509 46835 46760 ] 374037 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [25226 25106 25236 24857 25022 25371 25142 24970 ] 200930 +MM_W Atomic [0 0 0 0 0 0 0 0 ] 0 +MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_Local_GETX [726 705 680 664 692 661 707 713 ] 5548 +MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_Local_GETS [1308 1301 1347 1301 1330 1295 1309 1253 ] 10444 +MM_W Persistent_GETX [6 17 10 26 0 6 48 0 ] 113 +MM_W Persistent_GETS [11 26 13 47 0 8 62 1 ] 168 +MM_W Own_Lock_or_Unlock [56 8 48 0 16 91 27 45 ] 291 +MM_W Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123 +MM_W Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177 +MM_W Use_TimeoutNoStarvers [7077 7040 7071 7014 7084 7072 6967 7083 ] 56408 +MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 + +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM Atomic [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IM Data_Owner [1 0 1 0 0 1 0 0 ] 3 +IM Data_All_Tokens [2518 2465 2516 2471 2492 2469 2479 2461 ] 19871 +IM Ack [0 1 1 1 0 0 0 1 ] 4 +IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETX [222 216 237 258 221 212 225 232 ] 1823 +IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETS [400 402 434 422 408 454 399 431 ] 3350 +IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Persistent_GETX [4521 4513 4646 4487 4479 4548 4472 4529 ] 36195 +IM Persistent_GETS [8641 8405 8595 8462 8549 8387 8536 8357 ] 67932 +IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Own_Lock_or_Unlock [2182 1996 2007 1984 2492 2470 2235 2406 ] 17772 +IM Request_Timeout [1799 1793 1784 1765 1766 1755 1871 1763 ] 14296 + +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM Atomic [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +SM Data_Owner [0 0 0 0 0 0 0 0 ] 0 +SM Data_All_Tokens [2 2 0 1 1 3 2 2 ] 13 +SM Ack [0 0 0 0 0 0 0 0 ] 0 +SM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETX [3 2 3 0 2 2 0 1 ] 13 +SM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETS [0 0 0 0 0 2 0 0 ] 2 +SM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 +SM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 + +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM Atomic [0 0 0 0 0 0 0 0 ] 0 +OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +OM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +OM Ack [0 0 0 0 0 0 0 0 ] 0 +OM Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11 +OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETX [3 1 1 0 0 0 0 3 ] 8 +OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETS [0 0 0 1 0 0 0 0 ] 1 +OM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Persistent_GETX [0 0 0 0 0 1 0 0 ] 1 +OM Persistent_GETS [1 0 1 0 0 0 0 0 ] 2 +OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Own_Lock_or_Unlock [0 1 0 0 0 0 0 3 ] 4 +OM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 + +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS Atomic [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IS Data_Owner [5 6 2 2 1 2 5 4 ] 27 +IS Data_All_Tokens [4599 4650 4604 4647 4630 4651 4631 4657 ] 37069 +IS Ack [0 0 0 0 0 0 0 0 ] 0 +IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETX [400 408 389 443 408 431 429 415 ] 3323 +IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETS [769 757 780 755 748 754 760 742 ] 6065 +IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Persistent_GETX [8371 8439 8397 8510 8389 8397 8431 8464 ] 67398 +IS Persistent_GETS [15722 16004 15772 15880 15673 15863 15872 16008 ] 126794 +IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Own_Lock_or_Unlock [3999 3732 3684 3780 4636 4659 4178 4566 ] 33234 +IS Request_Timeout [3330 3318 3254 3362 3293 3408 3544 3379 ] 26888 + +I_L Load [4602 4651 4606 4649 4629 4651 4636 4662 ] 37086 +I_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +I_L Store [2516 2464 2512 2471 2490 2467 2482 2459 ] 19861 +I_L Atomic [0 0 0 0 0 0 0 0 ] 0 +I_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +I_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +I_L Ack [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Persistent_GETX [29 83 67 101 1 11 63 0 ] 355 +I_L Persistent_GETS [52 140 100 186 1 27 119 0 ] 625 +I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 + +S_L Load [3 9 6 0 7 12 0 4 ] 41 +S_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +S_L Store [4 4 2 1 2 3 2 2 ] 20 +S_L Atomic [0 0 0 0 0 0 0 0 ] 0 +S_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +S_L Ack [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Own_Lock_or_Unlock [0 0 1 0 1 2 0 1 ] 5 + +IM_L Load [0 0 0 0 0 0 0 0 ] 0 +IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM_L Store [0 0 0 0 0 0 0 0 ] 0 +IM_L Atomic [0 0 0 0 0 0 0 0 ] 0 +IM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_All_Tokens [0 1 0 0 0 0 3 0 ] 4 +IM_L Ack [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETX [5265 5143 5258 5229 5111 5141 5302 5088 ] 41537 +IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETS [9843 9650 9830 9596 9842 9666 9585 9672 ] 77684 +IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM_L Persistent_GETX [1517 1566 1504 1478 1373 1311 1418 1290 ] 11457 +IM_L Persistent_GETS [2742 2736 2735 2863 2483 2456 2680 2521 ] 21216 +IM_L Own_Lock_or_Unlock [15678 15381 15753 15420 15518 15403 15487 15345 ] 123985 +IM_L Request_Timeout [719 701 732 708 726 823 763 775 ] 5947 + +SM_L Load [0 0 0 0 0 0 0 0 ] 0 +SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM_L Store [0 0 0 0 0 0 0 0 ] 0 +SM_L Atomic [0 0 0 0 0 0 0 0 ] 0 +SM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +SM_L Ack [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Persistent_GETS [0 0 0 0 0 0 1 0 ] 1 +SM_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Own_Lock_or_Unlock [5 4 3 1 2 3 2 2 ] 22 +SM_L Request_Timeout [0 0 0 0 0 0 0 0 ] 0 + +IS_L Load [0 0 0 0 0 0 0 0 ] 0 +IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS_L Store [0 0 0 0 0 0 0 0 ] 0 +IS_L Atomic [0 0 0 0 0 0 0 0 ] 0 +IS_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_All_Tokens [0 0 0 2 0 0 4 0 ] 6 +IS_L Ack [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETX [9592 9799 9675 9691 9773 9788 9599 9799 ] 77716 +IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETS [18021 18133 17959 18205 17990 18119 18238 18162 ] 144827 +IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS_L Persistent_GETX [2765 2876 2805 2917 2676 2649 2829 2564 ] 22081 +IS_L Persistent_GETS [4930 5143 5114 5121 4743 4669 4838 4519 ] 39077 +IS_L Own_Lock_or_Unlock [28695 29094 28775 29037 28691 28911 28935 29134 ] 231272 +IS_L Request_Timeout [1299 1414 1377 1305 1337 1482 1361 1416 ] 10991 + +Cache Stats: system.l1_cntrl1.L1IcacheMemory + system.l1_cntrl1.L1IcacheMemory_total_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl1.L1DcacheMemory + system.l1_cntrl1.L1DcacheMemory_total_misses: 7127 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.315% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.685% + + system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% + +Cache Stats: system.l1_cntrl2.L1IcacheMemory + system.l1_cntrl2.L1IcacheMemory_total_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1DcacheMemory + system.l1_cntrl2.L1DcacheMemory_total_misses: 7127 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.1326% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.8674% + + system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% + +Cache Stats: system.l1_cntrl3.L1IcacheMemory + system.l1_cntrl3.L1IcacheMemory_total_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1DcacheMemory + system.l1_cntrl3.L1DcacheMemory_total_misses: 7130 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 7130 + system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.3997% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.6003% + + system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 7130 100% + +Cache Stats: system.l1_cntrl4.L1IcacheMemory + system.l1_cntrl4.L1IcacheMemory_total_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.L1DcacheMemory + system.l1_cntrl4.L1DcacheMemory_total_misses: 7129 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 7129 + system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.5953% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.4047% + + system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 7129 100% + +Cache Stats: system.l1_cntrl5.L1IcacheMemory + system.l1_cntrl5.L1IcacheMemory_total_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1DcacheMemory + system.l1_cntrl5.L1DcacheMemory_total_misses: 7127 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 6 -I Ifetch 0 <-- -I Store 3 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 3 - -S Load 1 -S Ifetch 0 <-- -S Store 2 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 7 -O Ifetch 0 <-- -O Store 5 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 8 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 10 - -M Load 157 -M Ifetch 0 <-- -M Store 87 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 2 -M Persistent_GETS 14 -M Own_Lock_or_Unlock 73 - -MM Load 37407 -MM Ifetch 0 <-- -MM Store 20168 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3149 -MM Persistent_GETS 5728 -MM Own_Lock_or_Unlock 8660 - -M_W Load 10437 -M_W Ifetch 0 <-- -M_W Store 5625 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1592 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2880 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 3 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 103 - -MM_W Load 44078 -MM_W Ifetch 0 <-- -MM_W Store 23874 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 953 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1733 -MM_W Persistent_GETX 3 -MM_W Persistent_GETS 4 -MM_W Own_Lock_or_Unlock 123 -MM_W Use_TimeoutStarverX 3 -MM_W Use_TimeoutStarverS 4 -MM_W Use_TimeoutNoStarvers 8790 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 1 -IM Data_All_Tokens 3157 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 272 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 427 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5610 -IM Persistent_GETS 10506 -IM Own_Lock_or_Unlock 3021 -IM Request_Timeout 2203 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 10 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 4 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 5 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 2 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 1 -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 13 -IS Data_All_Tokens 5728 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 444 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 758 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10291 -IS Persistent_GETS 19195 -IS Own_Lock_or_Unlock 5481 -IS Request_Timeout 3967 - -I_L Load 5737 -I_L Ifetch 0 <-- -I_L Store 3149 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 5 -I_L Persistent_GETS 11 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 19 -S_L Ifetch 0 <-- -S_L Store 11 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 3 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6621 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12284 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2040 -IM_L Persistent_GETS 3733 -IM_L Own_Lock_or_Unlock 19265 -IM_L Request_Timeout 979 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 12 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12000 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22424 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3586 -IS_L Persistent_GETS 6608 -IS_L Own_Lock_or_Unlock 35221 -IS_L Request_Timeout 1800 - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 2 --- - - Event Counts - -Load 100000 -Ifetch 0 -Store 54082 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 17 -Data_All_Tokens 8888 -Ack 0 -Ack_All_Tokens 9 -Transient_GETX 0 -Transient_Local_GETX 21915 -Transient_GETS 0 -Transient_Local_GETS 40488 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 24880 -Persistent_GETS 46033 -Own_Lock_or_Unlock 71449 -Request_Timeout 8898 -Use_TimeoutStarverX 10 -Use_TimeoutStarverS 14 -Use_TimeoutNoStarvers 8872 + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.3431% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.6569% - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 7 -I Ifetch 0 <-- -I Store 4 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 3 - -S Load 8 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 3 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 11 -O Ifetch 0 <-- -O Store 9 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 8 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 14 - -M Load 188 -M Ifetch 0 <-- -M Store 102 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 9 -M Persistent_GETS 13 -M Own_Lock_or_Unlock 83 - -MM Load 39705 -MM Ifetch 0 <-- -MM Store 21181 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3130 -MM Persistent_GETS 5720 -MM Own_Lock_or_Unlock 8637 - -M_W Load 10480 -M_W Ifetch 0 <-- -M_W Store 5620 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1566 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2909 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 1 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 124 - -MM_W Load 43821 -MM_W Ifetch 0 <-- -MM_W Store 24025 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 914 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1744 -MM_W Persistent_GETX 10 -MM_W Persistent_GETS 14 -MM_W Own_Lock_or_Unlock 23 -MM_W Use_TimeoutStarverX 10 -MM_W Use_TimeoutStarverS 14 -MM_W Use_TimeoutNoStarvers 8748 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3138 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 270 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 428 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5591 -IM Persistent_GETS 10381 -IM Own_Lock_or_Unlock 2975 -IM Request_Timeout 2196 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 6 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 4 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 9 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 8 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 1 -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 17 -IS Data_All_Tokens 5744 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 441 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 766 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10221 -IS Persistent_GETS 19165 -IS Own_Lock_or_Unlock 5460 -IS Request_Timeout 3916 - -I_L Load 5753 -I_L Ifetch 0 <-- -I_L Store 3130 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 31 -I_L Persistent_GETS 63 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 26 -S_L Ifetch 0 <-- -S_L Store 9 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 4 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6599 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12210 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2151 -IM_L Persistent_GETS 3738 -IM_L Own_Lock_or_Unlock 19101 -IM_L Request_Timeout 941 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 9 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12102 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22430 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3737 -IS_L Persistent_GETS 6939 -IS_L Own_Lock_or_Unlock 35139 -IS_L Request_Timeout 1845 - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 3 --- - - Event Counts - -Load 97548 -Ifetch 0 -Store 52845 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 15 -Data_All_Tokens 8890 -Ack 0 -Ack_All_Tokens 9 -Transient_GETX 0 -Transient_Local_GETX 21893 -Transient_GETS 0 -Transient_Local_GETS 40509 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 24936 -Persistent_GETS 46314 -Own_Lock_or_Unlock 71112 -Request_Timeout 9055 -Use_TimeoutStarverX 18 -Use_TimeoutStarverS 47 -Use_TimeoutNoStarvers 8834 + system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 8 -I Ifetch 0 <-- -I Store 2 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 4 - -S Load 7 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 4 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 21 -O Ifetch 0 <-- -O Store 9 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 6 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 11 - -M Load 149 -M Ifetch 0 <-- -M Store 71 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 7 -M Persistent_GETS 17 -M Own_Lock_or_Unlock 70 - -MM Load 37142 -MM Ifetch 0 <-- -MM Store 20055 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3053 -MM Persistent_GETS 5757 -MM Own_Lock_or_Unlock 8418 - -M_W Load 10116 -M_W Ifetch 0 <-- -M_W Store 5630 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1537 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2910 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 3 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 95 - -MM_W Load 44353 -MM_W Ifetch 0 <-- -MM_W Store 23913 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 966 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1750 -MM_W Persistent_GETX 18 -MM_W Persistent_GETS 46 -MM_W Own_Lock_or_Unlock 99 -MM_W Use_TimeoutStarverX 18 -MM_W Use_TimeoutStarverS 47 -MM_W Use_TimeoutNoStarvers 8739 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3157 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 240 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 417 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5599 -IM Persistent_GETS 10582 -IM Own_Lock_or_Unlock 2850 -IM Request_Timeout 2215 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 8 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 5 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 9 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 5 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 15 -IS Data_All_Tokens 5724 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 467 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 762 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10393 -IS Persistent_GETS 18988 -IS Own_Lock_or_Unlock 5198 -IS Request_Timeout 4113 - -I_L Load 5731 -I_L Ifetch 0 <-- -I_L Store 3151 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 58 -I_L Persistent_GETS 108 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 20 -S_L Ifetch 0 <-- -S_L Store 12 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 5 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6699 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12233 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2031 -IM_L Persistent_GETS 3864 -IM_L Own_Lock_or_Unlock 19331 -IM_L Request_Timeout 1000 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 2 -SM_L Own_Lock_or_Unlock 12 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 1 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 11964 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22437 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3777 -IS_L Persistent_GETS 6949 -IS_L Own_Lock_or_Unlock 35111 -IS_L Request_Timeout 1727 - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 4 --- - - Event Counts - -Load 98336 -Ifetch 0 -Store 52558 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 22 -Data_All_Tokens 8882 -Ack 2 -Ack_All_Tokens 10 -Transient_GETX 0 -Transient_Local_GETX 21927 -Transient_GETS 0 -Transient_Local_GETS 40476 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 24899 -Persistent_GETS 46131 -Own_Lock_or_Unlock 71332 -Request_Timeout 8962 -Use_TimeoutStarverX 11 -Use_TimeoutStarverS 17 -Use_TimeoutNoStarvers 8864 +Cache Stats: system.l1_cntrl6.L1IcacheMemory + system.l1_cntrl6.L1IcacheMemory_total_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 10 -I Ifetch 0 <-- -I Store 4 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 - -S Load 2 -S Ifetch 0 <-- -S Store 2 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 3 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 20 -O Ifetch 0 <-- -O Store 10 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 11 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 19 - -M Load 166 -M Ifetch 0 <-- -M Store 86 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 10 -M Persistent_GETS 16 -M Own_Lock_or_Unlock 83 - -MM Load 37712 -MM Ifetch 0 <-- -MM Store 19992 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3090 -MM Persistent_GETS 5748 -MM Own_Lock_or_Unlock 8387 - -M_W Load 10442 -M_W Ifetch 0 <-- -M_W Store 5639 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1598 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2819 -M_W Persistent_GETX 1 -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 3 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 112 - -MM_W Load 44196 -MM_W Ifetch 0 <-- -MM_W Store 23699 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 902 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1779 -MM_W Persistent_GETX 9 -MM_W Persistent_GETS 17 -MM_W Own_Lock_or_Unlock 95 -MM_W Use_TimeoutStarverX 11 -MM_W Use_TimeoutStarverS 17 -MM_W Use_TimeoutNoStarvers 8752 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 1 -IM Data_All_Tokens 3126 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 229 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 407 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5549 -IM Persistent_GETS 10517 -IM Own_Lock_or_Unlock 2855 -IM Request_Timeout 2152 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 5 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 9 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 10 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 7 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 1 -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 21 -IS Data_All_Tokens 5750 -IS Ack 1 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 491 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 805 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10484 -IS Persistent_GETS 19149 -IS Own_Lock_or_Unlock 5299 -IS Request_Timeout 4040 - -I_L Load 5761 -I_L Ifetch 0 <-- -I_L Store 3115 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 80 -I_L Persistent_GETS 123 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 25 -S_L Ifetch 0 <-- -S_L Store 11 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 5 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6491 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12257 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 1961 -IM_L Persistent_GETS 3726 -IM_L Own_Lock_or_Unlock 19180 -IM_L Request_Timeout 988 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 12 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 1 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12186 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22408 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3715 -IS_L Persistent_GETS 6833 -IS_L Own_Lock_or_Unlock 35392 -IS_L Request_Timeout 1782 - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 97596 -Ifetch 0 -Store 52680 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 8 -Data_All_Tokens 8899 -Ack 0 -Ack_All_Tokens 2 -Transient_GETX 0 -Transient_Local_GETX 22013 -Transient_GETS 0 -Transient_Local_GETS 40394 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25459 -Persistent_GETS 46885 -Own_Lock_or_Unlock 70018 -Request_Timeout 9144 -Use_TimeoutStarverX 41 -Use_TimeoutStarverS 78 -Use_TimeoutNoStarvers 8782 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 5 -I Ifetch 0 <-- -I Store 1 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 3 - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 2 -O Ifetch 0 <-- -O Store 2 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 6 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 5 - -M Load 143 -M Ifetch 0 <-- -M Store 82 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 10 -M Persistent_GETS 12 -M Own_Lock_or_Unlock 75 - -MM Load 37054 -MM Ifetch 0 <-- -MM Store 20002 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3069 -MM Persistent_GETS 5691 -MM Own_Lock_or_Unlock 8228 - -M_W Load 10582 -M_W Ifetch 0 <-- -M_W Store 5741 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1563 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2981 -M_W Persistent_GETX 1 -M_W Persistent_GETS 1 -M_W Own_Lock_or_Unlock 2 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 104 - -MM_W Load 43952 -MM_W Ifetch 0 <-- -MM_W Store 23799 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 896 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1686 -MM_W Persistent_GETX 40 -MM_W Persistent_GETS 76 -MM_W Own_Lock_or_Unlock 48 -MM_W Use_TimeoutStarverX 41 -MM_W Use_TimeoutStarverS 77 -MM_W Use_TimeoutNoStarvers 8678 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3043 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 264 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 412 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5392 -IM Persistent_GETS 10154 -IM Own_Lock_or_Unlock 2439 -IM Request_Timeout 2167 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 10 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 3 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 2 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 2 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 8 -IS Data_All_Tokens 5845 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 462 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 808 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10637 -IS Persistent_GETS 19370 -IS Own_Lock_or_Unlock 4767 -IS Request_Timeout 4200 - -I_L Load 5849 -I_L Ifetch 0 <-- -I_L Store 3039 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 104 -I_L Persistent_GETS 214 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 8 -S_L Ifetch 0 <-- -S_L Store 13 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 2 -S_L Own_Lock_or_Unlock 0 <-- - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6400 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 11834 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2161 -IM_L Persistent_GETS 3947 -IM_L Own_Lock_or_Unlock 18584 -IM_L Request_Timeout 934 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 13 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 1 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12417 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22673 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4045 -IS_L Persistent_GETS 7418 -IS_L Own_Lock_or_Unlock 35854 -IS_L Request_Timeout 1843 - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 97890 -Ifetch 0 -Store 52462 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 14 -Data_All_Tokens 8893 -Ack 2 -Ack_All_Tokens 7 -Transient_GETX 0 -Transient_Local_GETX 21982 -Transient_GETS 0 -Transient_Local_GETS 40420 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25433 -Persistent_GETS 46779 -Own_Lock_or_Unlock 70150 -Request_Timeout 8995 -Use_TimeoutStarverX 59 -Use_TimeoutStarverS 91 -Use_TimeoutNoStarvers 8750 +Cache Stats: system.l1_cntrl6.L1DcacheMemory + system.l1_cntrl6.L1DcacheMemory_total_misses: 7125 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 5 -I Ifetch 0 <-- -I Store 3 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 - -S Load 1 -S Ifetch 0 <-- -S Store 3 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 5 -O Ifetch 0 <-- -O Store 7 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 1 -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 7 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 12 - -M Load 175 -M Ifetch 0 <-- -M Store 82 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 5 -M Persistent_GETS 20 -M Own_Lock_or_Unlock 77 - -MM Load 37311 -MM Ifetch 0 <-- -MM Store 19913 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3037 -MM Persistent_GETS 5688 -MM Own_Lock_or_Unlock 8062 - -M_W Load 10708 -M_W Ifetch 0 <-- -M_W Store 5706 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1629 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2878 -M_W Persistent_GETX 4 -M_W Persistent_GETS 2 -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 107 - -MM_W Load 43836 -MM_W Ifetch 0 <-- -MM_W Store 23674 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 974 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1682 -MM_W Persistent_GETX 55 -MM_W Persistent_GETS 89 -MM_W Own_Lock_or_Unlock 11 -MM_W Use_TimeoutStarverX 59 -MM_W Use_TimeoutStarverS 90 -MM_W Use_TimeoutNoStarvers 8643 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3069 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 245 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 389 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5601 -IM Persistent_GETS 10146 -IM Own_Lock_or_Unlock 2518 -IM Request_Timeout 2145 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 10 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 10 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 7 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 3 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 14 -IS Data_All_Tokens 5814 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 492 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 759 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10459 -IS Persistent_GETS 19532 -IS Own_Lock_or_Unlock 4832 -IS Request_Timeout 4014 - -I_L Load 5824 -I_L Ifetch 0 <-- -I_L Store 3055 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 151 -I_L Persistent_GETS 242 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 25 -S_L Ifetch 0 <-- -S_L Store 17 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 2 -S_L Own_Lock_or_Unlock 4 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6386 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12013 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2174 -IM_L Persistent_GETS 3820 -IM_L Own_Lock_or_Unlock 18801 -IM_L Request_Timeout 978 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 3 -SM_L Own_Lock_or_Unlock 17 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12235 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22698 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 3947 -IS_L Persistent_GETS 7235 -IS_L Own_Lock_or_Unlock 35814 -IS_L Request_Timeout 1858 - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 97464 -Ifetch 0 -Store 51982 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 21 -Data_All_Tokens 8881 -Ack 1 -Ack_All_Tokens 8 -Transient_GETX 0 -Transient_Local_GETX 21914 -Transient_GETS 0 -Transient_Local_GETS 40494 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25492 -Persistent_GETS 47155 -Own_Lock_or_Unlock 69715 -Request_Timeout 9514 -Use_TimeoutStarverX 78 -Use_TimeoutStarverS 164 -Use_TimeoutNoStarvers 8647 + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.6737% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.3263% - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 8 -I Ifetch 0 <-- -I Store 5 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 9 - -S Load 3 -S Ifetch 0 <-- -S Store 2 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 11 -O Ifetch 0 <-- -O Store 8 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 12 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 11 - -M Load 148 -M Ifetch 0 <-- -M Store 79 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 8 -M Persistent_GETS 13 -M Own_Lock_or_Unlock 65 - -MM Load 36904 -MM Ifetch 0 <-- -MM Store 19338 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3047 -MM Persistent_GETS 5579 -MM Own_Lock_or_Unlock 7946 - -M_W Load 10283 -M_W Ifetch 0 <-- -M_W Store 5634 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1545 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2924 -M_W Persistent_GETX 4 -M_W Persistent_GETS 13 -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 100 - -MM_W Load 44338 -MM_W Ifetch 0 <-- -MM_W Store 23776 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 908 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1759 -MM_W Persistent_GETX 73 -MM_W Persistent_GETS 147 -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 77 -MM_W Use_TimeoutStarverS 164 -MM_W Use_TimeoutNoStarvers 8547 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 1 -IM Data_All_Tokens 3142 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 232 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 444 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5658 -IM Persistent_GETS 10537 -IM Own_Lock_or_Unlock 2485 -IM Request_Timeout 2317 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 2 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 11 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 8 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 4 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 1 -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 1 -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 20 -IS Data_All_Tokens 5732 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 463 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 759 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10253 -IS Persistent_GETS 19299 -IS Own_Lock_or_Unlock 4569 -IS Request_Timeout 4269 - -I_L Load 5747 -I_L Ifetch 0 <-- -I_L Store 3129 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 140 -I_L Persistent_GETS 344 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 21 -S_L Ifetch 0 <-- -S_L Store 10 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 3 -S_L Own_Lock_or_Unlock 3 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 2 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6660 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12193 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2248 -IM_L Persistent_GETS 3909 -IM_L Own_Lock_or_Unlock 19321 -IM_L Request_Timeout 1049 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 11 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 3 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12078 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22413 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4061 -IS_L Persistent_GETS 7310 -IS_L Own_Lock_or_Unlock 35295 -IS_L Request_Timeout 1879 - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- + system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + +Cache Stats: system.l1_cntrl7.L1IcacheMemory + system.l1_cntrl7.L1IcacheMemory_total_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.L1DcacheMemory + system.l1_cntrl7.L1DcacheMemory_total_misses: 7125 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.2772% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.7228% + + system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 57015 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 57015 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 65.0916% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 34.9084% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 57015 100% + + --- L2Cache --- - Event Counts - -L1_GETS 46249 -L1_GETS_Last_Token 0 -L1_GETX 25069 -L1_INV 71135 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 0 -Writeback_Tokens 0 -Writeback_Shared_Data 0 -Writeback_All_Tokens 0 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 28628 -Persistent_GETS 52955 -Own_Lock_or_Unlock 60779 +L1_GETS [37112 ] 37112 +L1_GETS_Last_Token [0 ] 0 +L1_GETX [19903 ] 19903 +L1_INV [56964 ] 56964 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [0 ] 0 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [0 ] 0 +Writeback_All_Tokens [0 ] 0 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [22460 ] 22460 +Persistent_GETS [41771 ] 41771 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [49719 ] 49719 - Transitions - -NP L1_GETS 60 -NP L1_GETX 143 -NP L1_INV 78 -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 0 <-- -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 0 <-- -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 60779 - -I L1_GETS 0 <-- -I L1_GETS_Last_Token 0 <-- -I L1_GETX 0 <-- -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 0 <-- -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 0 <-- -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 0 <-- -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 0 <-- -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -I_L L1_GETS 46189 -I_L L1_GETX 24926 -I_L L1_INV 71057 -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 28628 -I_L Persistent_GETS 52955 -I_L Own_Lock_or_Unlock 0 <-- - -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +NP L1_GETS [26 ] 26 +NP L1_GETX [27 ] 27 +NP L1_INV [17 ] 17 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [0 ] 0 +NP Writeback_All_Tokens [0 ] 0 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [49719 ] 49719 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [0 ] 0 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [0 ] 0 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [0 ] 0 +S L1_GETX [0 ] 0 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [0 ] 0 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [0 ] 0 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [0 ] 0 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [37086 ] 37086 +I_L L1_GETX [19876 ] 19876 +I_L L1_INV [56947 ] 56947 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [22460 ] 22460 +I_L Persistent_GETS [41771 ] 41771 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -3197,215 +1058,278 @@ Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 25266 -GETS 46457 -Lockdown 81583 -Unlockdown 60779 -Own_Lock_or_Unlock 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack_Owner 0 -Ack_Owner_All_Tokens 0 -Tokens 0 -Ack_All_Tokens 0 -Request_Timeout 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [19962 ] 19962 +GETS [37458 ] 37458 +Lockdown [64231 ] 64231 +Unlockdown [49719 ] 49719 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack_Owner [0 ] 0 +Ack_Owner_All_Tokens [0 ] 0 +Tokens [0 ] 0 +Ack_All_Tokens [0 ] 0 +Request_Timeout [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 1 -O GETS 1 -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- - -NO GETX 200 -NO GETS 59 -NO Lockdown 60781 -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 0 <-- -NO Data_All_Tokens 0 <-- -NO Ack_Owner 0 <-- -NO Ack_Owner_All_Tokens 0 <-- -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -L GETX 24868 -L GETS 46189 -L Lockdown 20802 -L Unlockdown 60779 -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- - -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- - -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- - -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- - -NO_W GETX 197 -NO_W GETS 208 -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 2 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- - -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- - -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- - -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- - -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- - -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- - -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- - -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- - +O GETX [0 ] 0 +O GETS [2 ] 2 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [42 ] 42 +NO GETS [24 ] 24 +NO Lockdown [49719 ] 49719 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [0 ] 0 +NO Data_All_Tokens [0 ] 0 +NO Ack_Owner [0 ] 0 +NO Ack_Owner_All_Tokens [0 ] 0 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [19861 ] 19861 +L GETS [37086 ] 37086 +L Lockdown [14512 ] 14512 +L Unlockdown [49719 ] 49719 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [59 ] 59 +NO_W GETS [346 ] 346 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [2 ] 2 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens
\ No newline at end of file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index d78beb62f..36afc005b 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -1,74 +1,74 @@ -system.cpu2: completed 10000 read accesses @322194 -system.cpu0: completed 10000 read accesses @322719 -system.cpu5: completed 10000 read accesses @330050 -system.cpu7: completed 10000 read accesses @330574 -system.cpu6: completed 10000 read accesses @330892 -system.cpu4: completed 10000 read accesses @331172 -system.cpu1: completed 10000 read accesses @333911 -system.cpu3: completed 10000 read accesses @335019 -system.cpu0: completed 20000 read accesses @641579 -system.cpu2: completed 20000 read accesses @642932 -system.cpu6: completed 20000 read accesses @660969 -system.cpu4: completed 20000 read accesses @661309 -system.cpu5: completed 20000 read accesses @662083 -system.cpu7: completed 20000 read accesses @664047 -system.cpu1: completed 20000 read accesses @664884 -system.cpu3: completed 20000 read accesses @668081 -system.cpu0: completed 30000 read accesses @964302 -system.cpu2: completed 30000 read accesses @967590 -system.cpu4: completed 30000 read accesses @990023 -system.cpu7: completed 30000 read accesses @990043 -system.cpu6: completed 30000 read accesses @991961 -system.cpu5: completed 30000 read accesses @993160 -system.cpu1: completed 30000 read accesses @996431 -system.cpu3: completed 30000 read accesses @1001054 -system.cpu2: completed 40000 read accesses @1287629 -system.cpu0: completed 40000 read accesses @1291802 -system.cpu4: completed 40000 read accesses @1317065 -system.cpu7: completed 40000 read accesses @1322312 -system.cpu6: completed 40000 read accesses @1324580 -system.cpu5: completed 40000 read accesses @1326928 -system.cpu1: completed 40000 read accesses @1328485 -system.cpu3: completed 40000 read accesses @1330568 -system.cpu2: completed 50000 read accesses @1610807 -system.cpu0: completed 50000 read accesses @1611621 -system.cpu4: completed 50000 read accesses @1645302 -system.cpu7: completed 50000 read accesses @1650899 -system.cpu6: completed 50000 read accesses @1654396 -system.cpu5: completed 50000 read accesses @1657056 -system.cpu1: completed 50000 read accesses @1661586 -system.cpu3: completed 50000 read accesses @1662920 -system.cpu0: completed 60000 read accesses @1928533 -system.cpu2: completed 60000 read accesses @1935763 -system.cpu4: completed 60000 read accesses @1973168 -system.cpu7: completed 60000 read accesses @1985073 -system.cpu6: completed 60000 read accesses @1987312 -system.cpu1: completed 60000 read accesses @1992182 -system.cpu5: completed 60000 read accesses @1992692 -system.cpu3: completed 60000 read accesses @1994120 -system.cpu0: completed 70000 read accesses @2251425 -system.cpu2: completed 70000 read accesses @2258967 -system.cpu4: completed 70000 read accesses @2302588 -system.cpu6: completed 70000 read accesses @2314337 -system.cpu7: completed 70000 read accesses @2315937 -system.cpu5: completed 70000 read accesses @2322183 -system.cpu1: completed 70000 read accesses @2323330 -system.cpu3: completed 70000 read accesses @2326357 -system.cpu0: completed 80000 read accesses @2576249 -system.cpu2: completed 80000 read accesses @2582991 -system.cpu4: completed 80000 read accesses @2630111 -system.cpu6: completed 80000 read accesses @2644662 -system.cpu7: completed 80000 read accesses @2648201 -system.cpu1: completed 80000 read accesses @2650725 -system.cpu5: completed 80000 read accesses @2653106 -system.cpu3: completed 80000 read accesses @2653877 -system.cpu2: completed 90000 read accesses @2907948 -system.cpu0: completed 90000 read accesses @2917526 -system.cpu4: completed 90000 read accesses @2951732 -system.cpu6: completed 90000 read accesses @2969846 -system.cpu1: completed 90000 read accesses @2970686 -system.cpu3: completed 90000 read accesses @2978760 -system.cpu5: completed 90000 read accesses @2981622 -system.cpu7: completed 90000 read accesses @2987871 -system.cpu2: completed 100000 read accesses @3229931 +system.cpu0: completed 10000 read accesses @257947 +system.cpu1: completed 10000 read accesses @260311 +system.cpu3: completed 10000 read accesses @264703 +system.cpu7: completed 10000 read accesses @266036 +system.cpu5: completed 10000 read accesses @266378 +system.cpu4: completed 10000 read accesses @267169 +system.cpu2: completed 10000 read accesses @267625 +system.cpu6: completed 10000 read accesses @271366 +system.cpu0: completed 20000 read accesses @515410 +system.cpu1: completed 20000 read accesses @519078 +system.cpu7: completed 20000 read accesses @528562 +system.cpu3: completed 20000 read accesses @529556 +system.cpu5: completed 20000 read accesses @531753 +system.cpu4: completed 20000 read accesses @536204 +system.cpu6: completed 20000 read accesses @537031 +system.cpu2: completed 20000 read accesses @537314 +system.cpu0: completed 30000 read accesses @772994 +system.cpu1: completed 30000 read accesses @780923 +system.cpu3: completed 30000 read accesses @794263 +system.cpu7: completed 30000 read accesses @796675 +system.cpu4: completed 30000 read accesses @797063 +system.cpu5: completed 30000 read accesses @800026 +system.cpu2: completed 30000 read accesses @802601 +system.cpu6: completed 30000 read accesses @805267 +system.cpu0: completed 40000 read accesses @1033304 +system.cpu1: completed 40000 read accesses @1040457 +system.cpu3: completed 40000 read accesses @1058903 +system.cpu7: completed 40000 read accesses @1062178 +system.cpu5: completed 40000 read accesses @1064117 +system.cpu4: completed 40000 read accesses @1065423 +system.cpu6: completed 40000 read accesses @1066744 +system.cpu2: completed 40000 read accesses @1068649 +system.cpu0: completed 50000 read accesses @1292512 +system.cpu1: completed 50000 read accesses @1299935 +system.cpu3: completed 50000 read accesses @1324981 +system.cpu5: completed 50000 read accesses @1327818 +system.cpu7: completed 50000 read accesses @1328780 +system.cpu4: completed 50000 read accesses @1329164 +system.cpu6: completed 50000 read accesses @1332786 +system.cpu2: completed 50000 read accesses @1334645 +system.cpu0: completed 60000 read accesses @1550153 +system.cpu1: completed 60000 read accesses @1559435 +system.cpu7: completed 60000 read accesses @1591474 +system.cpu3: completed 60000 read accesses @1593078 +system.cpu4: completed 60000 read accesses @1594642 +system.cpu5: completed 60000 read accesses @1595392 +system.cpu2: completed 60000 read accesses @1600002 +system.cpu6: completed 60000 read accesses @1600595 +system.cpu0: completed 70000 read accesses @1802423 +system.cpu1: completed 70000 read accesses @1829858 +system.cpu7: completed 70000 read accesses @1853648 +system.cpu5: completed 70000 read accesses @1854214 +system.cpu3: completed 70000 read accesses @1854818 +system.cpu4: completed 70000 read accesses @1855726 +system.cpu6: completed 70000 read accesses @1868528 +system.cpu2: completed 70000 read accesses @1875446 +system.cpu0: completed 80000 read accesses @2061056 +system.cpu1: completed 80000 read accesses @2090957 +system.cpu7: completed 80000 read accesses @2119055 +system.cpu4: completed 80000 read accesses @2119432 +system.cpu5: completed 80000 read accesses @2121677 +system.cpu3: completed 80000 read accesses @2123217 +system.cpu6: completed 80000 read accesses @2133942 +system.cpu2: completed 80000 read accesses @2139530 +system.cpu0: completed 90000 read accesses @2322313 +system.cpu1: completed 90000 read accesses @2351193 +system.cpu4: completed 90000 read accesses @2382901 +system.cpu7: completed 90000 read accesses @2384445 +system.cpu5: completed 90000 read accesses @2387842 +system.cpu3: completed 90000 read accesses @2390630 +system.cpu6: completed 90000 read accesses @2400244 +system.cpu2: completed 90000 read accesses @2403389 +system.cpu0: completed 100000 read accesses @2583072 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 12db6638e..333832488 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:39:47 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:40:13 -M5 executing on phenom -command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token +M5 compiled Aug 20 2010 12:14:24 +M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates +M5 started Aug 20 2010 12:14:33 +M5 executing on SC2B0629 +command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3229931 because maximum number of loads reached +Exiting @ tick 2583072 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index aaeb05b60..a96eed002 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 332852 # Number of bytes of host memory used -host_seconds 26.21 # Real time elapsed on the host -host_tick_rate 123225 # Simulator tick rate (ticks/s) +host_mem_usage 341980 # Number of bytes of host memory used +host_seconds 25.58 # Real time elapsed on the host +host_tick_rate 100993 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003230 # Number of seconds simulated -sim_ticks 3229931 # Number of ticks simulated +sim_seconds 0.002583 # Number of seconds simulated +sim_ticks 2583072 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99664 # number of read accesses completed -system.cpu0.num_writes 53551 # number of write accesses completed +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 53663 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 97847 # number of read accesses completed -system.cpu1.num_writes 52926 # number of write accesses completed +system.cpu1.num_reads 98827 # number of read accesses completed +system.cpu1.num_writes 53487 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54081 # number of write accesses completed +system.cpu2.num_reads 96775 # number of read accesses completed +system.cpu2.num_writes 51846 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 97548 # number of read accesses completed -system.cpu3.num_writes 52843 # number of write accesses completed +system.cpu3.num_reads 97235 # number of read accesses completed +system.cpu3.num_writes 52295 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98335 # number of read accesses completed -system.cpu4.num_writes 52557 # number of write accesses completed +system.cpu4.num_reads 97597 # number of read accesses completed +system.cpu4.num_writes 52429 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97595 # number of read accesses completed -system.cpu5.num_writes 52679 # number of write accesses completed +system.cpu5.num_reads 97329 # number of read accesses completed +system.cpu5.num_writes 52105 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 97889 # number of read accesses completed -system.cpu6.num_writes 52461 # number of write accesses completed +system.cpu6.num_reads 96958 # number of read accesses completed +system.cpu6.num_writes 52281 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97463 # number of read accesses completed -system.cpu7.num_writes 51981 # number of write accesses completed +system.cpu7.num_reads 97500 # number of read accesses completed +system.cpu7.num_writes 52109 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 8cace1d25..1464a2cc5 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -5,13 +5,14 @@ dummy=0 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -129,6 +137,57 @@ trace_addr=0 functional=system.funcmem.port[7] test=system.ruby.cpu_ruby_ports7.port[0] +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + [system.funcmem] type=PhysicalMemory file= @@ -139,563 +198,554 @@ range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort - -[system.ruby] -type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports0] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.cpu_ruby_ports1] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.cpu_ruby_ports2] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.cpu_ruby_ports3] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.cpu_ruby_ports4] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.cpu_ruby_ports5] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.cpu_ruby_ports6] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.cpu_ruby_ports7] -type=RubySequencer -dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 -num_int_nodes=10 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] +[system.l1_cntrl0] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] +[system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] +[system.l1_cntrl1] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory +L2cacheMemory=system.l1_cntrl1.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] +[system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] +[system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] +[system.l1_cntrl1.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.l1_cntrl2] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory +L2cacheMemory=system.l1_cntrl2.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] +[system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] +[system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory] +[system.l1_cntrl2.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links3] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node -int_node=3 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links3.ext_node] +[system.l1_cntrl3] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory +L2cacheMemory=system.l1_cntrl3.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] +[system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] +[system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory] +[system.l1_cntrl3.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links4] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node -int_node=4 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links4.ext_node] +[system.l1_cntrl4] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory +L2cacheMemory=system.l1_cntrl4.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] +[system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] +[system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory] +[system.l1_cntrl4.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links5] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node -int_node=5 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links5.ext_node] +[system.l1_cntrl5] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory +L2cacheMemory=system.l1_cntrl5.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] +[system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] +[system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory] +[system.l1_cntrl5.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links6] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node -int_node=6 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links6.ext_node] +[system.l1_cntrl6] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory +L2cacheMemory=system.l1_cntrl6.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] +[system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] +[system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory] +[system.l1_cntrl6.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links7] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node -int_node=7 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links7.ext_node] +[system.l1_cntrl7] type=L1Cache_Controller children=L1DcacheMemory L1IcacheMemory L2cacheMemory -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory +L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory +L2cacheMemory=system.l1_cntrl7.L2cacheMemory buffer_size=0 -cache_response_latency=12 +cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] +[system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] +[system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -latency=3 +latency=2 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory] +[system.l1_cntrl7.L2cacheMemory] type=RubyCache assoc=2 -latency=15 +latency=10 replacement_policy=PSEUDO_LRU size=512 +start_index_bit=6 -[system.ruby.network.topology.ext_links8] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.l1_cntrl1.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.l1_cntrl2.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.l1_cntrl3.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.l1_cntrl4.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl4.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.l1_cntrl5.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl5.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.l1_cntrl6.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl6.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.l1_cntrl7.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl7.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 +num_int_nodes=10 +print_config=false + +[system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node -int_node=8 +ext_node=system.l1_cntrl0 +int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links8.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl1 +int_node=1 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links8.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl2 +int_node=2 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links8.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 +[system.ruby.network.topology.ext_links3] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl3 +int_node=3 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl4 +int_node=4 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links5] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl5 +int_node=5 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links6] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl6 +int_node=6 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links7] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl7 +int_node=7 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links8] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=8 +latency=1 +weight=1 [system.ruby.network.topology.int_links0] type=IntLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 5f070ae7c..dfe8adee6 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/01/2010 14:39:27 +Real time: Aug/20/2010 12:18:32 Profiler Stats -------------- -Elapsed_time_in_seconds: 32 -Elapsed_time_in_minutes: 0.533333 -Elapsed_time_in_hours: 0.00888889 -Elapsed_time_in_days: 0.00037037 +Elapsed_time_in_seconds: 37 +Elapsed_time_in_minutes: 0.616667 +Elapsed_time_in_hours: 0.0102778 +Elapsed_time_in_days: 0.000428241 -Virtual_time_in_seconds: 32.37 -Virtual_time_in_minutes: 0.5395 -Virtual_time_in_hours: 0.00899167 -Virtual_time_in_days: 0.000374653 +Virtual_time_in_seconds: 37.71 +Virtual_time_in_minutes: 0.6285 +Virtual_time_in_hours: 0.010475 +Virtual_time_in_days: 0.000436458 -Ruby_current_time: 4329426 +Ruby_current_time: 3305503 Ruby_start_time: 0 -Ruby_cycles: 4329426 +Ruby_cycles: 3305503 -mbytes_resident: 32.1484 -mbytes_total: 324.824 -resident_ratio: 0.0989838 +mbytes_resident: 32.625 +mbytes_total: 333.629 +resident_ratio: 0.0978 -ruby_cycles_executed: [ 4329427 4329427 4329427 4329427 4329427 4329427 4329427 4329427 ] +ruby_cycles_executed: [ 3305504 3305504 3305504 3305504 3305504 3305504 3305504 3305504 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,13 +66,31 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1217344 average: 1.9553 | standard deviation: 0.206639 | 0 54411 1162933 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1224677 average: 1.93738 | standard deviation: 0.24228 | 0 76690 1147987 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 16 max: 3117 count: 1217328 average: 54.8996 | standard deviation: 182.188 | 1062418 0 0 311 18298 68 401 7732 474 308 323 30614 240 267 3005 2219 254 546 21462 551 195 1076 3640 111 396 11292 946 204 417 4667 93 208 6265 158 167 149 5043 185 55 3548 197 160 3692 659 182 47 2461 384 73 2408 748 216 294 1630 503 61 1246 1085 74 108 1229 537 85 506 1072 74 67 1257 122 82 185 870 98 26 843 159 80 534 245 112 7 590 200 21 313 206 125 111 226 155 23 171 247 40 51 152 144 37 75 190 33 32 188 49 39 41 123 41 13 103 32 28 68 47 46 9 57 46 11 41 38 34 26 20 39 9 25 34 10 7 8 23 12 5 26 8 6 14 6 9 7 12 4 1 10 6 5 9 7 5 2 3 7 1 3 0 1 2 0 1 2 4 1 0 0 0 3 3 1 2 1 1 2 1 0 0 2 2 0 2 0 0 1 0 2 0 1 0 3 0 0 0 0 0 1 ] -miss_latency_2: [binsize: 16 max: 3017 count: 791763 average: 51.8282 | standard deviation: 176.682 | 696361 0 0 0 11763 0 0 4961 185 0 0 19895 35 0 1832 1425 8 44 13756 258 0 612 2313 2 16 7243 565 1 222 2975 5 5 3981 65 4 68 3212 39 2 2253 126 5 2376 378 46 1 1611 231 4 1523 465 103 153 1069 306 7 765 675 19 24 744 354 16 307 669 41 9 797 68 26 109 544 47 4 556 103 43 329 153 53 0 373 124 8 188 131 71 63 134 100 11 104 164 21 26 99 87 14 35 120 19 14 123 26 15 24 77 25 5 71 21 12 38 28 25 4 39 31 5 25 24 25 19 9 27 5 18 21 5 4 4 15 3 5 20 3 3 11 5 6 2 7 1 0 5 2 4 7 5 3 2 2 3 1 2 0 0 1 0 0 2 2 1 0 0 0 1 2 0 1 0 0 2 1 0 0 0 2 0 2 0 0 1 0 0 0 0 0 2 ] -miss_latency_3: [binsize: 16 max: 3117 count: 425565 average: 60.6139 | standard deviation: 191.881 | 366057 0 0 311 6535 68 401 2771 289 308 323 10719 205 267 1173 794 246 502 7706 293 195 464 1327 109 380 4049 381 203 195 1692 88 203 2284 93 163 81 1831 146 53 1295 71 155 1316 281 136 46 850 153 69 885 283 113 141 561 197 54 481 410 55 84 485 183 69 199 403 33 58 460 54 56 76 326 51 22 287 56 37 205 92 59 7 217 76 13 125 75 54 48 92 55 12 67 83 19 25 53 57 23 40 70 14 18 65 23 24 17 46 16 8 32 11 16 30 19 21 5 18 15 6 16 14 9 7 11 12 4 7 13 5 3 4 8 9 0 6 5 3 3 1 3 5 5 3 1 5 4 1 2 2 2 0 1 4 0 1 0 1 1 0 1 0 2 0 0 0 0 2 1 1 1 1 1 0 0 0 0 2 0 0 0 0 0 0 0 2 0 1 0 1 0 0 0 0 0 1 ] +miss_latency: [binsize: 4 max: 483 count: 1224663 average: 41.1802 | standard deviation: 90.1625 | 1000304 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7005 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 10 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 483 count: 795679 average: 22.1087 | standard deviation: 64.9617 | 711546 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 1 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4 max: 442 count: 428984 average: 76.5539 | standard deviation: 115.993 | 288758 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 1000304 average: 2 | standard deviation: 0 | 0 0 1000304 ] +miss_latency_Directory: [binsize: 2 max: 358 count: 2 average: 303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 4 max: 483 count: 224357 average: 215.864 | standard deviation: 83.754 | 0 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7004 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 2 count: 140230 average: 1.99996 | standard deviation: 0.00925064 | 3 0 140227 ] +miss_latency_wCC_initial_forward_request: [binsize: 4 max: 459 count: 140230 average: 203.958 | standard deviation: 78.4902 | 0 0 6212 20 98 67 95 140 250 0 0 1 1158 74 1037 220 349 551 1081 592 0 5 113 112 1635 2713 530 808 1650 3233 16 19 103 216 2099 6872 447 621 1222 4793 1914 74 320 1024 1743 7379 3458 282 513 2610 6341 300 767 1912 1837 6522 4902 99 141 770 6765 2933 1663 2774 3916 2940 3746 439 31 325 4465 13834 2498 2827 2733 1196 1565 289 2 23 232 2118 382 0 0 0 0 0 0 1 14 199 231 1 0 0 0 0 0 0 1 3 21 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 140230 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 140230 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 140230 average: 0.125494 | standard deviation: 0.335859 | 122846 17170 214 ] +imcomplete_wCC_Times: 84127 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 2 count: 2 average: 2 | standard deviation: 0 | 0 0 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 8 count: 2 average: 8 | standard deviation: 0 | 0 0 0 0 0 0 0 0 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 2 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 324 count: 2 average: 269 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 711546 average: 2 | standard deviation: 0 | 0 0 711546 ] +miss_latency_LD_Directory: [binsize: 2 max: 358 count: 2 average: 303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 483 count: 84131 average: 192.173 | standard deviation: 86.9918 | 0 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 0 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 288758 average: 2 | standard deviation: 0 | 0 0 288758 ] +miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 442 count: 140226 average: 230.078 | standard deviation: 78.3858 | 0 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -102,1893 +120,742 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 32 +user_time: 37 system_time: 0 -page_reclaims: 8443 +page_reclaims: 9470 page_faults: 0 swaps: 0 -block_inputs: 48 -block_outputs: 88 +block_inputs: 16 +block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 724737 5797896 +total_msg_count_Response_Data: 603819 43474968 +total_msg_count_Response_Control: 2526462 20211696 +total_msg_count_Broadcast_Control: 2103450 16827600 +total_msg_count_Unblock_Control: 673075 5384600 +total_msgs: 6631543 total_bytes: 91696760 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.251323 - links_utilized_percent_switch_0_link_0: 0.12279 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.379855 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 19278 1388016 [ 0 0 0 0 19278 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 116236 929888 [ 0 0 0 0 116236 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 135551 1084408 [ 0 0 0 135551 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 19361 154888 [ 0 0 19361 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 19330 1391760 [ 0 0 0 0 19330 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 116221 929768 [ 0 0 0 0 116221 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 19359 154872 [ 0 0 0 0 0 19359 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.346445 + links_utilized_percent_switch_0_link_0: 0.182474 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.510416 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 28166 225328 [ 0 0 28166 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 19532 1406304 [ 0 0 0 0 19532 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 105318 842544 [ 0 0 0 0 105318 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 28164 225312 [ 0 0 0 0 0 28164 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.251069 - links_utilized_percent_switch_1_link_0: 0.122725 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.379413 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 19261 1386792 [ 0 0 0 0 19261 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 116147 929176 [ 0 0 0 0 116147 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 135566 1084528 [ 0 0 0 135566 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 19346 154768 [ 0 0 19346 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 19284 1388448 [ 0 0 0 0 19284 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 116282 930256 [ 0 0 0 0 116282 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 19344 154752 [ 0 0 0 0 0 19344 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.345452 + links_utilized_percent_switch_1_link_0: 0.181714 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.50919 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 27960 223680 [ 0 0 27960 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 19481 1402632 [ 0 0 0 0 19481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 105379 843032 [ 0 0 0 0 105379 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 27958 223664 [ 0 0 0 0 0 27958 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.250795 - links_utilized_percent_switch_2_link_0: 0.122802 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.378788 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 19292 1389024 [ 0 0 0 0 19292 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 116138 929104 [ 0 0 0 0 116138 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 135563 1084504 [ 0 0 0 135563 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 19349 154792 [ 0 0 19349 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 19216 1383552 [ 0 0 0 0 19216 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 116347 930776 [ 0 0 0 0 116347 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 19347 154776 [ 0 0 0 0 0 19347 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.347269 + links_utilized_percent_switch_2_link_0: 0.182656 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.511881 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 28157 225256 [ 0 0 28157 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 19660 1415520 [ 0 0 0 0 19660 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 105153 841224 [ 0 0 0 0 105153 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 28155 225240 [ 0 0 0 0 0 28155 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.251498 - links_utilized_percent_switch_3_link_0: 0.123014 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.379982 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 19333 1391976 [ 0 0 0 0 19333 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 116572 932576 [ 0 0 0 0 116572 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 135495 1083960 [ 0 0 0 135495 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 19416 155328 [ 0 0 19416 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 19337 1392264 [ 0 0 0 0 19337 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 116158 929264 [ 0 0 0 0 116158 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 19414 155312 [ 0 0 0 0 0 19414 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.346043 + links_utilized_percent_switch_3_link_0: 0.181891 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.510195 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 27975 223800 [ 0 0 27975 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 19562 1408464 [ 0 0 0 0 19562 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 105284 842272 [ 0 0 0 0 105284 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 27973 223784 [ 0 0 0 0 0 27973 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.249848 - links_utilized_percent_switch_4_link_0: 0.12226 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.377437 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Response_Data: 19149 1378728 [ 0 0 0 0 19149 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 115426 923408 [ 0 0 0 0 115426 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 135685 1085480 [ 0 0 0 135685 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 19227 153816 [ 0 0 19227 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 19085 1374120 [ 0 0 0 0 19085 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 116600 932800 [ 0 0 0 0 116600 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 19225 153800 [ 0 0 0 0 0 19225 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.346195 + links_utilized_percent_switch_4_link_0: 0.182121 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.51027 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 28045 224360 [ 0 0 28045 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 19556 1408032 [ 0 0 0 0 19556 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 105248 841984 [ 0 0 0 0 105248 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 28043 224344 [ 0 0 0 0 0 28043 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.249997 - links_utilized_percent_switch_5_link_0: 0.122273 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.377721 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Response_Data: 19150 1378800 [ 0 0 0 0 19150 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 115467 923736 [ 0 0 0 0 115467 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 135679 1085432 [ 0 0 0 135679 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 19233 153864 [ 0 0 19233 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 19115 1376280 [ 0 0 0 0 19115 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 116564 932512 [ 0 0 0 0 116564 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 19231 153848 [ 0 0 0 0 0 19231 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.346499 + links_utilized_percent_switch_5_link_0: 0.181925 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.511074 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 27996 223968 [ 0 0 27996 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 19618 1412496 [ 0 0 0 0 19618 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 105319 842552 [ 0 0 0 0 105319 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 27994 223952 [ 0 0 0 0 0 27994 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.252646 - links_utilized_percent_switch_6_link_0: 0.12355 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.381742 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Response_Data: 19460 1401120 [ 0 0 0 0 19460 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 117425 939400 [ 0 0 0 0 117425 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 135355 1082840 [ 0 0 0 135355 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 19556 156448 [ 0 0 19556 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 19510 1404720 [ 0 0 0 0 19510 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 115845 926760 [ 0 0 0 0 115845 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 19554 156432 [ 0 0 0 0 0 19554 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.34662 + links_utilized_percent_switch_6_link_0: 0.182139 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.511101 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 28036 224288 [ 0 0 28036 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 19615 1412280 [ 0 0 0 0 19615 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 105283 842264 [ 0 0 0 0 105283 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 28035 224280 [ 0 0 0 0 0 28035 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.251885 - links_utilized_percent_switch_7_link_0: 0.123116 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.380653 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Response_Data: 19363 1394136 [ 0 0 0 0 19363 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 116675 933400 [ 0 0 0 0 116675 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 135476 1083808 [ 0 0 0 135476 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 19436 155488 [ 0 0 19436 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 19407 1397304 [ 0 0 0 0 19407 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 116069 928552 [ 0 0 0 0 116069 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 19434 155472 [ 0 0 0 0 0 19434 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.346674 + links_utilized_percent_switch_7_link_0: 0.182194 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.511154 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 28038 224304 [ 0 0 28038 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 19631 1413432 [ 0 0 0 0 19631 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 105170 841360 [ 0 0 0 0 105170 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 28037 224296 [ 0 0 0 0 0 28037 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.13419 - links_utilized_percent_switch_8_link_0: 0.0894553 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.178924 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.20393 + links_utilized_percent_switch_8_link_0: 0.169691 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.23817 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 154924 1239392 [ 0 0 154924 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 154908 1239264 [ 0 0 0 0 0 154908 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 17206 137648 [ 0 0 0 17206 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 154910 1239280 [ 0 0 0 154910 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 140230 1121840 [ 0 0 0 140230 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 0.476438 - links_utilized_percent_switch_9_link_0: 0.491161 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.490899 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.491207 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.492056 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.489039 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.48909 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.494199 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.492465 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.357821 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Response_Data: 19278 1388016 [ 0 0 0 0 19278 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 116236 929888 [ 0 0 0 0 116236 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Forwarded_Control: 135551 1084408 [ 0 0 0 135551 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 19261 1386792 [ 0 0 0 0 19261 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 116147 929176 [ 0 0 0 0 116147 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Forwarded_Control: 135566 1084528 [ 0 0 0 135566 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 19292 1389024 [ 0 0 0 0 19292 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 116138 929104 [ 0 0 0 0 116138 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Forwarded_Control: 135563 1084504 [ 0 0 0 135563 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 19333 1391976 [ 0 0 0 0 19333 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 116572 932576 [ 0 0 0 0 116572 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Forwarded_Control: 135495 1083960 [ 0 0 0 135495 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 19149 1378728 [ 0 0 0 0 19149 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 115426 923408 [ 0 0 0 0 115426 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Forwarded_Control: 135685 1085480 [ 0 0 0 135685 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 19150 1378800 [ 0 0 0 0 19150 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 115467 923736 [ 0 0 0 0 115467 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Forwarded_Control: 135679 1085432 [ 0 0 0 135679 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 19460 1401120 [ 0 0 0 0 19460 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 117425 939400 [ 0 0 0 0 117425 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Forwarded_Control: 135355 1082840 [ 0 0 0 135355 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 19363 1394136 [ 0 0 0 0 19363 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 116675 933400 [ 0 0 0 0 116675 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Forwarded_Control: 135476 1083808 [ 0 0 0 135476 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 154924 1239392 [ 0 0 154924 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 154908 1239264 [ 0 0 0 0 0 154908 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 19361 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 19361 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_type_LD: 61.4121% - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_type_ST: 38.5879% - - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19361 100% - system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19361 average: 1 | standard deviation: 0 | 0 19361 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 19361 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 19361 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 61.4121% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 38.5879% - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19361 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19361 average: 1 | standard deviation: 0 | 0 19361 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_9: 0.723025 + links_utilized_percent_switch_9_link_0: 0.729898 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.726855 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.730626 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.727564 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.728482 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.727702 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.728558 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.728777 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 0.678764 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 28166 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 28166 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 37.8364% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 62.1636% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 28166 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 28166 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 28166 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 37.8364% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 62.1636% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 28166 100% + + --- L1Cache --- - Event Counts - -Load 99344 -Ifetch 0 -Store 53020 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52037 -Other_GETS 83514 -Ack 115719 -Shared_Ack 517 -Data 275 -Shared_Data 698 -Exclusive_Data 18305 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 698 -All_acks_no_sharers 18661 +Load [99210 99376 100000 99219 99692 99063 99665 99458 ] 795683 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [53780 53529 53389 53948 53675 53375 53908 53390 ] 428994 +L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +Other_GETX [122682 122718 122712 122644 122719 122751 122647 122709 ] 981582 +Other_GETS [3 3 3 3 2 2 2 3 ] 21 +Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206 +Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +Invalidate [0 0 0 0 0 0 0 0 ] 0 +Ack [105371 105154 105165 105596 105154 104959 105564 105191 ] 842154 +Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +Data [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428 +Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 +Exclusive_Data [15418 15411 15413 15387 15339 15302 15409 15344 ] 123023 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 +All_acks_no_sharers [17544 17508 17514 17582 17508 17476 17580 17517 ] 140229 - Transitions - -I Load 11890 -I Ifetch 0 <-- -I Store 6416 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1247 -S Ifetch 0 <-- -S Store 677 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 21 -S Other_GETS 22 - -O Load 699 -O Ifetch 0 <-- -O Store 378 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 1 -O Other_GETS 2 - -M Load 19926 -M Ifetch 0 <-- -M Store 10584 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 227 -M Other_GETS 379 - -MM Load 65582 -MM Ifetch 0 <-- -MM Store 34965 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6807 -MM Other_GETS 11248 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17706 -IM Other_GETS 27589 -IM Ack 21983 -IM Data 203 -IM Exclusive_Data 7115 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 605 -SM Other_GETS 542 -SM Ack 227 -SM Data 72 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 297 -OM Other_GETS 369 -OM Ack 567 -OM All_acks 0 <-- -OM All_acks_no_sharers 81 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 752 -ISM All_acks_no_sharers 275 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33721 -M_W All_acks_no_sharers 11190 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21378 -MM_W All_acks_no_sharers 7115 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26373 -IS Other_GETS 43363 -IS Ack 35284 -IS Shared_Ack 271 -IS Data 0 <-- -IS Shared_Data 698 -IS Exclusive_Data 11190 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1807 -SS Shared_Ack 246 -SS All_acks 698 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 19346 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 19346 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_type_LD: 61.4442% - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_type_ST: 38.5558% - - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19346 100% - system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19346 average: 1 | standard deviation: 0 | 0 19346 ] - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 19346 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 19346 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_LD: 61.4442% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_ST: 38.5558% - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19346 100% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19346 average: 1 | standard deviation: 0 | 0 19346 ] - - --- L1Cache 1 --- - - Event Counts - -Load 98746 -Ifetch 0 -Store 53385 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52050 -Other_GETS 83516 -Ack 115650 -Shared_Ack 497 -Data 304 -Shared_Data 680 -Exclusive_Data 18277 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 680 -All_acks_no_sharers 18664 +I Load [10500 10487 10521 10455 10657 10484 10576 10457 ] 84137 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [5743 5634 5649 5815 5592 5753 5650 5790 ] 45626 +I L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +I L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +I Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +I Other_GETX [0 0 0 0 0 0 0 0 ] 0 +I Other_GETS [0 0 0 0 0 0 0 0 ] 0 +I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +I Invalidate [0 0 0 0 0 0 0 0 ] 0 + +S Load [18002 18238 18415 17804 18407 18155 18219 18081 ] 145321 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [9708 9676 9707 9635 9816 9635 9796 9625 ] 77598 +S L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +S L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +S Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +S Other_GETX [791 810 814 820 840 847 779 831 ] 6532 +S Other_GETS [0 0 0 0 0 0 0 0 ] 0 +S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +S Invalidate [0 0 0 0 0 0 0 0 ] 0 + +O Load [3730 3928 4020 4060 4122 3754 4001 3925 ] 31540 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [2094 2199 2159 2133 2101 2088 2135 2103 ] 17012 +O L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +O L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +O Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +O Other_GETX [25 17 24 21 28 19 29 31 ] 194 +O Other_GETS [0 0 0 0 0 0 0 0 ] 0 +O Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +O Invalidate [0 0 0 0 0 0 0 0 ] 0 + +M Load [0 0 0 0 1 1 1 0 ] 3 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [0 0 0 0 1 1 1 0 ] 3 +M L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +M L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +M Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +M Other_GETX [0 0 0 0 0 0 0 0 ] 0 +M Other_GETS [0 0 0 0 0 0 0 0 ] 0 +M Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +M Invalidate [0 0 0 0 0 0 0 0 ] 0 + +MM Load [66978 66723 67044 66900 66505 66669 66868 66995 ] 534682 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [36235 36020 35874 36365 36165 35898 36326 35872 ] 288755 +MM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MM Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +MM Other_GETX [15425 15292 15330 15427 15379 15368 15416 15383 ] 123020 +MM Other_GETS [0 0 0 0 0 1 0 0 ] 1 +MM Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206 +MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MM Invalidate [0 0 0 0 0 0 0 0 ] 0 + +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IM Other_GETX [61926 61585 61837 61982 61426 61580 61822 61858 ] 494016 +IM Other_GETS [0 0 1 0 0 0 0 2 ] 3 +IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IM Invalidate [0 0 0 0 0 0 0 0 ] 0 +IM Ack [50324 50375 50462 50772 50076 50008 49747 50687 ] 402451 +IM Data [1296 1262 1251 1350 1269 1317 1265 1314 ] 10324 +IM Exclusive_Data [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020 + +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +SM Other_GETX [8985 8947 8938 8894 9021 8880 8974 8855 ] 71494 +SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +SM Invalidate [0 0 0 0 0 0 0 0 ] 0 +SM Ack [2116 2161 2439 2130 2490 2249 2469 2247 ] 18301 +SM Data [723 729 769 741 795 755 822 770 ] 6104 + +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OM Other_GETX [1987 2093 2078 2029 1996 1986 2051 2014 ] 16234 +OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OM Invalidate [0 0 0 0 0 0 0 0 ] 0 +OM Ack [749 742 567 728 735 714 588 623 ] 5446 +OM All_acks [0 0 0 0 0 0 0 0 ] 0 +OM All_acks_no_sharers [107 106 81 104 105 102 84 89 ] 778 + +ISM Load [0 0 0 0 0 0 0 0 ] 0 +ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 +ISM Store [0 0 0 0 0 0 0 0 ] 0 +ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +ISM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +ISM Ack [6059 6066 6055 6411 6149 6074 6336 6177 ] 49327 +ISM All_acks_no_sharers [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428 + +M_W Load [0 0 0 0 0 0 0 0 ] 0 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [0 0 0 0 0 0 0 0 ] 0 +M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +M_W Ack [0 0 0 0 0 0 1 0 ] 1 +M_W All_acks_no_sharers [0 0 0 0 1 1 1 0 ] 3 + +MM_W Load [0 0 0 0 0 0 0 0 ] 0 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [0 0 0 0 0 0 0 0 ] 0 +MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MM_W Ack [46123 45810 45642 45555 45697 45907 46418 45457 ] 366609 +MM_W All_acks_no_sharers [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020 + +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IS Other_GETX [33543 33974 33691 33471 34029 34071 33576 33737 ] 270092 +IS Other_GETS [3 3 2 3 2 1 2 1 ] 17 +IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IS Invalidate [0 0 0 0 0 0 0 0 ] 0 +IS Ack [0 0 0 0 7 7 5 0 ] 19 +IS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +IS Data [0 0 0 0 0 0 0 0 ] 0 +IS Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 +IS Exclusive_Data [0 0 0 0 1 1 1 0 ] 3 + +SS Load [0 0 0 0 0 0 0 0 ] 0 +SS Ifetch [0 0 0 0 0 0 0 0 ] 0 +SS Store [0 0 0 0 0 0 0 0 ] 0 +SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +SS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +SS Ack [0 0 0 0 0 0 0 0 ] 0 +SS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +SS All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 +SS All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 + +OI Load [0 0 0 0 0 0 0 0 ] 0 +OI Ifetch [0 0 0 0 0 0 0 0 ] 0 +OI Store [0 0 0 0 0 0 0 0 ] 0 +OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETX [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OI Invalidate [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 + +MI Load [0 0 0 0 0 0 0 0 ] 0 +MI Ifetch [0 0 0 0 0 0 0 0 ] 0 +MI Store [0 0 0 0 0 0 0 0 ] 0 +MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MI Invalidate [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 + +II Load [0 0 0 0 0 0 0 0 ] 0 +II Ifetch [0 0 0 0 0 0 0 0 ] 0 +II Store [0 0 0 0 0 0 0 0 ] 0 +II L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +II L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +II Other_GETX [0 0 0 0 0 0 0 0 ] 0 +II Other_GETS [0 0 0 0 0 0 0 0 ] 0 +II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +II Invalidate [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 + +IT Load [0 0 0 0 0 0 0 0 ] 0 +IT Ifetch [0 0 0 0 0 0 0 0 ] 0 +IT Store [0 0 0 0 0 0 0 0 ] 0 +IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +IT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IT Invalidate [0 0 0 0 0 0 0 0 ] 0 + +ST Load [0 0 0 0 0 0 0 0 ] 0 +ST Ifetch [0 0 0 0 0 0 0 0 ] 0 +ST Store [0 0 0 0 0 0 0 0 ] 0 +ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +ST L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +ST Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETX [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETS [0 0 0 0 0 0 0 0 ] 0 +ST Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +ST Invalidate [0 0 0 0 0 0 0 0 ] 0 + +OT Load [0 0 0 0 0 0 0 0 ] 0 +OT Ifetch [0 0 0 0 0 0 0 0 ] 0 +OT Store [0 0 0 0 0 0 0 0 ] 0 +OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OT Invalidate [0 0 0 0 0 0 0 0 ] 0 + +MT Load [0 0 0 0 0 0 0 0 ] 0 +MT Ifetch [0 0 0 0 0 0 0 0 ] 0 +MT Store [0 0 0 0 0 0 0 0 ] 0 +MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MT Invalidate [0 0 0 0 0 0 0 0 ] 0 + +MMT Load [0 0 0 0 0 0 0 0 ] 0 +MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 +MMT Store [0 0 0 0 0 0 0 0 ] 0 +MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MMT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MMT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MMT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MMT Invalidate [0 0 0 0 0 0 0 0 ] 0 + +Cache Stats: system.l1_cntrl1.L1IcacheMemory + system.l1_cntrl1.L1IcacheMemory_total_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl1.L1DcacheMemory + system.l1_cntrl1.L1DcacheMemory_total_misses: 27960 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 27960 + system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 37.4964% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 62.5036% + + system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 27960 100% + +Cache Stats: system.l1_cntrl1.L2cacheMemory + system.l1_cntrl1.L2cacheMemory_total_misses: 27960 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 27960 + system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl1.L2cacheMemory_request_type_LD: 37.4964% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 62.5036% + + system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode: 27960 100% + +Cache Stats: system.l1_cntrl2.L1IcacheMemory + system.l1_cntrl2.L1IcacheMemory_total_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.L1DcacheMemory + system.l1_cntrl2.L1DcacheMemory_total_misses: 28157 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 28157 + system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 37.5608% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 62.4392% + + system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 28157 100% + +Cache Stats: system.l1_cntrl2.L2cacheMemory + system.l1_cntrl2.L2cacheMemory_total_misses: 28157 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 28157 + system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl2.L2cacheMemory_request_type_LD: 37.5608% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 62.4392% + + system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode: 28157 100% + +Cache Stats: system.l1_cntrl3.L1IcacheMemory + system.l1_cntrl3.L1IcacheMemory_total_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.L1DcacheMemory + system.l1_cntrl3.L1DcacheMemory_total_misses: 27975 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 27975 + system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 37.3798% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 62.6202% + + system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 27975 100% + +Cache Stats: system.l1_cntrl3.L2cacheMemory + system.l1_cntrl3.L2cacheMemory_total_misses: 27975 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 27975 + system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl3.L2cacheMemory_request_type_LD: 37.3798% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 62.6202% + + system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode: 27975 100% + +Cache Stats: system.l1_cntrl4.L1IcacheMemory + system.l1_cntrl4.L1IcacheMemory_total_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 11887 -I Ifetch 0 <-- -I Store 6432 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1220 -S Ifetch 0 <-- -S Store 661 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 19 -S Other_GETS 15 - -O Load 681 -O Ifetch 0 <-- -O Store 366 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 1 - -M Load 20150 -M Ifetch 0 <-- -M Store 10628 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 210 -M Other_GETS 368 - -MM Load 64808 -MM Ifetch 0 <-- -MM Store 35298 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6880 -MM Other_GETS 11206 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17173 -IM Other_GETS 26846 -IM Ack 21762 -IM Data 215 -IM Exclusive_Data 7071 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 572 -SM Other_GETS 527 -SM Ack 242 -SM Data 89 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 283 -OM Other_GETS 334 -OM Ack 581 -OM All_acks 0 <-- -OM All_acks_no_sharers 83 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 963 -ISM All_acks_no_sharers 304 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33742 -M_W All_acks_no_sharers 11206 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21283 -MM_W All_acks_no_sharers 7071 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26911 -IS Other_GETS 44219 -IS Ack 35249 -IS Shared_Ack 242 -IS Data 0 <-- -IS Shared_Data 680 -IS Exclusive_Data 11206 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1828 -SS Shared_Ack 255 -SS All_acks 680 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 19349 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 19349 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_type_LD: 61.3417% - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_type_ST: 38.6583% - - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19349 100% - system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19349 average: 1 | standard deviation: 0 | 0 19349 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_misses: 19349 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_demand_misses: 19349 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_LD: 61.3417% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_ST: 38.6583% - - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19349 100% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19349 average: 1 | standard deviation: 0 | 0 19349 ] - - --- L1Cache 2 --- - - Event Counts - -Load 98624 -Ifetch 0 -Store 53315 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52030 -Other_GETS 83533 -Ack 115623 -Shared_Ack 515 -Data 272 -Shared_Data 719 -Exclusive_Data 18301 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 719 -All_acks_no_sharers 18628 - - Transitions - -I Load 11869 -I Ifetch 0 <-- -I Store 6439 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1254 -S Ifetch 0 <-- -S Store 699 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 20 -S Other_GETS 18 - -O Load 672 -O Ifetch 0 <-- -O Store 342 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 1 - -M Load 19515 -M Ifetch 0 <-- -M Store 10604 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 202 -M Other_GETS 344 - -MM Load 65314 -MM Ifetch 0 <-- -MM Store 35231 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6815 -MM Other_GETS 11267 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17023 -IM Other_GETS 26686 -IM Ack 22228 -IM Data 199 -IM Exclusive_Data 7151 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 626 -SM Other_GETS 536 -SM Ack 221 -SM Data 73 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 286 -OM Other_GETS 299 -OM Ack 385 -OM All_acks 0 <-- -OM All_acks_no_sharers 55 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 823 -ISM All_acks_no_sharers 272 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33805 -M_W All_acks_no_sharers 11150 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21267 -MM_W All_acks_no_sharers 7151 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27056 -IS Other_GETS 44382 -IS Ack 35091 -IS Shared_Ack 273 -IS Data 0 <-- -IS Shared_Data 719 -IS Exclusive_Data 11150 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1803 -SS Shared_Ack 242 -SS All_acks 719 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 19416 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 19416 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_type_LD: 61.9077% - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_type_ST: 38.0923% - - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19416 100% - system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19416 average: 1 | standard deviation: 0 | 0 19416 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_misses: 19416 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_demand_misses: 19416 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_LD: 61.9077% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_ST: 38.0923% - - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19416 100% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19416 average: 1 | standard deviation: 0 | 0 19416 ] - - --- L1Cache 3 --- - - Event Counts - -Load 99275 -Ifetch 0 -Store 53327 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52112 -Other_GETS 83383 -Ack 116023 -Shared_Ack 549 -Data 281 -Shared_Data 715 -Exclusive_Data 18337 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 715 -All_acks_no_sharers 18700 +Cache Stats: system.l1_cntrl4.L1DcacheMemory + system.l1_cntrl4.L1DcacheMemory_total_misses: 28045 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 28045 + system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 12020 -I Ifetch 0 <-- -I Store 6330 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1337 -S Ifetch 0 <-- -S Store 692 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 22 -S Other_GETS 24 - -O Load 652 -O Ifetch 0 <-- -O Store 374 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 1 -O Other_GETS 1 - -M Load 19894 -M Ifetch 0 <-- -M Store 10721 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 208 -M Other_GETS 375 - -MM Load 65372 -MM Ifetch 0 <-- -MM Store 35210 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6827 -MM Other_GETS 11290 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 16735 -IM Other_GETS 26100 -IM Ack 21436 -IM Data 174 -IM Exclusive_Data 7033 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 585 -SM Other_GETS 551 -SM Ack 310 -SM Data 107 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 292 -OM Other_GETS 343 -OM Ack 574 -OM All_acks 0 <-- -OM All_acks_no_sharers 82 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 887 -ISM All_acks_no_sharers 281 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 34315 -M_W All_acks_no_sharers 11304 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21251 -MM_W All_acks_no_sharers 7033 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27442 -IS Other_GETS 44699 -IS Ack 35339 -IS Shared_Ack 289 -IS Data 0 <-- -IS Shared_Data 715 -IS Exclusive_Data 11304 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1911 -SS Shared_Ack 260 -SS All_acks 715 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 19227 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 19227 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_type_LD: 61.6269% - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_type_ST: 38.3731% - - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19227 100% - system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19227 average: 1 | standard deviation: 0 | 0 19227 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_misses: 19227 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_demand_misses: 19227 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_LD: 61.6269% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_ST: 38.3731% - - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19227 100% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19227 average: 1 | standard deviation: 0 | 0 19227 ] - - --- L1Cache 4 --- - - Event Counts - -Load 98085 -Ifetch 0 -Store 52520 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52130 -Other_GETS 83555 -Ack 114858 -Shared_Ack 568 -Data 293 -Shared_Data 735 -Exclusive_Data 18121 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 735 -All_acks_no_sharers 18490 + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 37.4398% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 62.5602% - - Transitions - -I Load 11849 -I Ifetch 0 <-- -I Store 6303 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1289 -S Ifetch 0 <-- -S Store 724 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 11 -S Other_GETS 20 - -O Load 650 -O Ifetch 0 <-- -O Store 351 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- - -M Load 19521 -M Ifetch 0 <-- -M Store 10542 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 219 -M Other_GETS 351 - -MM Load 64776 -MM Ifetch 0 <-- -MM Store 34600 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6837 -MM Other_GETS 11083 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17328 -IM Other_GETS 27038 -IM Ack 21720 -IM Data 204 -IM Exclusive_Data 7009 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 635 -SM Other_GETS 551 -SM Ack 280 -SM Data 89 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 275 -OM Other_GETS 320 -OM Ack 532 -OM All_acks 0 <-- -OM All_acks_no_sharers 76 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 903 -ISM All_acks_no_sharers 293 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33570 -M_W All_acks_no_sharers 11112 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 20909 -MM_W All_acks_no_sharers 7009 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26825 -IS Other_GETS 44192 -IS Ack 35093 -IS Shared_Ack 270 -IS Data 0 <-- -IS Shared_Data 735 -IS Exclusive_Data 11112 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1851 -SS Shared_Ack 298 -SS All_acks 735 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 19233 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 19233 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_type_LD: 61.2905% - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_type_ST: 38.7095% - - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19233 100% - system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19233 average: 1 | standard deviation: 0 | 0 19233 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_misses: 19233 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_demand_misses: 19233 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_LD: 61.2905% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_ST: 38.7095% - - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19233 100% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19233 average: 1 | standard deviation: 0 | 0 19233 ] - - --- L1Cache 5 --- - - Event Counts - -Load 98307 -Ifetch 0 -Store 52894 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52064 -Other_GETS 83615 -Ack 114896 -Shared_Ack 571 -Data 297 -Shared_Data 704 -Exclusive_Data 18149 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 704 -All_acks_no_sharers 18527 + system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 28045 100% - - Transitions - -I Load 11788 -I Ifetch 0 <-- -I Store 6422 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1309 -S Ifetch 0 <-- -S Store 680 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 24 -S Other_GETS 13 - -O Load 594 -O Ifetch 0 <-- -O Store 343 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 3 - -M Load 19300 -M Ifetch 0 <-- -M Store 10530 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 210 -M Other_GETS 343 - -MM Load 65316 -MM Ifetch 0 <-- -MM Store 34919 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6792 -MM Other_GETS 11182 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17452 -IM Other_GETS 27344 -IM Ack 21879 -IM Data 217 -IM Exclusive_Data 7066 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 600 -SM Other_GETS 459 -SM Ack 226 -SM Data 80 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 262 -OM Other_GETS 323 -OM Ack 567 -OM All_acks 0 <-- -OM All_acks_no_sharers 81 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 939 -ISM All_acks_no_sharers 297 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 32853 -M_W All_acks_no_sharers 11083 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21134 -MM_W All_acks_no_sharers 7066 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26724 -IS Other_GETS 43948 -IS Ack 35479 -IS Shared_Ack 299 -IS Data 0 <-- -IS Shared_Data 704 -IS Exclusive_Data 11083 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1819 -SS Shared_Ack 272 -SS All_acks 704 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 19556 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 19556 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_type_LD: 61.9043% - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_type_ST: 38.0957% - - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19556 100% - system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19556 average: 1 | standard deviation: 0 | 0 19556 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_misses: 19556 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_demand_misses: 19556 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_LD: 61.9043% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_ST: 38.0957% - - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19556 100% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19556 average: 1 | standard deviation: 0 | 0 19556 ] - - --- L1Cache 6 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 53622 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52058 -Other_GETS 83297 -Ack 116891 -Shared_Ack 534 -Data 300 -Shared_Data 669 -Exclusive_Data 18491 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 669 -All_acks_no_sharers 18886 +Cache Stats: system.l1_cntrl4.L2cacheMemory + system.l1_cntrl4.L2cacheMemory_total_misses: 28045 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 28045 + system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 12106 -I Ifetch 0 <-- -I Store 6420 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1090 -S Ifetch 0 <-- -S Store 653 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 16 -S Other_GETS 11 - -O Load 632 -O Ifetch 0 <-- -O Store 377 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 3 - -M Load 20362 -M Ifetch 0 <-- -M Store 10812 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 246 -M Other_GETS 377 - -MM Load 65811 -MM Ifetch 0 <-- -MM Store 35360 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 7016 -MM Other_GETS 11246 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 16702 -IM Other_GETS 26259 -IM Ack 21931 -IM Data 211 -IM Exclusive_Data 7055 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 564 -SM Other_GETS 502 -SM Ack 236 -SM Data 89 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 282 -OM Other_GETS 340 -OM Ack 665 -OM All_acks 0 <-- -OM All_acks_no_sharers 95 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 947 -ISM All_acks_no_sharers 300 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33907 -M_W All_acks_no_sharers 11436 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21016 -MM_W All_acks_no_sharers 7055 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27232 -IS Other_GETS 44559 -IS Ack 36431 -IS Shared_Ack 278 -IS Data 0 <-- -IS Shared_Data 669 -IS Exclusive_Data 11436 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1758 -SS Shared_Ack 256 -SS All_acks 669 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 19436 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 19436 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_type_LD: 61.7514% - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_type_ST: 38.2486% - - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19436 100% - system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19436 average: 1 | standard deviation: 0 | 0 19436 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_misses: 19436 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_demand_misses: 19436 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_LD: 61.7514% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_ST: 38.2486% - - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19436 100% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19436 average: 1 | standard deviation: 0 | 0 19436 ] - - --- L1Cache 7 --- - - Event Counts - -Load 99390 -Ifetch 0 -Store 53487 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52075 -Other_GETS 83401 -Ack 116123 -Shared_Ack 552 -Data 278 -Shared_Data 688 -Exclusive_Data 18397 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 688 -All_acks_no_sharers 18746 + system.l1_cntrl4.L2cacheMemory_request_type_LD: 37.4398% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 62.5602% - - Transitions - -I Load 12002 -I Ifetch 0 <-- -I Store 6376 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1285 -S Ifetch 0 <-- -S Store 672 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 16 -S Other_GETS 26 - -O Load 736 -O Ifetch 0 <-- -O Store 386 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 2 - -M Load 19905 -M Ifetch 0 <-- -M Store 10715 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 210 -M Other_GETS 388 - -MM Load 65462 -MM Ifetch 0 <-- -MM Store 35338 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6877 -MM Other_GETS 11271 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17167 -IM Other_GETS 26381 -IM Ack 21891 -IM Data 204 -IM Exclusive_Data 7084 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 598 -SM Other_GETS 486 -SM Ack 234 -SM Data 74 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 315 -OM Other_GETS 342 -OM Ack 497 -OM All_acks 0 <-- -OM All_acks_no_sharers 71 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 785 -ISM All_acks_no_sharers 278 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33978 -M_W All_acks_no_sharers 11313 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21262 -MM_W All_acks_no_sharers 7084 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26890 -IS Other_GETS 44505 -IS Ack 35618 -IS Shared_Ack 274 -IS Data 0 <-- -IS Shared_Data 688 -IS Exclusive_Data 11313 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1858 -SS Shared_Ack 278 -SS All_acks 688 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: + system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode: 28045 100% + +Cache Stats: system.l1_cntrl5.L1IcacheMemory + system.l1_cntrl5.L1IcacheMemory_total_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.L1DcacheMemory + system.l1_cntrl5.L1DcacheMemory_total_misses: 27996 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 27996 + system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 37.4589% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 62.5411% + + system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 27996 100% + +Cache Stats: system.l1_cntrl5.L2cacheMemory + system.l1_cntrl5.L2cacheMemory_total_misses: 27996 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 27996 + system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl5.L2cacheMemory_request_type_LD: 37.4589% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 62.5411% + + system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode: 27996 100% + +Cache Stats: system.l1_cntrl6.L1IcacheMemory + system.l1_cntrl6.L1IcacheMemory_total_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.L1DcacheMemory + system.l1_cntrl6.L1DcacheMemory_total_misses: 28036 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 28036 + system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 37.5268% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 62.4732% + + system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 28036 100% + +Cache Stats: system.l1_cntrl6.L2cacheMemory + system.l1_cntrl6.L2cacheMemory_total_misses: 28036 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 28036 + system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl6.L2cacheMemory_request_type_LD: 37.5268% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 62.4732% + + system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode: 28036 100% + +Cache Stats: system.l1_cntrl7.L1IcacheMemory + system.l1_cntrl7.L1IcacheMemory_total_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.L1DcacheMemory + system.l1_cntrl7.L1DcacheMemory_total_misses: 28038 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 28038 + system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 37.2887% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 62.7113% + + system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 28038 100% + +Cache Stats: system.l1_cntrl7.L2cacheMemory + system.l1_cntrl7.L2cacheMemory_total_misses: 28038 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 28038 + system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl7.L2cacheMemory_request_type_LD: 37.2887% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 62.7113% + + system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode: 28038 100% + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -2008,178 +875,282 @@ Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 2249313 -GETS 3541903 -PUT 0 -Unblock 154908 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 0 -Writeback_Exclusive_Dirty 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 2 -Memory_Ack 0 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [829725 ] 829725 +GETS [354236 ] 354236 +PUT [0 ] 0 +Unblock [0 ] 0 +UnblockS [84130 ] 84130 +UnblockM [140228 ] 140228 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [0 ] 0 +Writeback_Exclusive_Dirty [0 ] 0 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [17206 ] 17206 - Transitions - -NO GETX 59507 -NO GETS 95401 -NO PUT 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -E GETX 1 -E GETS 1 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- - -NO_B GETX 2189606 -NO_B GETS 3446289 -NO_B PUT 0 <-- -NO_B Unblock 154908 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- - -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- - -NO_B_W GETX 199 -NO_B_W GETS 212 -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 2 - -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- - -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- - -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- - -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- - -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- - -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- - -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- - -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- - -WB GETX 0 <-- -WB GETS 0 <-- -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 0 <-- -WB Writeback_Exclusive_Dirty 0 <-- -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- - -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- - -WB_E_W GETX 0 <-- -WB_E_W GETS 0 <-- -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 0 <-- - +NX GETX [17206 ] 17206 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 + +NO GETX [123021 ] 123021 +NO GETS [1 ] 1 +NO PUT [0 ] 0 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +E GETX [0 ] 0 +E GETS [2 ] 2 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 + +NO_B GETX [123022 ] 123022 +NO_B GETS [17206 ] 17206 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [2 ] 2 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 + +NO_B_X GETX [468040 ] 468040 +NO_B_X GETS [270091 ] 270091 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [123020 ] 123020 +NO_B_X Pf_Replacement [0 ] 0 + +NO_B_S GETX [36312 ] 36312 +NO_B_S GETS [66924 ] 66924 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [17206 ] 17206 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 + +NO_B_S_W GETX [62122 ] 62122 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [84130 ] 84130 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [17206 ] 17206 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 + +NO_B_W GETX [2 ] 2 +NO_B_W GETS [12 ] 12 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [2 ] 2 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [0 ] 0 +WB GETS [0 ] 0 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [0 ] 0 +WB Writeback_Exclusive_Dirty [0 ] 0 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [0 ] 0 +WB_E_W GETS [0 ] 0 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 4ad631c35..1aa1be599 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @427588 -system.cpu7: completed 10000 read accesses @431412 -system.cpu2: completed 10000 read accesses @431662 -system.cpu0: completed 10000 read accesses @436404 -system.cpu6: completed 10000 read accesses @437826 -system.cpu3: completed 10000 read accesses @441295 -system.cpu4: completed 10000 read accesses @446537 -system.cpu1: completed 10000 read accesses @454121 -system.cpu6: completed 20000 read accesses @860243 -system.cpu5: completed 20000 read accesses @863931 -system.cpu0: completed 20000 read accesses @870865 -system.cpu7: completed 20000 read accesses @874151 -system.cpu2: completed 20000 read accesses @878670 -system.cpu1: completed 20000 read accesses @880979 -system.cpu3: completed 20000 read accesses @881568 -system.cpu4: completed 20000 read accesses @885967 -system.cpu6: completed 30000 read accesses @1296805 -system.cpu7: completed 30000 read accesses @1298533 -system.cpu0: completed 30000 read accesses @1301793 -system.cpu5: completed 30000 read accesses @1305764 -system.cpu3: completed 30000 read accesses @1313209 -system.cpu1: completed 30000 read accesses @1317956 -system.cpu4: completed 30000 read accesses @1322397 -system.cpu2: completed 30000 read accesses @1327680 -system.cpu7: completed 40000 read accesses @1724327 -system.cpu6: completed 40000 read accesses @1741883 -system.cpu3: completed 40000 read accesses @1743341 -system.cpu0: completed 40000 read accesses @1746338 -system.cpu5: completed 40000 read accesses @1749918 -system.cpu4: completed 40000 read accesses @1756944 -system.cpu1: completed 40000 read accesses @1758785 -system.cpu2: completed 40000 read accesses @1766923 -system.cpu7: completed 50000 read accesses @2153101 -system.cpu3: completed 50000 read accesses @2174455 -system.cpu6: completed 50000 read accesses @2175676 -system.cpu0: completed 50000 read accesses @2176642 -system.cpu1: completed 50000 read accesses @2195626 -system.cpu5: completed 50000 read accesses @2196192 -system.cpu4: completed 50000 read accesses @2206329 -system.cpu2: completed 50000 read accesses @2212172 -system.cpu7: completed 60000 read accesses @2597994 -system.cpu3: completed 60000 read accesses @2607264 -system.cpu6: completed 60000 read accesses @2608871 -system.cpu0: completed 60000 read accesses @2617931 -system.cpu1: completed 60000 read accesses @2626417 -system.cpu5: completed 60000 read accesses @2627919 -system.cpu2: completed 60000 read accesses @2649345 -system.cpu4: completed 60000 read accesses @2649516 -system.cpu7: completed 70000 read accesses @3041950 -system.cpu6: completed 70000 read accesses @3046421 -system.cpu3: completed 70000 read accesses @3055853 -system.cpu0: completed 70000 read accesses @3057789 -system.cpu1: completed 70000 read accesses @3060703 -system.cpu5: completed 70000 read accesses @3069601 -system.cpu4: completed 70000 read accesses @3076345 -system.cpu2: completed 70000 read accesses @3079487 -system.cpu7: completed 80000 read accesses @3472996 -system.cpu6: completed 80000 read accesses @3475066 -system.cpu3: completed 80000 read accesses @3481511 -system.cpu0: completed 80000 read accesses @3498566 -system.cpu1: completed 80000 read accesses @3506662 -system.cpu2: completed 80000 read accesses @3515589 -system.cpu5: completed 80000 read accesses @3522207 -system.cpu4: completed 80000 read accesses @3524696 -system.cpu6: completed 90000 read accesses @3905962 -system.cpu7: completed 90000 read accesses @3913222 -system.cpu3: completed 90000 read accesses @3920060 -system.cpu0: completed 90000 read accesses @3930216 -system.cpu2: completed 90000 read accesses @3948853 -system.cpu1: completed 90000 read accesses @3953559 -system.cpu5: completed 90000 read accesses @3960654 -system.cpu4: completed 90000 read accesses @3965634 -system.cpu6: completed 100000 read accesses @4329426 +system.cpu2: completed 10000 read accesses @332309 +system.cpu0: completed 10000 read accesses @332762 +system.cpu3: completed 10000 read accesses @333275 +system.cpu7: completed 10000 read accesses @334660 +system.cpu4: completed 10000 read accesses @336400 +system.cpu6: completed 10000 read accesses @336827 +system.cpu1: completed 10000 read accesses @336833 +system.cpu5: completed 10000 read accesses @339345 +system.cpu3: completed 20000 read accesses @659139 +system.cpu0: completed 20000 read accesses @662762 +system.cpu2: completed 20000 read accesses @662918 +system.cpu4: completed 20000 read accesses @663822 +system.cpu6: completed 20000 read accesses @664214 +system.cpu7: completed 20000 read accesses @673557 +system.cpu1: completed 20000 read accesses @673720 +system.cpu5: completed 20000 read accesses @675222 +system.cpu3: completed 30000 read accesses @990404 +system.cpu6: completed 30000 read accesses @991868 +system.cpu0: completed 30000 read accesses @993980 +system.cpu2: completed 30000 read accesses @994621 +system.cpu4: completed 30000 read accesses @995936 +system.cpu5: completed 30000 read accesses @1005609 +system.cpu1: completed 30000 read accesses @1008145 +system.cpu7: completed 30000 read accesses @1008840 +system.cpu6: completed 40000 read accesses @1322251 +system.cpu0: completed 40000 read accesses @1324139 +system.cpu3: completed 40000 read accesses @1324341 +system.cpu2: completed 40000 read accesses @1325019 +system.cpu4: completed 40000 read accesses @1328462 +system.cpu5: completed 40000 read accesses @1335869 +system.cpu1: completed 40000 read accesses @1336407 +system.cpu7: completed 40000 read accesses @1342910 +system.cpu6: completed 50000 read accesses @1654106 +system.cpu0: completed 50000 read accesses @1654925 +system.cpu3: completed 50000 read accesses @1657897 +system.cpu2: completed 50000 read accesses @1658205 +system.cpu1: completed 50000 read accesses @1668347 +system.cpu5: completed 50000 read accesses @1668465 +system.cpu4: completed 50000 read accesses @1670315 +system.cpu7: completed 50000 read accesses @1681232 +system.cpu6: completed 60000 read accesses @1984633 +system.cpu0: completed 60000 read accesses @1986549 +system.cpu2: completed 60000 read accesses @1989981 +system.cpu3: completed 60000 read accesses @1993690 +system.cpu1: completed 60000 read accesses @2001694 +system.cpu4: completed 60000 read accesses @2002313 +system.cpu5: completed 60000 read accesses @2005561 +system.cpu7: completed 60000 read accesses @2014675 +system.cpu6: completed 70000 read accesses @2317222 +system.cpu0: completed 70000 read accesses @2318277 +system.cpu2: completed 70000 read accesses @2322048 +system.cpu3: completed 70000 read accesses @2324750 +system.cpu4: completed 70000 read accesses @2332151 +system.cpu1: completed 70000 read accesses @2332386 +system.cpu5: completed 70000 read accesses @2332911 +system.cpu7: completed 70000 read accesses @2343337 +system.cpu0: completed 80000 read accesses @2646207 +system.cpu6: completed 80000 read accesses @2646561 +system.cpu3: completed 80000 read accesses @2652685 +system.cpu2: completed 80000 read accesses @2655532 +system.cpu5: completed 80000 read accesses @2662477 +system.cpu4: completed 80000 read accesses @2665813 +system.cpu7: completed 80000 read accesses @2668350 +system.cpu1: completed 80000 read accesses @2668666 +system.cpu6: completed 90000 read accesses @2976982 +system.cpu0: completed 90000 read accesses @2982010 +system.cpu2: completed 90000 read accesses @2983845 +system.cpu3: completed 90000 read accesses @2993125 +system.cpu5: completed 90000 read accesses @2995492 +system.cpu4: completed 90000 read accesses @2998220 +system.cpu7: completed 90000 read accesses @3003787 +system.cpu1: completed 90000 read accesses @3004322 +system.cpu6: completed 100000 read accesses @3305503 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 419882138..9fe27411d 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:37:50 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:38:54 -M5 executing on phenom -command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer +M5 compiled Aug 20 2010 12:17:38 +M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates +M5 started Aug 20 2010 12:17:55 +M5 executing on SC2B0629 +command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4329426 because maximum number of loads reached +Exiting @ tick 3305503 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 3f6218f25..d441ad68e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 332624 # Number of bytes of host memory used -host_seconds 32.19 # Real time elapsed on the host -host_tick_rate 134514 # Simulator tick rate (ticks/s) +host_mem_usage 341640 # Number of bytes of host memory used +host_seconds 37.52 # Real time elapsed on the host +host_tick_rate 88100 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.004329 # Number of seconds simulated -sim_ticks 4329426 # Number of ticks simulated +sim_seconds 0.003306 # Number of seconds simulated +sim_ticks 3305503 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99342 # number of read accesses completed -system.cpu0.num_writes 53020 # number of write accesses completed +system.cpu0.num_reads 99692 # number of read accesses completed +system.cpu0.num_writes 53673 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98745 # number of read accesses completed -system.cpu1.num_writes 53384 # number of write accesses completed +system.cpu1.num_reads 99062 # number of read accesses completed +system.cpu1.num_writes 53374 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98624 # number of read accesses completed -system.cpu2.num_writes 53313 # number of write accesses completed +system.cpu2.num_reads 99665 # number of read accesses completed +system.cpu2.num_writes 53906 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99274 # number of read accesses completed -system.cpu3.num_writes 53327 # number of write accesses completed +system.cpu3.num_reads 99457 # number of read accesses completed +system.cpu3.num_writes 53389 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98083 # number of read accesses completed -system.cpu4.num_writes 52520 # number of write accesses completed +system.cpu4.num_reads 99209 # number of read accesses completed +system.cpu4.num_writes 53779 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98306 # number of read accesses completed -system.cpu5.num_writes 52893 # number of write accesses completed +system.cpu5.num_reads 99375 # number of read accesses completed +system.cpu5.num_writes 53528 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53622 # number of write accesses completed +system.cpu6.num_writes 53388 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99389 # number of read accesses completed -system.cpu7.num_writes 53486 # number of write accesses completed +system.cpu7.num_reads 99219 # number of read accesses completed +system.cpu7.num_writes 53946 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index 48e21bb75..370a5746b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -5,13 +5,14 @@ dummy=0 [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,48 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports7.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 [system.funcmem] type=PhysicalMemory @@ -139,380 +188,288 @@ range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=false -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 -num_int_nodes=10 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] +[system.l1_cntrl0] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl0.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +[system.l1_cntrl0.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] +[system.l1_cntrl1] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl1.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] +[system.l1_cntrl1.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.l1_cntrl2] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl2.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] +[system.l1_cntrl2.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links3] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node -int_node=3 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links3.ext_node] +[system.l1_cntrl3] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl3.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] +[system.l1_cntrl3.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links4] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node -int_node=4 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links4.ext_node] +[system.l1_cntrl4] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl4.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] +[system.l1_cntrl4.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links5] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node -int_node=5 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links5.ext_node] +[system.l1_cntrl5] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl5.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] +[system.l1_cntrl5.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links6] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node -int_node=6 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links6.ext_node] +[system.l1_cntrl6] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl6.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] +[system.l1_cntrl6.cacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 +start_index_bit=6 -[system.ruby.network.topology.ext_links7] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node -int_node=7 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links7.ext_node] +[system.l1_cntrl7] type=L1Cache_Controller -children=sequencer +children=cacheMemory buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +cacheMemory=system.l1_cntrl7.cacheMemory cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.sequencer] +[system.l1_cntrl7.cacheMemory] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.l1_cntrl1.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.l1_cntrl2.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +dcache=system.l1_cntrl3.cacheMemory deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +icache=system.l1_cntrl3.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.l1_cntrl4.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl4.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.l1_cntrl5.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl5.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.l1_cntrl6.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl6.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.l1_cntrl7.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl7.cacheMemory max_outstanding_requests=16 physmem=system.physmem using_ruby_tester=false @@ -520,62 +477,105 @@ version=7 physMemPort=system.physmem.port[7] port=system.cpu7.test -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none -[system.ruby.network.topology.ext_links8] +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 +num_int_nodes=10 +print_config=false + +[system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node -int_node=8 +ext_node=system.l1_cntrl0 +int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links8.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl1 +int_node=1 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links8.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl2 +int_node=2 +latency=1 +weight=1 -[system.ruby.network.topology.ext_links8.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 +[system.ruby.network.topology.ext_links3] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl3 +int_node=3 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl4 +int_node=4 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links5] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl5 +int_node=5 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links6] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl6 +int_node=6 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links7] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl7 +int_node=7 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links8] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=8 +latency=1 +weight=1 [system.ruby.network.topology.int_links0] type=IntLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index ae201be61..f3ddd5354 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:36:18 +Real time: Aug/20/2010 13:39:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 77 -Elapsed_time_in_minutes: 1.28333 -Elapsed_time_in_hours: 0.0213889 -Elapsed_time_in_days: 0.000891204 +Elapsed_time_in_seconds: 69 +Elapsed_time_in_minutes: 1.15 +Elapsed_time_in_hours: 0.0191667 +Elapsed_time_in_days: 0.000798611 -Virtual_time_in_seconds: 76.96 -Virtual_time_in_minutes: 1.28267 -Virtual_time_in_hours: 0.0213778 -Virtual_time_in_days: 0.000890741 +Virtual_time_in_seconds: 68.75 +Virtual_time_in_minutes: 1.14583 +Virtual_time_in_hours: 0.0190972 +Virtual_time_in_days: 0.000795718 -Ruby_current_time: 11048357 +Ruby_current_time: 11059012 Ruby_start_time: 0 -Ruby_cycles: 11048357 +Ruby_cycles: 11059012 -mbytes_resident: 30.7461 -mbytes_total: 331.699 -resident_ratio: 0.0927045 +mbytes_resident: 32.25 +mbytes_total: 333.105 +resident_ratio: 0.0968279 -ruby_cycles_executed: [ 11048358 11048358 11048358 11048358 11048358 11048358 11048358 11048358 ] +ruby_cycles_executed: [ 11059013 11059013 11059013 11059013 11059013 11059013 11059013 11059013 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,13 +66,31 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1227589 average: 1.875 | standard deviation: 0.330723 | 0 153452 1074137 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228772 average: 1.9375 | standard deviation: 0.242071 | 0 76804 1151968 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 4 max: 549 count: 1227573 average: 141.876 | standard deviation: 1.82074 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 294 5125 80867 1141231 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 4 max: 549 count: 798072 average: 141.875 | standard deviation: 1.78629 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 192 3318 52570 741960 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 4 max: 531 count: 429501 average: 141.879 | standard deviation: 1.88309 | 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 102 1807 28297 399271 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 4 max: 548 count: 1228757 average: 141.941 | standard deviation: 1.79768 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 548 count: 798474 average: 141.942 | standard deviation: 1.87927 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4 max: 459 count: 430283 average: 141.94 | standard deviation: 1.63553 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 14 average: 3 | standard deviation: 0 | 0 0 0 14 ] +miss_latency_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 4 max: 548 count: 1228741 average: 141.942 | standard deviation: 1.72165 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 495 count: 6 average: 412.667 | standard deviation: 76.4147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_wCC_Times: 1228735 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_LD_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 548 count: 798465 average: 141.943 | standard deviation: 1.81358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 459 count: 430276 average: 141.942 | standard deviation: 1.53653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -86,11 +104,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227559 average: 0 | standard deviation: 0 | 1227559 ] - virtual_network_2_delay_cycles: [binsize: 4 max: 152 count: 1227559 average: 94.8743 | standard deviation: 1.46213 | 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1228743 average: 0 | standard deviation: 0 | 1228743 ] + virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1228743 average: 94.9391 | standard deviation: 1.44451 | 2 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -102,9 +120,9 @@ Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | Resource Usage -------------- page_size: 4096 -user_time: 76 +user_time: 68 system_time: 0 -page_reclaims: 8851 +page_reclaims: 9322 page_faults: 0 swaps: 0 block_inputs: 0 @@ -113,49 +131,54 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 3686271 29490168 +total_msg_count_Response_Data: 3686229 265408488 +total_msg_count_Writeback_Control: 3686259 29490072 +total_msgs: 11058759 total_bytes: 324388728 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.434016 - links_utilized_percent_switch_0_link_0: 0.173607 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.694426 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 links_utilized_percent_switch_1: 0.434016 links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.694426 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 links_utilized_percent_switch_2: 0.434016 links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.694426 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 links_utilized_percent_switch_3: 0.434016 links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.694426 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 @@ -163,32 +186,32 @@ links_utilized_percent_switch_4: 0.434014 links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1 links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 links_utilized_percent_switch_5: 0.434016 links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.694426 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.434013 - links_utilized_percent_switch_6_link_0: 0.173605 bw: 640000 base_latency: 1 +links_utilized_percent_switch_6: 0.434014 + links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1 links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 @@ -196,10 +219,10 @@ links_utilized_percent_switch_7: 0.434013 links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1 links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 @@ -207,458 +230,177 @@ links_utilized_percent_switch_8: 0.347219 links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1 links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 1227569 9820552 [ 0 0 0 1227569 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 1228753 9830024 [ 0 0 0 1228753 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 links_utilized_percent_switch_9: 0.678994 - links_utilized_percent_switch_9_link_0: 0.694429 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1 links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.694426 bw: 160000 base_latency: 1 links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1 links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1 links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.694421 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.69442 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.555545 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.0211% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.9789% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 0 --- - - Event Counts - -Load 99774 -Ifetch 0 -Store 53675 -Data 153446 -Fwd_GETX 153446 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99773 -I Ifetch 0 <-- -I Store 53674 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 1 -M Ifetch 0 <-- -M Store 1 -M Fwd_GETX 153446 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99773 - -IM Data 53673 - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.6816% - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.3184% - - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 1 --- - - Event Counts - -Load 99260 -Ifetch 0 -Store 54199 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99252 -I Ifetch 0 <-- -I Store 54195 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 8 -M Ifetch 0 <-- -M Store 4 -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99251 - -IM Data 54194 - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8804% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1196% - - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 2 --- - - Event Counts - -Load 99557 -Ifetch 0 -Store 53890 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99557 -I Ifetch 0 <-- -I Store 53890 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99555 - -IM Data 53890 - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.1254% - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.8746% - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 3 --- - - Event Counts - -Load 99933 -Ifetch 0 -Store 53514 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99933 -I Ifetch 0 <-- -I Store 53514 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99932 - -IM Data 53513 - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.1702% - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.8298% - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] - - --- L1Cache 4 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 53445 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 100001 -I Ifetch 0 <-- -I Store 53445 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 100000 - -IM Data 53445 - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.1137% - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.8863% - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 5 --- + links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.694421 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 153595 + system.l1_cntrl0.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.cacheMemory_request_type_LD: 64.8608% + system.l1_cntrl0.cacheMemory_request_type_ST: 35.1392% + + system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + + --- L1Cache --- - Event Counts - -Load 99915 -Ifetch 0 -Store 53532 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 +Load [100001 99948 99718 99978 99623 99719 99984 99512 ] 798483 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [53593 53647 53876 53616 53974 53880 53619 54083 ] 430288 +Data [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 +Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 +Inv [0 0 0 0 0 0 0 0 ] 0 +Replacement [0 0 0 0 0 0 0 0 ] 0 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load 99915 -I Ifetch 0 <-- -I Store 53532 -I Inv 0 <-- -I Replacement 0 <-- +I Load [100001 99948 99718 99978 99623 99718 99978 99512 ] 798476 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [53593 53647 53876 53616 53972 53877 53617 54083 ] 430281 +I Inv [0 0 0 0 0 0 0 0 ] 0 +I Replacement [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- +M Load [0 0 0 0 0 1 6 0 ] 7 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [0 0 0 0 2 3 2 0 ] 7 +M Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 +M Inv [0 0 0 0 0 0 0 0 ] 0 +M Replacement [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Inv [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Data 99914 +IS Data [100000 99946 99718 99976 99622 99716 99977 99512 ] 798467 -IM Data 53531 +IM Data [53593 53647 53875 53616 53971 53877 53616 54081 ] 430276 -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.cacheMemory + system.l1_cntrl1.cacheMemory_total_misses: 153595 + system.l1_cntrl1.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl1.cacheMemory_total_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0203% - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9797% + system.l1_cntrl1.cacheMemory_request_type_LD: 64.9227% + system.l1_cntrl1.cacheMemory_request_type_ST: 35.0773% - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] + system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode: 153595 100% - --- L1Cache 6 --- - - Event Counts - -Load 99771 -Ifetch 0 -Store 53675 -Data 153444 -Fwd_GETX 153444 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 +Cache Stats: system.l1_cntrl2.cacheMemory + system.l1_cntrl2.cacheMemory_total_misses: 153595 + system.l1_cntrl2.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl2.cacheMemory_total_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 99771 -I Ifetch 0 <-- -I Store 53675 -I Inv 0 <-- -I Replacement 0 <-- + system.l1_cntrl2.cacheMemory_request_type_LD: 65.092% + system.l1_cntrl2.cacheMemory_request_type_ST: 34.908% -II Writeback_Nack 0 <-- + system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode: 153595 100% -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153444 -M Inv 0 <-- -M Replacement 0 <-- +Cache Stats: system.l1_cntrl3.cacheMemory + system.l1_cntrl3.cacheMemory_total_misses: 153595 + system.l1_cntrl3.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl3.cacheMemory_total_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- + system.l1_cntrl3.cacheMemory_request_type_LD: 64.7886% + system.l1_cntrl3.cacheMemory_request_type_ST: 35.2114% -MII Fwd_GETX 0 <-- + system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode: 153595 100% -IS Data 99770 +Cache Stats: system.l1_cntrl4.cacheMemory + system.l1_cntrl4.cacheMemory_total_misses: 153594 + system.l1_cntrl4.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl4.cacheMemory_total_prefetches: 0 + system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0 -IM Data 53674 + system.l1_cntrl4.cacheMemory_request_type_LD: 65.1074% + system.l1_cntrl4.cacheMemory_request_type_ST: 34.8926% -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode: 153594 100% - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 65.0841% - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 34.9159% +Cache Stats: system.l1_cntrl5.cacheMemory + system.l1_cntrl5.cacheMemory_total_misses: 153595 + system.l1_cntrl5.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl5.cacheMemory_total_prefetches: 0 + system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] + system.l1_cntrl5.cacheMemory_request_type_LD: 65.0724% + system.l1_cntrl5.cacheMemory_request_type_ST: 34.9276% - --- L1Cache 7 --- - - Event Counts - -Load 99869 -Ifetch 0 -Store 53577 -Data 153444 -Fwd_GETX 153444 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99869 -I Ifetch 0 <-- -I Store 53577 -I Inv 0 <-- -I Replacement 0 <-- + system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode: 153595 100% -II Writeback_Nack 0 <-- +Cache Stats: system.l1_cntrl6.cacheMemory + system.l1_cntrl6.cacheMemory_total_misses: 153594 + system.l1_cntrl6.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl6.cacheMemory_total_prefetches: 0 + system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0 -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153444 -M Inv 0 <-- -M Replacement 0 <-- + system.l1_cntrl6.cacheMemory_request_type_LD: 64.9231% + system.l1_cntrl6.cacheMemory_request_type_ST: 35.0769% -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- + system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode: 153594 100% -MII Fwd_GETX 0 <-- +Cache Stats: system.l1_cntrl7.cacheMemory + system.l1_cntrl7.cacheMemory_total_misses: 153594 + system.l1_cntrl7.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl7.cacheMemory_total_prefetches: 0 + system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0 -IS Data 99868 + system.l1_cntrl7.cacheMemory_request_type_LD: 65.0924% + system.l1_cntrl7.cacheMemory_request_type_ST: 34.9076% -IM Data 53576 + system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode: 153594 100% -Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -678,70 +420,69 @@ Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1227984 -GETS 0 -PUTX 0 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 2 -Memory_Ack 0 +GETX [1229168 ] 1229168 +GETS [0 ] 0 +PUTX [0 ] 0 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 - Transitions - -I GETX 2 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 1227571 -M PUTX 0 <-- -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 411 -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 2 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 0 <-- - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [2 ] 2 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [1228755 ] 1228755 +M PUTX [0 ] 0 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [411 ] 411 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [2 ] 2 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [0 ] 0 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index a4ad9a45d..bc0af1811 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @1097795 -system.cpu1: completed 10000 read accesses @1101449 -system.cpu4: completed 10000 read accesses @1103861 -system.cpu3: completed 10000 read accesses @1104689 -system.cpu6: completed 10000 read accesses @1107767 -system.cpu2: completed 10000 read accesses @1108955 -system.cpu0: completed 10000 read accesses @1109315 -system.cpu7: completed 10000 read accesses @1115237 -system.cpu5: completed 20000 read accesses @2202527 -system.cpu4: completed 20000 read accesses @2207405 -system.cpu3: completed 20000 read accesses @2212049 -system.cpu2: completed 20000 read accesses @2212140 -system.cpu6: completed 20000 read accesses @2216495 -system.cpu1: completed 20000 read accesses @2218601 -system.cpu7: completed 20000 read accesses @2229041 -system.cpu0: completed 20000 read accesses @2229203 -system.cpu5: completed 30000 read accesses @3306575 -system.cpu4: completed 30000 read accesses @3307925 -system.cpu3: completed 30000 read accesses @3308753 -system.cpu7: completed 30000 read accesses @3318869 -system.cpu6: completed 30000 read accesses @3328247 -system.cpu2: completed 30000 read accesses @3331884 -system.cpu1: completed 30000 read accesses @3338201 -system.cpu0: completed 30000 read accesses @3340343 -system.cpu5: completed 40000 read accesses @4410227 -system.cpu4: completed 40000 read accesses @4410389 -system.cpu3: completed 40000 read accesses @4424177 -system.cpu7: completed 40000 read accesses @4429973 -system.cpu0: completed 40000 read accesses @4435175 -system.cpu6: completed 40000 read accesses @4438199 -system.cpu2: completed 40000 read accesses @4444715 -system.cpu1: completed 40000 read accesses @4450313 -system.cpu5: completed 50000 read accesses @5504627 -system.cpu4: completed 50000 read accesses @5519333 -system.cpu3: completed 50000 read accesses @5526785 -system.cpu7: completed 50000 read accesses @5529377 -system.cpu0: completed 50000 read accesses @5532419 -system.cpu6: completed 50000 read accesses @5546639 -system.cpu2: completed 50000 read accesses @5560715 -system.cpu1: completed 50000 read accesses @5569193 -system.cpu5: completed 60000 read accesses @6620303 -system.cpu4: completed 60000 read accesses @6630005 -system.cpu3: completed 60000 read accesses @6637745 -system.cpu7: completed 60000 read accesses @6639905 -system.cpu0: completed 60000 read accesses @6649463 -system.cpu6: completed 60000 read accesses @6652055 -system.cpu2: completed 60000 read accesses @6667068 -system.cpu1: completed 60000 read accesses @6690378 -system.cpu5: completed 70000 read accesses @7728671 -system.cpu3: completed 70000 read accesses @7729265 -system.cpu4: completed 70000 read accesses @7729373 -system.cpu7: completed 70000 read accesses @7748849 -system.cpu6: completed 70000 read accesses @7751423 -system.cpu0: completed 70000 read accesses @7760099 -system.cpu2: completed 70000 read accesses @7781196 -system.cpu1: completed 70000 read accesses @7788377 -system.cpu4: completed 80000 read accesses @8833637 -system.cpu3: completed 80000 read accesses @8841377 -system.cpu5: completed 80000 read accesses @8845283 -system.cpu7: completed 80000 read accesses @8850647 -system.cpu0: completed 80000 read accesses @8859269 -system.cpu6: completed 80000 read accesses @8861015 -system.cpu2: completed 80000 read accesses @8880203 -system.cpu1: completed 80000 read accesses @8893866 -system.cpu4: completed 90000 read accesses @9931349 -system.cpu7: completed 90000 read accesses @9951959 -system.cpu5: completed 90000 read accesses @9952175 -system.cpu3: completed 90000 read accesses @9957341 -system.cpu6: completed 90000 read accesses @9967079 -system.cpu0: completed 90000 read accesses @9971795 -system.cpu2: completed 90000 read accesses @9992027 -system.cpu1: completed 90000 read accesses @10012745 -system.cpu4: completed 100000 read accesses @11048357 +system.cpu5: completed 10000 read accesses @1097056 +system.cpu4: completed 10000 read accesses @1101790 +system.cpu2: completed 10000 read accesses @1104058 +system.cpu0: completed 10000 read accesses @1107910 +system.cpu7: completed 10000 read accesses @1111870 +system.cpu1: completed 10000 read accesses @1114192 +system.cpu6: completed 10000 read accesses @1114876 +system.cpu3: completed 10000 read accesses @1117090 +system.cpu5: completed 20000 read accesses @2192968 +system.cpu0: completed 20000 read accesses @2201554 +system.cpu2: completed 20000 read accesses @2213290 +system.cpu4: completed 20000 read accesses @2213470 +system.cpu6: completed 20000 read accesses @2213812 +system.cpu7: completed 20000 read accesses @2222758 +system.cpu1: completed 20000 read accesses @2232856 +system.cpu3: completed 20000 read accesses @2238562 +system.cpu5: completed 30000 read accesses @3309256 +system.cpu6: completed 30000 read accesses @3313180 +system.cpu0: completed 30000 read accesses @3314566 +system.cpu4: completed 30000 read accesses @3316942 +system.cpu2: completed 30000 read accesses @3324682 +system.cpu7: completed 30000 read accesses @3331702 +system.cpu1: completed 30000 read accesses @3337912 +system.cpu3: completed 30000 read accesses @3342322 +system.cpu5: completed 40000 read accesses @4420792 +system.cpu7: completed 40000 read accesses @4420990 +system.cpu6: completed 40000 read accesses @4421692 +system.cpu4: completed 40000 read accesses @4422430 +system.cpu0: completed 40000 read accesses @4424770 +system.cpu2: completed 40000 read accesses @4424842 +system.cpu3: completed 40000 read accesses @4446316 +system.cpu1: completed 40000 read accesses @4448440 +system.cpu5: completed 50000 read accesses @5519584 +system.cpu4: completed 50000 read accesses @5528980 +system.cpu0: completed 50000 read accesses @5530150 +system.cpu2: completed 50000 read accesses @5533210 +system.cpu7: completed 50000 read accesses @5537782 +system.cpu6: completed 50000 read accesses @5538916 +system.cpu3: completed 50000 read accesses @5549410 +system.cpu1: completed 50000 read accesses @5549536 +system.cpu7: completed 60000 read accesses @6629734 +system.cpu5: completed 60000 read accesses @6636160 +system.cpu4: completed 60000 read accesses @6637060 +system.cpu2: completed 60000 read accesses @6637402 +system.cpu0: completed 60000 read accesses @6644710 +system.cpu1: completed 60000 read accesses @6651352 +system.cpu6: completed 60000 read accesses @6651892 +system.cpu3: completed 60000 read accesses @6661234 +system.cpu7: completed 70000 read accesses @7727014 +system.cpu4: completed 70000 read accesses @7730110 +system.cpu5: completed 70000 read accesses @7736608 +system.cpu2: completed 70000 read accesses @7742746 +system.cpu6: completed 70000 read accesses @7757092 +system.cpu0: completed 70000 read accesses @7759378 +system.cpu1: completed 70000 read accesses @7770088 +system.cpu3: completed 70000 read accesses @7773058 +system.cpu5: completed 80000 read accesses @8842240 +system.cpu7: completed 80000 read accesses @8843086 +system.cpu4: completed 80000 read accesses @8844580 +system.cpu2: completed 80000 read accesses @8853131 +system.cpu0: completed 80000 read accesses @8863426 +system.cpu6: completed 80000 read accesses @8876836 +system.cpu1: completed 80000 read accesses @8878960 +system.cpu3: completed 80000 read accesses @8885602 +system.cpu5: completed 90000 read accesses @9955126 +system.cpu7: completed 90000 read accesses @9956782 +system.cpu4: completed 90000 read accesses @9957844 +system.cpu2: completed 90000 read accesses @9967690 +system.cpu1: completed 90000 read accesses @9973576 +system.cpu0: completed 90000 read accesses @9976024 +system.cpu6: completed 90000 read accesses @9981604 +system.cpu3: completed 90000 read accesses @9999874 +system.cpu4: completed 100000 read accesses @11059012 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 25d31cbd1..5cb14d0de 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 15:34:55 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:35:01 -M5 executing on cabr0210 +M5 compiled Aug 20 2010 12:21:09 +M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates +M5 started Aug 20 2010 13:38:22 +M5 executing on SC2B0629 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 11048357 because maximum number of loads reached +Exiting @ tick 11059012 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 8bfe5c848..09849fe3c 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 339664 # Number of bytes of host memory used -host_seconds 76.81 # Real time elapsed on the host -host_tick_rate 143842 # Simulator tick rate (ticks/s) +host_mem_usage 341104 # Number of bytes of host memory used +host_seconds 68.57 # Real time elapsed on the host +host_tick_rate 161272 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.011048 # Number of seconds simulated -sim_ticks 11048357 # Number of ticks simulated +sim_seconds 0.011059 # Number of seconds simulated +sim_ticks 11059012 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99774 # number of read accesses completed -system.cpu0.num_writes 53674 # number of write accesses completed +system.cpu0.num_reads 99622 # number of read accesses completed +system.cpu0.num_writes 53973 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99259 # number of read accesses completed -system.cpu1.num_writes 54198 # number of write accesses completed +system.cpu1.num_reads 99717 # number of read accesses completed +system.cpu1.num_writes 53880 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99555 # number of read accesses completed -system.cpu2.num_writes 53890 # number of write accesses completed +system.cpu2.num_reads 99983 # number of read accesses completed +system.cpu2.num_writes 53618 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99932 # number of read accesses completed -system.cpu3.num_writes 53513 # number of write accesses completed +system.cpu3.num_reads 99512 # number of read accesses completed +system.cpu3.num_writes 54081 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53445 # number of write accesses completed +system.cpu4.num_writes 53593 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99914 # number of read accesses completed -system.cpu5.num_writes 53531 # number of write accesses completed +system.cpu5.num_reads 99946 # number of read accesses completed +system.cpu5.num_writes 53647 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99770 # number of read accesses completed -system.cpu6.num_writes 53674 # number of write accesses completed +system.cpu6.num_reads 99718 # number of read accesses completed +system.cpu6.num_writes 53875 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99868 # number of read accesses completed -system.cpu7.num_writes 53576 # number of write accesses completed +system.cpu7.num_reads 99976 # number of read accesses completed +system.cpu7.num_writes 53616 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 4072a18fe..5a4805332 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -13,6 +13,7 @@ physmem=system.physmem type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -60,6 +61,7 @@ mem_side=system.toL2Bus.port[1] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -107,6 +109,7 @@ mem_side=system.toL2Bus.port[2] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -154,6 +157,7 @@ mem_side=system.toL2Bus.port[3] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -201,6 +205,7 @@ mem_side=system.toL2Bus.port[4] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -248,6 +253,7 @@ mem_side=system.toL2Bus.port[5] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -295,6 +301,7 @@ mem_side=system.toL2Bus.port[6] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -342,6 +349,7 @@ mem_side=system.toL2Bus.port[7] type=MemTest children=l1c atomic=false +issue_dmas=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr index 76b354de5..984b0004c 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read accesses @26226880 -system.cpu0: completed 10000 read accesses @26416342 -system.cpu3: completed 10000 read accesses @26427251 -system.cpu2: completed 10000 read accesses @26798889 -system.cpu5: completed 10000 read accesses @26886521 -system.cpu7: completed 10000 read accesses @27109446 -system.cpu6: completed 10000 read accesses @27197408 -system.cpu1: completed 10000 read accesses @27318359 -system.cpu4: completed 20000 read accesses @53279230 -system.cpu0: completed 20000 read accesses @53417084 -system.cpu3: completed 20000 read accesses @53757092 -system.cpu5: completed 20000 read accesses @53888320 -system.cpu2: completed 20000 read accesses @53947132 -system.cpu1: completed 20000 read accesses @54390092 -system.cpu6: completed 20000 read accesses @54397720 -system.cpu7: completed 20000 read accesses @54632966 -system.cpu0: completed 30000 read accesses @80144176 -system.cpu4: completed 30000 read accesses @80518264 -system.cpu5: completed 30000 read accesses @80638600 -system.cpu2: completed 30000 read accesses @80869702 -system.cpu6: completed 30000 read accesses @81289158 -system.cpu3: completed 30000 read accesses @81358716 -system.cpu7: completed 30000 read accesses @81981296 -system.cpu1: completed 30000 read accesses @82043104 -system.cpu0: completed 40000 read accesses @107087547 -system.cpu5: completed 40000 read accesses @107662142 -system.cpu4: completed 40000 read accesses @107722516 -system.cpu2: completed 40000 read accesses @107884124 -system.cpu6: completed 40000 read accesses @107981413 -system.cpu7: completed 40000 read accesses @108415286 -system.cpu3: completed 40000 read accesses @108655120 -system.cpu1: completed 40000 read accesses @109427858 -system.cpu0: completed 50000 read accesses @133583246 -system.cpu5: completed 50000 read accesses @133832383 -system.cpu2: completed 50000 read accesses @134755386 -system.cpu6: completed 50000 read accesses @134792594 -system.cpu7: completed 50000 read accesses @134914312 -system.cpu4: completed 50000 read accesses @134993978 -system.cpu3: completed 50000 read accesses @135362549 -system.cpu1: completed 50000 read accesses @135394370 -system.cpu5: completed 60000 read accesses @160410176 -system.cpu0: completed 60000 read accesses @160667590 -system.cpu7: completed 60000 read accesses @161466346 -system.cpu6: completed 60000 read accesses @161592434 -system.cpu2: completed 60000 read accesses @161656374 -system.cpu1: completed 60000 read accesses @161882626 -system.cpu3: completed 60000 read accesses @162062631 -system.cpu4: completed 60000 read accesses @162154299 -system.cpu0: completed 70000 read accesses @187592265 -system.cpu6: completed 70000 read accesses @188138542 -system.cpu7: completed 70000 read accesses @188373105 -system.cpu5: completed 70000 read accesses @188690782 -system.cpu4: completed 70000 read accesses @189309687 -system.cpu3: completed 70000 read accesses @189360790 -system.cpu1: completed 70000 read accesses @189391126 -system.cpu2: completed 70000 read accesses @189902895 -system.cpu0: completed 80000 read accesses @214739574 -system.cpu6: completed 80000 read accesses @215665444 -system.cpu5: completed 80000 read accesses @216021457 -system.cpu7: completed 80000 read accesses @216394344 -system.cpu4: completed 80000 read accesses @216537382 -system.cpu1: completed 80000 read accesses @216775798 -system.cpu3: completed 80000 read accesses @216868662 -system.cpu2: completed 80000 read accesses @217401619 -system.cpu0: completed 90000 read accesses @241415090 -system.cpu6: completed 90000 read accesses @242558992 -system.cpu5: completed 90000 read accesses @242897388 -system.cpu7: completed 90000 read accesses @243372191 -system.cpu4: completed 90000 read accesses @243630762 -system.cpu2: completed 90000 read accesses @243633950 -system.cpu1: completed 90000 read accesses @243710816 -system.cpu3: completed 90000 read accesses @243974160 -system.cpu0: completed 100000 read accesses @268915439 +system.cpu2: completed 10000 read accesses @26695905 +system.cpu6: completed 10000 read accesses @26791606 +system.cpu5: completed 10000 read accesses @26792650 +system.cpu1: completed 10000 read accesses @26942582 +system.cpu7: completed 10000 read accesses @27101805 +system.cpu3: completed 10000 read accesses @27218798 +system.cpu0: completed 10000 read accesses @27391241 +system.cpu4: completed 10000 read accesses @27569488 +system.cpu6: completed 20000 read accesses @53349763 +system.cpu2: completed 20000 read accesses @53503744 +system.cpu5: completed 20000 read accesses @53714174 +system.cpu7: completed 20000 read accesses @53950546 +system.cpu3: completed 20000 read accesses @54185930 +system.cpu0: completed 20000 read accesses @54225484 +system.cpu1: completed 20000 read accesses @54276231 +system.cpu4: completed 20000 read accesses @54597598 +system.cpu0: completed 30000 read accesses @80866924 +system.cpu7: completed 30000 read accesses @80945592 +system.cpu6: completed 30000 read accesses @81027764 +system.cpu2: completed 30000 read accesses @81035060 +system.cpu4: completed 30000 read accesses @81318103 +system.cpu5: completed 30000 read accesses @81377684 +system.cpu3: completed 30000 read accesses @81429000 +system.cpu1: completed 30000 read accesses @81820011 +system.cpu2: completed 40000 read accesses @106813760 +system.cpu3: completed 40000 read accesses @106974444 +system.cpu6: completed 40000 read accesses @106993530 +system.cpu7: completed 40000 read accesses @107261306 +system.cpu5: completed 40000 read accesses @107310319 +system.cpu0: completed 40000 read accesses @107652944 +system.cpu1: completed 40000 read accesses @107852182 +system.cpu4: completed 40000 read accesses @108023308 +system.cpu2: completed 50000 read accesses @133853751 +system.cpu6: completed 50000 read accesses @134086054 +system.cpu3: completed 50000 read accesses @134273902 +system.cpu7: completed 50000 read accesses @134574750 +system.cpu0: completed 50000 read accesses @134577823 +system.cpu1: completed 50000 read accesses @134778033 +system.cpu5: completed 50000 read accesses @134896821 +system.cpu4: completed 50000 read accesses @135759299 +system.cpu2: completed 60000 read accesses @161211555 +system.cpu3: completed 60000 read accesses @161581369 +system.cpu6: completed 60000 read accesses @161831828 +system.cpu0: completed 60000 read accesses @161942121 +system.cpu1: completed 60000 read accesses @162215822 +system.cpu7: completed 60000 read accesses @162487402 +system.cpu5: completed 60000 read accesses @162758928 +system.cpu4: completed 60000 read accesses @162827113 +system.cpu2: completed 70000 read accesses @188493937 +system.cpu1: completed 70000 read accesses @189035964 +system.cpu3: completed 70000 read accesses @189157397 +system.cpu6: completed 70000 read accesses @189252661 +system.cpu0: completed 70000 read accesses @189257028 +system.cpu7: completed 70000 read accesses @189348164 +system.cpu5: completed 70000 read accesses @189769120 +system.cpu4: completed 70000 read accesses @191028989 +system.cpu2: completed 80000 read accesses @215328997 +system.cpu7: completed 80000 read accesses @216072978 +system.cpu1: completed 80000 read accesses @216240482 +system.cpu6: completed 80000 read accesses @216413258 +system.cpu3: completed 80000 read accesses @216551338 +system.cpu5: completed 80000 read accesses @216884718 +system.cpu0: completed 80000 read accesses @216894493 +system.cpu4: completed 80000 read accesses @218108705 +system.cpu2: completed 90000 read accesses @242508064 +system.cpu7: completed 90000 read accesses @242698389 +system.cpu1: completed 90000 read accesses @242967798 +system.cpu5: completed 90000 read accesses @243529194 +system.cpu3: completed 90000 read accesses @243598064 +system.cpu6: completed 90000 read accesses @243621284 +system.cpu0: completed 90000 read accesses @244529131 +system.cpu4: completed 90000 read accesses @246008618 +system.cpu2: completed 100000 read accesses @269223994 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index d2f584939..35f602702 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 1 2010 14:37:40 -M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate -M5 started Jul 1 2010 14:37:50 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest +M5 compiled Aug 20 2010 12:21:09 +M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates +M5 started Aug 20 2010 12:21:31 +M5 executing on SC2B0629 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 268915439 because maximum number of loads reached +Exiting @ tick 269223994 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index b7210d154..c1f9d137d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,623 +1,623 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 318132 # Number of bytes of host memory used -host_seconds 165.43 # Real time elapsed on the host -host_tick_rate 1625594 # Simulator tick rate (ticks/s) +host_mem_usage 328092 # Number of bytes of host memory used +host_seconds 194.79 # Real time elapsed on the host +host_tick_rate 1382135 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268915439 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency +sim_ticks 269223994 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44447 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 35088.024234 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 34084.129987 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7473 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37586 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7474 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1297309520 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.831845 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 36973 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1260192538 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831845 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 36973 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 822421052 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24198 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 49598.993348 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 48595.207082 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 923 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23387 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 898 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1155656545 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.962889 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23300 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1132268325 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962889 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23300 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529109628 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3801.306186 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.403583 # Average number of references to valid blocks. -system.cpu0.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.409698 # Average number of references to valid blocks. +system.cpu0.l1c.blocked::no_mshrs 69363 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_mshrs 263670001 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69369 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8396 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60973 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68645 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40697.593699 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8372 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2452966065 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.878039 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60273 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2392460863 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.878039 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60273 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy -system.cpu0.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy -system.cpu0.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context -system.cpu0.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context -system.cpu0.l1c.overall_accesses 69369 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu0.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy +system.cpu0.l1c.occ_%::1 -0.006962 # Average percentage of cache occupancy +system.cpu0.l1c.occ_blocks::0 346.381949 # Average occupied blocks per context +system.cpu0.l1c.occ_blocks::1 -3.564360 # Average occupied blocks per context +system.cpu0.l1c.overall_accesses 68645 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40697.593699 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8396 # number of overall hits -system.cpu0.l1c.overall_miss_latency 2453091767 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60973 # number of overall misses +system.cpu0.l1c.overall_hits 8372 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2452966065 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.878039 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60273 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60973 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2392460863 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.878039 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60273 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1351530680 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.replacements 28139 # number of replacements -system.cpu0.l1c.sampled_refs 28470 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27642 # number of replacements +system.cpu0.l1c.sampled_refs 27984 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 343.673683 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11490 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 342.817588 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11465 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11130 # number of writebacks +system.cpu0.l1c.writebacks 10964 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 54239 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency +system.cpu0.num_reads 98887 # number of read accesses completed +system.cpu0.num_writes 53455 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44742 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 35246.657121 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34242.680675 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7462 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37225 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7551 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1310858425 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831232 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1273519537 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831232 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 821041101 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24235 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 48987.169998 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47983.555251 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 973 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23193 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1141988907 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961915 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23312 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1118592640 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961915 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23312 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 537191159 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3781.018448 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.411354 # Average number of references to valid blocks. -system.cpu1.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.407526 # Average number of references to valid blocks. +system.cpu1.l1c.blocked::no_mshrs 69602 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_mshrs 263166446 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68853 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8435 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60418 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68977 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40540.920814 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8474 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2452847332 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.877147 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60503 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2392112177 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.877147 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60503 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy -system.cpu1.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy -system.cpu1.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context -system.cpu1.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context -system.cpu1.l1c.overall_accesses 68853 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu1.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy +system.cpu1.l1c.occ_%::1 -0.006074 # Average percentage of cache occupancy +system.cpu1.l1c.occ_blocks::0 346.381795 # Average occupied blocks per context +system.cpu1.l1c.occ_blocks::1 -3.109691 # Average occupied blocks per context +system.cpu1.l1c.overall_accesses 68977 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40540.920814 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8435 # number of overall hits -system.cpu1.l1c.overall_miss_latency 2449625152 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60418 # number of overall misses +system.cpu1.l1c.overall_hits 8474 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2452847332 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.877147 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60503 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60418 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2392112177 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.877147 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60503 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1358232260 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.replacements 27721 # number of replacements -system.cpu1.l1c.sampled_refs 28078 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 28030 # number of replacements +system.cpu1.l1c.sampled_refs 28381 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 344.718702 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11550 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 343.272105 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11566 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10846 # number of writebacks +system.cpu1.l1c.writebacks 11122 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99301 # number of read accesses completed -system.cpu1.num_writes 53586 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency +system.cpu1.num_reads 99459 # number of read accesses completed +system.cpu1.num_writes 53508 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44755 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 34940.465460 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 33936.624875 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7472 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37075 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7682 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1295347876 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.828354 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37073 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1258132494 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.828354 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37073 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 842968180 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 23967 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49240.876366 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48237.004902 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23395 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 915 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1135100682 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.961823 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23052 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1111959437 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.961823 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23052 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 550257500 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3789.796507 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.410620 # Average number of references to valid blocks. -system.cpu2.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.418015 # Average number of references to valid blocks. +system.cpu2.l1c.blocked::no_mshrs 69457 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_mshrs 263227896 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68832 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8362 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60470 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68722 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40423.260840 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8597 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2430448558 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874902 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60125 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2370091931 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874902 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60125 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy -system.cpu2.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy -system.cpu2.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context -system.cpu2.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context -system.cpu2.l1c.overall_accesses 68832 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu2.l1c.occ_%::0 0.676497 # Average percentage of cache occupancy +system.cpu2.l1c.occ_%::1 -0.002501 # Average percentage of cache occupancy +system.cpu2.l1c.occ_blocks::0 346.366637 # Average occupied blocks per context +system.cpu2.l1c.occ_blocks::1 -1.280483 # Average occupied blocks per context +system.cpu2.l1c.overall_accesses 68722 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40423.260840 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8362 # number of overall hits -system.cpu2.l1c.overall_miss_latency 2452523238 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60470 # number of overall misses +system.cpu2.l1c.overall_hits 8597 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2430448558 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874902 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60125 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60470 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2370091931 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874902 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60125 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1393225680 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.replacements 27632 # number of replacements -system.cpu2.l1c.sampled_refs 27965 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27483 # number of replacements +system.cpu2.l1c.sampled_refs 27822 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 343.014216 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11483 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 345.086155 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11630 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10950 # number of writebacks +system.cpu2.l1c.writebacks 10776 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99024 # number of read accesses completed -system.cpu2.num_writes 53903 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 53740 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44853 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35352.171998 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34348.249371 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7547 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37391 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7463 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1321817711 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.833612 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1284281044 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833612 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 812771594 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24060 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49141.675980 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48137.889794 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23171 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 867 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1139742891 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.963965 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1116462078 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.963965 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 540024650 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3782.890162 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.410349 # Average number of references to valid blocks. -system.cpu3.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.405809 # Average number of references to valid blocks. +system.cpu3.l1c.blocked::no_mshrs 69548 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_mshrs 263092445 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68999 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8437 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60562 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68913 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40631.210108 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8330 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2461560602 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.879123 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60583 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2400743122 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.879123 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60583 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy -system.cpu3.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy -system.cpu3.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context -system.cpu3.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context -system.cpu3.l1c.overall_accesses 68999 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu3.l1c.occ_%::0 0.675485 # Average percentage of cache occupancy +system.cpu3.l1c.occ_%::1 -0.002427 # Average percentage of cache occupancy +system.cpu3.l1c.occ_blocks::0 345.848425 # Average occupied blocks per context +system.cpu3.l1c.occ_blocks::1 -1.242713 # Average occupied blocks per context +system.cpu3.l1c.overall_accesses 68913 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40631.210108 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8437 # number of overall hits -system.cpu3.l1c.overall_miss_latency 2458156635 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60562 # number of overall misses +system.cpu3.l1c.overall_hits 8330 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2461560602 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.879123 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60583 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60562 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2400743122 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.879123 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60583 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1352796244 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.replacements 27725 # number of replacements -system.cpu3.l1c.sampled_refs 28081 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27772 # number of replacements +system.cpu3.l1c.sampled_refs 28129 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 346.450009 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11523 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 344.605712 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11415 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10868 # number of writebacks +system.cpu3.l1c.writebacks 10844 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99153 # number of read accesses completed -system.cpu3.num_writes 52976 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency +system.cpu3.num_reads 99462 # number of read accesses completed +system.cpu3.num_writes 53250 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44365 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35201.306246 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34197.412075 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7629 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37136 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7447 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1299561824 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.832142 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 36918 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1262500059 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.832142 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 36918 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 824241710 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24091 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 49786.879855 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48783.051269 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 906 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23397 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 919 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1153661580 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.961853 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23172 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1130400864 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961853 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23172 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 525075683 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3810.709164 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.418843 # Average number of references to valid blocks. -system.cpu4.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.409480 # Average number of references to valid blocks. +system.cpu4.l1c.blocked::no_mshrs 69290 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_mshrs 264044038 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 69068 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8535 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60533 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68456 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40825.818006 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8366 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2453223404 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.877790 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60090 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2392900923 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.877790 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60090 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy -system.cpu4.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy -system.cpu4.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context -system.cpu4.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context -system.cpu4.l1c.overall_accesses 69068 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu4.l1c.occ_%::0 0.675570 # Average percentage of cache occupancy +system.cpu4.l1c.occ_%::1 -0.001897 # Average percentage of cache occupancy +system.cpu4.l1c.occ_blocks::0 345.891792 # Average occupied blocks per context +system.cpu4.l1c.occ_blocks::1 -0.971043 # Average occupied blocks per context +system.cpu4.l1c.overall_accesses 68456 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40825.818006 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8535 # number of overall hits -system.cpu4.l1c.overall_miss_latency 2459294321 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60533 # number of overall misses +system.cpu4.l1c.overall_hits 8366 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2453223404 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.877790 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60090 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60533 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2392900923 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.877790 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60090 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1349317393 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.replacements 27562 # number of replacements -system.cpu4.l1c.sampled_refs 27915 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27569 # number of replacements +system.cpu4.l1c.sampled_refs 27933 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 345.337496 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11692 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.920749 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11438 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10850 # number of writebacks +system.cpu4.l1c.writebacks 10833 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99282 # number of read accesses completed -system.cpu4.num_writes 53764 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency +system.cpu4.num_reads 98484 # number of read accesses completed +system.cpu4.num_writes 53322 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44597 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 35021.258089 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 34017.390307 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7762 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7416 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1302125397 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.833711 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37181 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1264800589 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.833711 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37181 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 826768479 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24074 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 49364.188581 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48360.315635 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 912 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23362 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 832 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1147322471 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.965440 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23242 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1123990456 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.965440 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23242 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 523151149 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3789.531715 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.412252 # Average number of references to valid blocks. -system.cpu5.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.409166 # Average number of references to valid blocks. +system.cpu5.l1c.blocked::no_mshrs 69635 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_mshrs 263884041 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69441 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8674 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60767 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 68671 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40538.335865 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8248 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2449447868 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.879891 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60423 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2388791045 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.879891 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60423 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy -system.cpu5.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy -system.cpu5.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context -system.cpu5.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context -system.cpu5.l1c.overall_accesses 69441 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu5.l1c.occ_%::0 0.675030 # Average percentage of cache occupancy +system.cpu5.l1c.occ_%::1 -0.001774 # Average percentage of cache occupancy +system.cpu5.l1c.occ_blocks::0 345.615536 # Average occupied blocks per context +system.cpu5.l1c.occ_blocks::1 -0.908352 # Average occupied blocks per context +system.cpu5.l1c.overall_accesses 68671 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40538.335865 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8674 # number of overall hits -system.cpu5.l1c.overall_miss_latency 2449640896 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60767 # number of overall misses +system.cpu5.l1c.overall_hits 8248 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2449447868 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.879891 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60423 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60767 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2388791045 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.879891 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60423 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1349919628 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.replacements 28158 # number of replacements -system.cpu5.l1c.sampled_refs 28502 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27529 # number of replacements +system.cpu5.l1c.sampled_refs 27886 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 346.020042 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11750 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 344.707183 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11410 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 11054 # number of writebacks +system.cpu5.l1c.writebacks 10821 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99578 # number of read accesses completed -system.cpu5.num_writes 53795 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency +system.cpu5.num_reads 99231 # number of read accesses completed +system.cpu5.num_writes 53409 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44579 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 34889.637670 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33885.824425 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7617 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37080 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7552 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1291858614 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.830593 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37027 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1254690421 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.830593 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37027 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 827526553 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24391 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 49206.403643 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 48202.444762 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23370 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 947 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1153594927 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.961174 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23444 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1130058115 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961174 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23444 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 533892016 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3771.501135 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.415709 # Average number of references to valid blocks. -system.cpu6.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.414445 # Average number of references to valid blocks. +system.cpu6.l1c.blocked::no_mshrs 69628 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_mshrs 262602081 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69001 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8551 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60450 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68970 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40440.104199 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8499 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2445453541 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.876773 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60471 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2384748536 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.876773 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60471 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy -system.cpu6.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy -system.cpu6.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context -system.cpu6.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context -system.cpu6.l1c.overall_accesses 69001 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu6.l1c.occ_%::0 0.676765 # Average percentage of cache occupancy +system.cpu6.l1c.occ_%::1 -0.002698 # Average percentage of cache occupancy +system.cpu6.l1c.occ_blocks::0 346.503445 # Average occupied blocks per context +system.cpu6.l1c.occ_blocks::1 -1.381316 # Average occupied blocks per context +system.cpu6.l1c.overall_accesses 68970 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40440.104199 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8551 # number of overall hits -system.cpu6.l1c.overall_miss_latency 2447852326 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60450 # number of overall misses +system.cpu6.l1c.overall_hits 8499 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2445453541 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.876773 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60471 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60450 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2384748536 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.876773 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60471 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1361418569 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.replacements 27563 # number of replacements -system.cpu6.l1c.sampled_refs 27921 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27737 # number of replacements +system.cpu6.l1c.sampled_refs 28093 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 342.745179 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11607 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 345.122129 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11643 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10923 # number of writebacks +system.cpu6.l1c.writebacks 11013 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99680 # number of read accesses completed -system.cpu6.num_writes 54175 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency +system.cpu6.num_reads 99221 # number of read accesses completed +system.cpu6.num_writes 53555 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 45091 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 34987.655695 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33983.814011 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7691 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1308538323 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.829434 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37400 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1270994644 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.829434 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37400 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 814528138 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24179 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 49459.078476 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48455.291783 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3782.889997 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 898 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1151456806 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.962860 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23281 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1128087648 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962860 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23281 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 533243363 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3781.140887 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. -system.cpu7.l1c.blocked::no_mshrs 69498 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.414313 # Average number of references to valid blocks. +system.cpu7.l1c.blocked::no_mshrs 69687 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles::no_mshrs 262903289 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_mshrs 263496365 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69270 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40539.792175 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8589 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2459995129 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876007 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60681 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 2399082292 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876007 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60681 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.occ_%::0 0.676947 # Average percentage of cache occupancy -system.cpu7.l1c.occ_%::1 -0.001736 # Average percentage of cache occupancy -system.cpu7.l1c.occ_blocks::0 346.596700 # Average occupied blocks per context -system.cpu7.l1c.occ_blocks::1 -0.888916 # Average occupied blocks per context -system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.occ_%::0 0.680280 # Average percentage of cache occupancy +system.cpu7.l1c.occ_%::1 -0.007590 # Average percentage of cache occupancy +system.cpu7.l1c.occ_blocks::0 348.303356 # Average occupied blocks per context +system.cpu7.l1c.occ_blocks::1 -3.885943 # Average occupied blocks per context +system.cpu7.l1c.overall_accesses 69270 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40539.792175 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8481 # number of overall hits -system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60440 # number of overall misses +system.cpu7.l1c.overall_hits 8589 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2459995129 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876007 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60681 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 2399082292 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876007 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60681 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1347771501 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.replacements 27627 # number of replacements -system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 28023 # number of replacements +system.cpu7.l1c.sampled_refs 28394 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 345.385459 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11764 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10984 # number of writebacks +system.cpu7.l1c.writebacks 11064 # number of writebacks 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# average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 397488.749417 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 396311.503279 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 397699.708311 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::4 399565.847499 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::5 403655.349278 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::6 399225.247949 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::7 397025.426725 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 3191263.387158 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles +system.cpu7.num_reads 99565 # number of read accesses completed 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+system.l2c.ReadExReq_avg_miss_latency::2 401215.324171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 399884.237372 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::4 394855.575822 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::5 399285.992092 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::6 399200.674573 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::7 399030.148868 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 3192762.352326 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 39999.222355 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3736518314 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses @@ -627,108 +627,108 @@ system.l2c.ReadExReq_miss_rate::5 1 # mi system.l2c.ReadExReq_miss_rate::6 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::7 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 8 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 9360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 9426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 9454 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 9421 # number of ReadExReq misses -system.l2c.ReadExReq_misses::4 9377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::5 9282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::6 9385 # number of ReadExReq misses -system.l2c.ReadExReq_misses::7 9437 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 75142 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 7.965278 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 7.909506 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 7.886080 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 7.913703 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::4 7.950837 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::5 8.032213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::6 7.944060 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::7 7.900286 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 63.501963 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses 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-system.l2c.ReadReq_avg_miss_latency::3 396065.052675 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::4 402281.769958 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::5 398581.854013 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::6 391254.019534 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::7 397187.049992 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 3177141.589053 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency +system.l2c.ReadExReq_misses::0 9412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 9288 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 9313 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 9344 # number of ReadExReq misses +system.l2c.ReadExReq_misses::4 9463 # number of ReadExReq misses +system.l2c.ReadExReq_misses::5 9358 # number of ReadExReq misses +system.l2c.ReadExReq_misses::6 9360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::7 9364 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 74902 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 557 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2973742186 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 7.898959 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 8.004414 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 7.982927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 7.956443 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::4 7.856388 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::5 7.944539 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::6 7.942842 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::7 7.939449 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 63.525961 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 74345 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 17188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 17330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 17220 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 17498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::4 17144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::5 17272 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::6 17157 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::7 17383 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 138192 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 401579.741645 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 391420.730324 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 401239.419831 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 391097.402445 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::4 398873.222746 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::5 393306.625187 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::6 405084.287645 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::7 395078.867991 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 3177680.297815 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40002.426325 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 11351 # number of ReadReq hits -system.l2c.ReadReq_hits::1 11171 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11100 # number of ReadReq hits -system.l2c.ReadReq_hits::3 11322 # number of ReadReq hits -system.l2c.ReadReq_hits::4 11319 # number of ReadReq hits -system.l2c.ReadReq_hits::5 11369 # number of ReadReq hits -system.l2c.ReadReq_hits::6 11109 # number of ReadReq hits -system.l2c.ReadReq_hits::7 11165 # number of ReadReq hits -system.l2c.ReadReq_hits::total 89906 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.346291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.349956 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.349851 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.347059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::4 0.343598 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::5 0.344688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::6 0.354165 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::7 0.349586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 2.785195 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 6013 # number of ReadReq misses -system.l2c.ReadReq_misses::1 6014 # number of ReadReq misses -system.l2c.ReadReq_misses::2 5973 # number of ReadReq misses -system.l2c.ReadReq_misses::3 6018 # number of ReadReq misses -system.l2c.ReadReq_misses::4 5925 # number of ReadReq misses -system.l2c.ReadReq_misses::5 5980 # number of ReadReq misses -system.l2c.ReadReq_misses::6 6092 # number of ReadReq misses -system.l2c.ReadReq_misses::7 6001 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48016 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 2.706750 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.734943 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.752885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 2.710496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::4 2.725586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::5 2.709090 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::6 2.732399 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::7 2.737970 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 21.810119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 2273 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 2288 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 2314 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 2311 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::4 2383 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::5 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::6 2257 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::7 2313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18428 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 226995.596128 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 225507.425699 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 222973.634399 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 223263.085244 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::4 216517.410827 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::5 225408.907820 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::6 228604.780682 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::7 223070.034587 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1792340.875388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits::0 11293 # number of ReadReq hits +system.l2c.ReadReq_hits::1 11282 # number of ReadReq hits +system.l2c.ReadReq_hits::2 11320 # number of ReadReq hits +system.l2c.ReadReq_hits::3 11445 # number of ReadReq hits +system.l2c.ReadReq_hits::4 11209 # number of ReadReq hits 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+system.l2c.ReadReq_mshr_miss_rate::3 2.664133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::4 2.719144 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::5 2.698993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::6 2.717083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::7 2.681758 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 21.590396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 46617 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3184396233 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 2342 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 2293 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 2237 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 2252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::4 2274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::5 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::6 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::7 2359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18459 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 217987.236123 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 222645.489315 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 228219.091194 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 226698.981794 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::4 224505.763852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::5 217152.746491 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::6 217152.746491 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::7 216416.323442 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1770778.378702 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.703945 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 510526107 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses @@ -738,189 +738,189 @@ system.l2c.UpgradeReq_miss_rate::5 1 # mi system.l2c.UpgradeReq_miss_rate::6 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::7 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 8 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 2288 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 2314 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 2311 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::4 2383 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::5 2289 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::6 2257 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::7 2313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18428 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 8.087549 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 8.034528 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 7.944252 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 7.954565 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::4 7.714226 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::5 8.031018 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::6 8.144883 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::7 7.947687 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 63.858708 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::0 2342 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 2293 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 2237 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 2252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::4 2274 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::5 2351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::6 2351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::7 2359 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18459 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 57 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 736092954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 7.857387 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 8.025294 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 8.226196 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 8.171403 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::4 8.092348 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::5 7.827308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::6 7.827308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::7 7.800763 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 63.828007 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 18402 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 86929 # number of Writeback hits -system.l2c.Writeback_hits::total 86929 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs 7154.090909 # average number of cycles each access was blocked +system.l2c.WriteReq_mshr_uncacheable_latency 1720878838 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 86764 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 86764 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 86764 # number of Writeback hits +system.l2c.Writeback_hits::total 86764 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs 6575.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked +system.l2c.avg_refs 2.025850 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 22 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 78695 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 144661 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 26724 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 26611 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 26527 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 26761 # number of demand (read+write) accesses -system.l2c.demand_accesses::4 26621 # number of demand (read+write) accesses -system.l2c.demand_accesses::5 26631 # number of demand (read+write) accesses -system.l2c.demand_accesses::6 26586 # number of demand (read+write) accesses -system.l2c.demand_accesses::7 26603 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 213064 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 398767.217784 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 397036.815997 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 397371.390355 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 397062.532483 # average overall miss latency -system.l2c.demand_avg_miss_latency::4 400617.464318 # average overall miss latency -system.l2c.demand_avg_miss_latency::5 401667.438016 # average overall miss latency -system.l2c.demand_avg_miss_latency::6 396087.642243 # average overall miss latency -system.l2c.demand_avg_miss_latency::7 397088.252300 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3185698.753496 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency -system.l2c.demand_hits::0 11351 # number of demand (read+write) hits -system.l2c.demand_hits::1 11171 # number of demand (read+write) hits -system.l2c.demand_hits::2 11100 # number of demand (read+write) hits -system.l2c.demand_hits::3 11322 # number of demand (read+write) hits -system.l2c.demand_hits::4 11319 # number of demand (read+write) hits -system.l2c.demand_hits::5 11369 # number of demand (read+write) hits -system.l2c.demand_hits::6 11109 # number of demand (read+write) hits -system.l2c.demand_hits::7 11165 # number of demand (read+write) hits -system.l2c.demand_hits::total 89906 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.575251 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.580211 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.581558 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.576922 # miss rate for demand accesses -system.l2c.demand_miss_rate::4 0.574809 # miss rate for demand accesses -system.l2c.demand_miss_rate::5 0.573092 # miss rate for demand accesses -system.l2c.demand_miss_rate::6 0.582148 # miss rate for demand accesses -system.l2c.demand_miss_rate::7 0.580310 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 4.624302 # miss rate for demand accesses -system.l2c.demand_misses::0 15373 # number of demand (read+write) misses -system.l2c.demand_misses::1 15440 # number of demand (read+write) misses -system.l2c.demand_misses::2 15427 # number of demand (read+write) misses -system.l2c.demand_misses::3 15439 # number of demand (read+write) misses -system.l2c.demand_misses::4 15302 # number of demand (read+write) misses -system.l2c.demand_misses::5 15262 # number of demand (read+write) misses -system.l2c.demand_misses::6 15477 # number of demand (read+write) misses -system.l2c.demand_misses::7 15438 # number of demand (read+write) misses -system.l2c.demand_misses::total 123158 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 4.548533 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 4.567848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 4.582312 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 4.542244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::4 4.566132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::5 4.564417 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::6 4.572143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::7 4.569222 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 36.512852 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 26600 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 26618 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 26533 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 26842 # number of demand (read+write) accesses +system.l2c.demand_accesses::4 26607 # number of demand (read+write) accesses +system.l2c.demand_accesses::5 26630 # number of demand (read+write) accesses +system.l2c.demand_accesses::6 26517 # number of demand (read+write) accesses +system.l2c.demand_accesses::7 26747 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 213094 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 398760.755929 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 398006.709116 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 401224.669099 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 396429.881860 # average overall miss latency +system.l2c.demand_avg_miss_latency::4 396404.136316 # average overall miss latency +system.l2c.demand_avg_miss_latency::5 396945.495935 # average overall miss latency +system.l2c.demand_avg_miss_latency::6 401462.173836 # average overall miss latency +system.l2c.demand_avg_miss_latency::7 397488.336220 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3186722.158311 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency +system.l2c.demand_hits::0 11293 # number of demand (read+write) hits +system.l2c.demand_hits::1 11282 # number of demand (read+write) hits +system.l2c.demand_hits::2 11320 # number of demand (read+write) hits +system.l2c.demand_hits::3 11445 # number of demand (read+write) hits +system.l2c.demand_hits::4 11209 # number of demand (read+write) hits +system.l2c.demand_hits::5 11253 # number of demand (read+write) hits +system.l2c.demand_hits::6 11313 # number of demand (read+write) hits +system.l2c.demand_hits::7 11391 # number of demand (read+write) hits +system.l2c.demand_hits::total 90506 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6103830891 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.575451 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.576151 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.573361 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.573616 # miss rate for demand accesses +system.l2c.demand_miss_rate::4 0.578720 # miss rate for demand accesses +system.l2c.demand_miss_rate::5 0.577431 # miss rate for demand accesses +system.l2c.demand_miss_rate::6 0.573368 # miss rate for demand accesses +system.l2c.demand_miss_rate::7 0.574120 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 4.602220 # miss rate for demand accesses +system.l2c.demand_misses::0 15307 # number of demand (read+write) misses +system.l2c.demand_misses::1 15336 # number of demand (read+write) misses +system.l2c.demand_misses::2 15213 # number of demand (read+write) misses +system.l2c.demand_misses::3 15397 # number of demand (read+write) misses +system.l2c.demand_misses::4 15398 # number of demand (read+write) misses +system.l2c.demand_misses::5 15377 # number of demand (read+write) misses +system.l2c.demand_misses::6 15204 # number of demand (read+write) misses +system.l2c.demand_misses::7 15356 # number of demand (read+write) misses +system.l2c.demand_misses::total 122588 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1626 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4838535294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 4.547444 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 4.544368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 4.558927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 4.506445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::4 4.546247 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::5 4.542321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::6 4.561677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::7 4.522451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 36.329880 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 120962 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.025896 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.025716 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.025892 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.026232 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.025792 # Average percentage of cache occupancy -system.l2c.occ_%::5 0.026195 # Average percentage of cache occupancy -system.l2c.occ_%::6 0.026471 # Average percentage of cache occupancy -system.l2c.occ_%::7 0.026663 # Average percentage of cache occupancy -system.l2c.occ_%::8 0.410030 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 26.517416 # Average occupied blocks per context -system.l2c.occ_blocks::1 26.332816 # Average occupied blocks per context -system.l2c.occ_blocks::2 26.512954 # Average occupied blocks per context -system.l2c.occ_blocks::3 26.861209 # Average occupied blocks per context -system.l2c.occ_blocks::4 26.410697 # Average occupied blocks per context -system.l2c.occ_blocks::5 26.823356 # Average occupied blocks per context -system.l2c.occ_blocks::6 27.106140 # Average occupied blocks per context -system.l2c.occ_blocks::7 27.302482 # Average occupied blocks per context -system.l2c.occ_blocks::8 419.870758 # Average occupied blocks per context -system.l2c.overall_accesses::0 26724 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 26611 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 26527 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 26761 # number of overall (read+write) accesses -system.l2c.overall_accesses::4 26621 # number of overall (read+write) accesses -system.l2c.overall_accesses::5 26631 # number of overall (read+write) accesses -system.l2c.overall_accesses::6 26586 # number of overall (read+write) accesses -system.l2c.overall_accesses::7 26603 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 213064 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 398767.217784 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 397036.815997 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 397371.390355 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 397062.532483 # average overall miss latency -system.l2c.overall_avg_miss_latency::4 400617.464318 # average overall miss latency -system.l2c.overall_avg_miss_latency::5 401667.438016 # average overall miss latency -system.l2c.overall_avg_miss_latency::6 396087.642243 # average overall miss latency -system.l2c.overall_avg_miss_latency::7 397088.252300 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3185698.753496 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.occ_%::0 0.025853 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.026694 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.026105 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.026914 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.026038 # Average percentage of cache occupancy +system.l2c.occ_%::5 0.026270 # Average percentage of cache occupancy +system.l2c.occ_%::6 0.025331 # Average percentage of cache occupancy +system.l2c.occ_%::7 0.026254 # Average percentage of cache occupancy +system.l2c.occ_%::8 0.409154 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 26.473544 # Average occupied blocks per context +system.l2c.occ_blocks::1 27.334486 # Average occupied blocks per context +system.l2c.occ_blocks::2 26.731121 # Average occupied blocks per context +system.l2c.occ_blocks::3 27.560151 # Average occupied blocks per context +system.l2c.occ_blocks::4 26.663054 # Average occupied blocks per context +system.l2c.occ_blocks::5 26.900488 # Average occupied blocks per context +system.l2c.occ_blocks::6 25.938523 # Average occupied blocks per context +system.l2c.occ_blocks::7 26.884287 # Average occupied blocks per context +system.l2c.occ_blocks::8 418.973617 # Average occupied blocks per context +system.l2c.overall_accesses::0 26600 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 26618 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 26533 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 26842 # number of overall (read+write) accesses +system.l2c.overall_accesses::4 26607 # number of overall (read+write) accesses +system.l2c.overall_accesses::5 26630 # number of overall (read+write) accesses +system.l2c.overall_accesses::6 26517 # number of overall (read+write) accesses +system.l2c.overall_accesses::7 26747 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 213094 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 398760.755929 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 398006.709116 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 401224.669099 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 396429.881860 # average overall miss latency +system.l2c.overall_avg_miss_latency::4 396404.136316 # average overall miss latency +system.l2c.overall_avg_miss_latency::5 396945.495935 # average overall miss latency +system.l2c.overall_avg_miss_latency::6 401462.173836 # average overall miss latency +system.l2c.overall_avg_miss_latency::7 397488.336220 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3186722.158311 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 11351 # number of overall hits -system.l2c.overall_hits::1 11171 # number of overall hits -system.l2c.overall_hits::2 11100 # number of overall hits -system.l2c.overall_hits::3 11322 # number of overall hits -system.l2c.overall_hits::4 11319 # number of overall hits -system.l2c.overall_hits::5 11369 # number of overall hits -system.l2c.overall_hits::6 11109 # number of overall hits -system.l2c.overall_hits::7 11165 # number of overall hits -system.l2c.overall_hits::total 89906 # number of overall hits -system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.575251 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.580211 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.581558 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.576922 # miss rate for overall accesses -system.l2c.overall_miss_rate::4 0.574809 # miss rate for overall accesses -system.l2c.overall_miss_rate::5 0.573092 # miss rate for overall accesses -system.l2c.overall_miss_rate::6 0.582148 # miss rate for overall accesses -system.l2c.overall_miss_rate::7 0.580310 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 4.624302 # miss rate for overall accesses -system.l2c.overall_misses::0 15373 # number of overall misses -system.l2c.overall_misses::1 15440 # number of overall misses -system.l2c.overall_misses::2 15427 # number of overall misses -system.l2c.overall_misses::3 15439 # number of overall misses -system.l2c.overall_misses::4 15302 # number of overall misses -system.l2c.overall_misses::5 15262 # number of overall misses -system.l2c.overall_misses::6 15477 # number of overall misses -system.l2c.overall_misses::7 15438 # number of overall misses -system.l2c.overall_misses::total 123158 # number of overall misses -system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 4.548533 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 4.567848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 4.582312 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 4.542244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::4 4.566132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::5 4.564417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::6 4.572143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::7 4.569222 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 36.512852 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 11293 # number of overall hits +system.l2c.overall_hits::1 11282 # number of overall hits +system.l2c.overall_hits::2 11320 # number of overall hits +system.l2c.overall_hits::3 11445 # number of overall hits +system.l2c.overall_hits::4 11209 # number of overall hits +system.l2c.overall_hits::5 11253 # number of overall hits +system.l2c.overall_hits::6 11313 # number of overall hits +system.l2c.overall_hits::7 11391 # number of overall hits +system.l2c.overall_hits::total 90506 # number of overall hits +system.l2c.overall_miss_latency 6103830891 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.575451 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.576151 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.573361 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.573616 # miss rate for overall accesses +system.l2c.overall_miss_rate::4 0.578720 # miss rate for overall accesses +system.l2c.overall_miss_rate::5 0.577431 # miss rate for overall accesses +system.l2c.overall_miss_rate::6 0.573368 # miss rate for overall accesses +system.l2c.overall_miss_rate::7 0.574120 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 4.602220 # miss rate for overall accesses +system.l2c.overall_misses::0 15307 # number of overall misses +system.l2c.overall_misses::1 15336 # number of overall misses +system.l2c.overall_misses::2 15213 # number of overall misses +system.l2c.overall_misses::3 15397 # number of overall misses +system.l2c.overall_misses::4 15398 # number of overall misses +system.l2c.overall_misses::5 15377 # number of overall misses +system.l2c.overall_misses::6 15204 # number of overall misses +system.l2c.overall_misses::7 15356 # number of overall misses +system.l2c.overall_misses::total 122588 # number of overall misses +system.l2c.overall_mshr_hits 1626 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4838535294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 4.547444 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 4.544368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 4.558927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 4.506445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::4 4.546247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::5 4.542321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::6 4.561677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::7 4.522451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 36.329880 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 120962 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4905275071 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 73303 # number of replacements -system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. +system.l2c.replacements 72848 # number of replacements +system.l2c.sampled_refs 73502 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.737828 # Cycle average of tags in use -system.l2c.total_refs 148204 # Total number of references to valid blocks. +system.l2c.tagsinuse 633.459270 # Cycle average of tags in use +system.l2c.total_refs 148904 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 47216 # number of writebacks +system.l2c.writebacks 46916 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini index ab3a160f3..6bc7e48b3 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini @@ -5,10 +5,118 @@ dummy=0 [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +125,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -56,6 +164,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 num_int_nodes=4 @@ -63,136 +172,28 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index 2e2c8b656..99657e89a 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:37:01 +Real time: Aug/20/2010 11:29:01 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 1.11 -Virtual_time_in_minutes: 0.0185 -Virtual_time_in_hours: 0.000308333 -Virtual_time_in_days: 1.28472e-05 +Virtual_time_in_seconds: 0.73 +Virtual_time_in_minutes: 0.0121667 +Virtual_time_in_hours: 0.000202778 +Virtual_time_in_days: 8.44907e-06 -Ruby_current_time: 385311 +Ruby_current_time: 362171 Ruby_start_time: 0 -Ruby_cycles: 385311 +Ruby_cycles: 362171 -mbytes_resident: 30.6758 -mbytes_total: 203.664 -resident_ratio: 0.150658 +mbytes_resident: 31.3438 +mbytes_total: 204.512 +resident_ratio: 0.153319 -ruby_cycles_executed: [ 385312 ] +ruby_cycles_executed: [ 362172 ] Busy Controller Counts: L1Cache-0:0 @@ -66,13 +66,28 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1035 average: 15.8406 | standard deviation: 1.10345 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 975 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 989 average: 15.8261 | standard deviation: 1.13064 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 922 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 256 max: 34673 count: 1020 average: 5812.61 | standard deviation: 8321.57 | 94 13 65 91 82 85 75 46 28 39 28 23 31 15 11 13 6 8 12 9 6 3 9 2 3 6 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 3 1 0 0 0 0 0 0 2 2 0 3 1 3 1 3 2 1 6 1 2 2 5 2 7 2 1 3 4 4 3 2 6 5 9 2 2 10 1 6 4 3 4 4 5 3 5 2 5 5 2 3 6 3 3 1 3 3 4 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 256 max: 28025 count: 100 average: 5269.19 | standard deviation: 7878.72 | 12 1 6 6 7 10 10 8 2 4 3 0 3 2 1 2 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 2 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 256 max: 34673 count: 920 average: 5871.67 | standard deviation: 8370.25 | 82 12 59 85 75 75 65 38 26 35 25 23 28 13 10 11 6 7 11 9 6 3 8 2 2 5 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 2 1 0 0 0 0 0 0 2 2 0 2 0 3 0 3 2 1 6 1 2 1 5 2 6 2 1 3 4 3 3 1 4 4 9 2 2 10 1 5 3 3 4 4 4 3 5 2 4 5 2 3 5 3 3 1 2 3 3 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 32770 count: 974 average: 5848.35 | standard deviation: 7643.86 | 78 21 56 74 77 80 49 39 35 30 33 25 16 19 17 15 6 9 8 7 4 5 5 5 4 3 8 3 5 6 5 7 0 3 1 6 1 3 3 1 1 1 2 1 1 1 3 2 0 1 2 3 2 6 3 3 2 3 2 4 3 6 2 3 6 5 3 3 3 2 4 2 3 5 10 4 1 3 4 9 3 4 3 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 16 max: 2239 count: 47 average: 995.638 | standard deviation: 452.716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 2 0 0 0 1 0 2 2 1 0 0 0 0 2 1 0 0 0 1 0 2 1 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 2 0 2 1 0 2 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 21145 count: 53 average: 4245.77 | standard deviation: 5383.1 | 5 0 0 0 1 1 4 2 1 2 1 6 3 2 1 0 1 1 0 0 0 1 3 0 0 1 0 1 0 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 256 max: 32770 count: 874 average: 6206.49 | standard deviation: 7863.36 | 73 14 42 60 69 63 42 36 32 30 32 22 15 18 15 14 6 9 8 6 4 5 4 5 4 3 7 3 5 6 5 7 0 3 1 4 1 2 3 1 1 1 2 1 1 0 3 2 0 1 2 3 2 6 3 3 2 2 1 4 3 6 2 2 6 5 3 2 3 2 4 2 3 4 10 4 1 3 4 9 3 4 2 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 32770 count: 974 average: 5848.35 | standard deviation: 7643.86 | 78 21 56 74 77 80 49 39 35 30 33 25 16 19 17 15 6 9 8 7 4 5 5 5 4 3 8 3 5 6 5 7 0 3 1 6 1 3 3 1 1 1 2 1 1 1 3 2 0 1 2 3 2 6 3 3 2 3 2 4 3 6 2 3 6 5 3 3 3 2 4 2 3 5 10 4 1 3 4 9 3 4 3 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 16 max: 2239 count: 47 average: 995.638 | standard deviation: 452.716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 2 0 0 0 1 0 2 2 1 0 0 0 0 2 1 0 0 0 1 0 2 1 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 2 0 2 1 0 2 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 128 max: 21145 count: 53 average: 4245.77 | standard deviation: 5383.1 | 5 0 0 0 1 1 4 2 1 2 1 6 3 2 1 0 1 1 0 0 0 1 3 0 0 1 0 1 0 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 256 max: 32770 count: 874 average: 6206.49 | standard deviation: 7863.36 | 73 14 42 60 69 63 42 36 32 30 32 22 15 18 15 14 6 9 8 6 4 5 4 5 4 3 7 3 5 6 5 7 0 3 1 4 1 2 3 1 1 1 2 1 1 0 3 2 0 1 2 3 2 6 3 3 2 2 1 4 3 6 2 2 6 5 3 2 3 2 4 2 3 4 10 4 1 3 4 9 3 4 2 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -86,12 +101,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1500 count: 6932 average: 17.1509 | standard deviation: 98.3547 | 6592 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4219 average: 0 | standard deviation: 0 | 4219 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1500 count: 2713 average: 43.8223 | standard deviation: 153.471 | 2373 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ] +Total_delay_cycles: [binsize: 32 max: 1370 count: 6560 average: 27.1387 | standard deviation: 120.504 | 6041 13 41 130 8 21 48 8 12 22 20 4 19 15 5 14 23 3 9 21 22 3 9 6 3 6 6 3 1 2 5 1 3 4 2 0 3 1 1 1 0 0 1 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4028 average: 0 | standard deviation: 0 | 4028 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 1370 count: 2532 average: 70.312 | standard deviation: 185.996 | 2013 13 41 130 8 21 48 8 12 22 20 4 19 15 5 14 23 3 9 21 22 3 9 6 3 6 6 3 1 2 5 1 3 4 2 0 3 1 1 1 0 0 1 0 0 0 0 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 566 average: 0 | standard deviation: 0 | 566 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3653 average: 0 | standard deviation: 0 | 3653 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 512 average: 0 | standard deviation: 0 | 512 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3516 average: 0 | standard deviation: 0 | 3516 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -102,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4219 average: 0 | standa Resource Usage -------------- page_size: 4096 -user_time: 1 +user_time: 0 system_time: 0 -page_reclaims: 8843 +page_reclaims: 9085 page_faults: 0 swaps: 0 block_inputs: 0 @@ -113,490 +128,494 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 5304 42432 +total_msg_count_Request_Control: 1537 12296 +total_msg_count_Response_Data: 7619 548568 +total_msg_count_Response_Control: 6666 53328 +total_msg_count_Writeback_Data: 3615 260280 +total_msg_count_Writeback_Control: 132 1056 +total_msgs: 24873 total_bytes: 917960 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.105942 - links_utilized_percent_switch_0_link_0: 0.0300309 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.181853 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 931 7448 [ 0 6 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.103063 + links_utilized_percent_switch_0_link_0: 0.0310005 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.175124 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 512 4096 [ 512 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 899 64728 [ 0 899 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 379 3032 [ 0 379 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 895 7160 [ 0 43 852 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151597 - links_utilized_percent_switch_1_link_0: 0.0748065 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.228387 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1743 125496 [ 0 1743 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 441 3528 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.153567 + links_utilized_percent_switch_1_link_0: 0.0736531 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.233481 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1756 14048 [ 0 904 852 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 513 4104 [ 513 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1674 120528 [ 0 1674 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 466 3728 [ 0 466 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0722257 - links_utilized_percent_switch_2_link_0: 0.0270658 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.117386 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0734115 + links_utilized_percent_switch_2_link_0: 0.0273352 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.119488 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 901 7208 [ 0 901 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 774 55728 [ 0 774 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 861 6888 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.175871 - links_utilized_percent_switch_3_link_0: 0.120124 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.299226 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.108263 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_3: 0.176026 + links_utilized_percent_switch_3_link_0: 0.124002 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.294612 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.109465 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 512 4096 [ 512 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 899 64728 [ 0 899 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 379 3032 [ 0 379 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 1756 14048 [ 0 904 852 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 775 55800 [ 0 775 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 1000 -Inv 566 -L1_Replacement 547844 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 88 -DataS_fromL1 0 -Data_all_Acks 838 -Ack 0 -Ack_all 0 -WB_Ack 357 +Load [53 ] 53 +Ifetch [260 ] 260 +Store [877 ] 877 +Inv [512 ] 512 +L1_Replacement [510484 ] 510484 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [48 ] 48 +DataS_fromL1 [0 ] 0 +Data_all_Acks [851 ] 851 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [379 ] 379 - Transitions - -NP Load 88 -NP Ifetch 0 <-- -NP Store 839 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I Inv 0 <-- -I L1_Replacement 63 - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S Inv 0 <-- -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 1 -E Inv 6 -E L1_Replacement 80 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 12 -M Ifetch 0 <-- -M Store 81 -M Inv 57 -M L1_Replacement 781 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 46341 -IS Data_Exclusive 88 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 0 <-- - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 500579 -IM Data 0 <-- -IM Data_all_Acks 838 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 79 -M_I Inv 503 -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 357 - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [48 ] 48 +NP Ifetch [47 ] 47 +NP Store [806 ] 806 +NP Inv [1 ] 1 +NP L1_Replacement [0 ] 0 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Inv [0 ] 0 +I L1_Replacement [110 ] 110 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S Inv [26 ] 26 +S L1_Replacement [6 ] 6 + +E Load [0 ] 0 +E Ifetch [0 ] 0 +E Store [0 ] 0 +E Inv [3 ] 3 +E L1_Replacement [45 ] 45 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [5 ] 5 +M Ifetch [0 ] 0 +M Store [70 ] 70 +M Inv [68 ] 68 +M L1_Replacement [735 ] 735 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [13 ] 13 +IS L1_Replacement [28783 ] 28783 +IS Data_Exclusive [48 ] 48 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [34 ] 34 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [480805 ] 480805 +IM Data [0 ] 0 +IM Data_all_Acks [804 ] 804 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [13 ] 13 + +M_I Load [0 ] 0 +M_I Ifetch [213 ] 213 +M_I Store [1 ] 1 +M_I Inv [401 ] 401 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [379 ] 379 + +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GET_INSTR 0 -L1_GETS 94 -L1_GETX 851 -L1_UPGRADE 0 -L1_PUTX 506 -L1_PUTX_old 504 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 292 -L2_Replacement_clean 12332 -Mem_Data 905 -Mem_Ack 900 -WB_Data 525 -WB_Data_clean 34 -Ack 0 -Ack_all 6 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 925 -MEM_Inv 0 +L1_GET_INSTR [48 ] 48 +L1_GETS [48 ] 48 +L1_GETX [807 ] 807 +L1_UPGRADE [0 ] 0 +L1_PUTX [568 ] 568 +L1_PUTX_old [1966 ] 1966 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [328 ] 328 +L2_Replacement_clean [16621 ] 16621 +Mem_Data [865 ] 865 +Mem_Ack [861 ] 861 +WB_Data [447 ] 447 +WB_Data_clean [22 ] 22 +Ack [0 ] 0 +Ack_all [43 ] 43 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [852 ] 852 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 0 <-- -NP L1_GETS 86 -NP L1_GETX 820 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 95 - -SS L1_GET_INSTR 0 <-- -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 0 <-- -SS MEM_Inv 0 <-- - -M L1_GET_INSTR 0 <-- -M L1_GETS 2 -M L1_GETX 19 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 292 -M L2_Replacement_clean 44 -M MEM_Inv 0 <-- - -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 357 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 0 <-- -MT L2_Replacement_clean 566 -MT MEM_Inv 0 <-- - -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 6 -M_I L1_GETX 12 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 108 -M_I Mem_Ack 900 -M_I MEM_Inv 0 <-- - -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 0 <-- -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 0 <-- -MT_I MEM_Inv 0 <-- - -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 124 -MCT_I WB_Data 525 -MCT_I WB_Data_clean 34 -MCT_I Ack_all 6 - -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 0 <-- - -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- - -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 481 -ISS Mem_Data 86 -ISS MEM_Inv 0 <-- - -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 0 <-- -IS MEM_Inv 0 <-- - -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 4544 -IM Mem_Data 819 -IM MEM_Inv 0 <-- - -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- - -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 149 -MT_MB L1_PUTX_old 177 -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 6697 -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 925 -MT_MB MEM_Inv 0 <-- - -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- - -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- - -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- - -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1723 - memory_reads: 906 - memory_writes: 817 - memory_refreshes: 803 - memory_total_request_delays: 1221 - memory_delays_per_request: 0.708648 - memory_delays_in_input_queue: 188 - memory_delays_behind_head_of_bank_queue: 7 - memory_delays_stalled_at_head_of_bank_queue: 1026 - memory_stalls_for_bank_busy: 216 +NP L1_GET_INSTR [41 ] 41 +NP L1_GETS [47 ] 47 +NP L1_GETX [779 ] 779 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [93 ] 93 + +SS L1_GET_INSTR [0 ] 0 +SS L1_GETS [0 ] 0 +SS L1_GETX [5 ] 5 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [41 ] 41 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [6 ] 6 +M L1_GETS [1 ] 1 +M L1_GETX [22 ] 22 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [328 ] 328 +M L2_Replacement_clean [22 ] 22 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [379 ] 379 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L2_Replacement_clean [472 ] 472 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [1 ] 1 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [1 ] 1 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [140 ] 140 +M_I Mem_Ack [861 ] 861 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [0 ] 0 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [0 ] 0 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [167 ] 167 +MCT_I WB_Data [447 ] 447 +MCT_I WB_Data_clean [22 ] 22 +MCT_I Ack_all [3 ] 3 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [40 ] 40 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [376 ] 376 +ISS Mem_Data [47 ] 47 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [1234 ] 1234 +IS Mem_Data [41 ] 41 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [5858 ] 5858 +IM Mem_Data [777 ] 777 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [5 ] 5 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [189 ] 189 +MT_MB L1_PUTX_old [1566 ] 1566 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [8618 ] 8618 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [847 ] 847 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1641 + memory_reads: 867 + memory_writes: 774 + memory_refreshes: 755 + memory_total_request_delays: 1219 + memory_delays_per_request: 0.74284 + memory_delays_in_input_queue: 205 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 1014 + memory_stalls_for_bank_busy: 156 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 86 - memory_stalls_for_bus: 387 + memory_stalls_for_arbitration: 89 + memory_stalls_for_bus: 403 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 251 - memory_stalls_for_read_read_turnaround: 86 - accesses_per_bank: 63 53 48 94 79 59 62 65 55 57 52 50 48 47 45 40 39 56 50 45 64 47 43 53 58 51 52 54 52 47 50 45 + memory_stalls_for_read_write_turnaround: 288 + memory_stalls_for_read_read_turnaround: 78 + accesses_per_bank: 54 61 46 85 55 63 50 44 52 43 42 47 32 53 58 44 49 60 55 44 56 46 52 48 42 68 40 47 41 48 61 55 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 906 -Data 817 -Memory_Data 906 -Memory_Ack 817 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 84 +Fetch [867 ] 867 +Data [774 ] 774 +Memory_Data [866 ] 866 +Memory_Ack [774 ] 774 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [87 ] 87 - Transitions - -I Fetch 906 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- - -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- - -M Data 817 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 84 - -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 906 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- - -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 817 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- - -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- - -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- - -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +I Fetch [867 ] 867 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [774 ] 774 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [87 ] 87 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [866 ] 866 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [774 ] 774 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE
\ No newline at end of file diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index ff895dd4e..d3d3f1d85 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:36:48 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:37:00 -M5 executing on cabr0210 +M5 compiled Aug 20 2010 11:26:07 +M5 revision 7074a6fb3b4f 7537 default qtip tip brad/regress_updates +M5 started Aug 20 2010 11:29:00 +M5 executing on SC2B0629 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 385311 because Ruby Tester completed +Exiting @ tick 362171 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 8113545a6..0b8e7d477 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208556 # Number of bytes of host memory used -host_seconds 0.90 # Real time elapsed on the host -host_tick_rate 429636 # Simulator tick rate (ticks/s) +host_mem_usage 209424 # Number of bytes of host memory used +host_seconds 0.56 # Real time elapsed on the host +host_tick_rate 645865 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000385 # Number of seconds simulated -sim_ticks 385311 # Number of ticks simulated +sim_seconds 0.000362 # Number of seconds simulated +sim_ticks 362171 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index c745e4b82..f737a2a36 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -5,10 +5,114 @@ dummy=0 [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +121,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,137 +162,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 2cfd0af56..8aa6f62e7 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:40:26 +Real time: Aug/05/2010 10:40:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 7 -Elapsed_time_in_minutes: 0.116667 -Elapsed_time_in_hours: 0.00194444 -Elapsed_time_in_days: 8.10185e-05 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 1.19 -Virtual_time_in_minutes: 0.0198333 -Virtual_time_in_hours: 0.000330556 -Virtual_time_in_days: 1.37731e-05 +Virtual_time_in_seconds: 1.03 +Virtual_time_in_minutes: 0.0171667 +Virtual_time_in_hours: 0.000286111 +Virtual_time_in_days: 1.19213e-05 -Ruby_current_time: 382981 +Ruby_current_time: 372291 Ruby_start_time: 0 -Ruby_cycles: 382981 +Ruby_cycles: 372291 -mbytes_resident: 30.7617 -mbytes_total: 203.789 -resident_ratio: 0.150987 +mbytes_resident: 31.6016 +mbytes_total: 31.6094 +resident_ratio: 1 -ruby_cycles_executed: [ 382982 ] +ruby_cycles_executed: [ 372292 ] Busy Controller Counts: L2Cache-0:0 @@ -66,13 +66,28 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 999 average: 15.8288 | standard deviation: 1.12451 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 52 933 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1034 average: 15.8404 | standard deviation: 1.10398 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 974 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 256 max: 35174 count: 984 average: 6099.68 | standard deviation: 8576.16 | 88 23 79 106 74 53 72 37 25 27 17 28 22 12 10 11 8 12 6 5 2 6 2 1 3 5 6 2 2 2 2 0 2 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 4 3 3 1 1 5 2 0 3 1 1 2 0 3 6 1 5 8 0 4 7 3 1 2 4 2 3 2 2 5 3 3 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 1 2 4 1 1 3 0 0 2 2 0 4 1 1 1 2 0 2 3 2 0 2 0 0 3 3 3 2 0 2 1 1 0 0 0 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 256 max: 34854 count: 100 average: 7109.16 | standard deviation: 10187.8 | 11 1 8 10 5 6 6 3 4 6 0 4 5 1 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 256 max: 35174 count: 884 average: 5985.48 | standard deviation: 8373.45 | 77 22 71 96 69 47 66 34 21 21 17 24 17 11 10 10 7 12 6 4 2 6 2 1 2 4 6 2 2 2 2 0 1 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 3 3 3 1 1 5 2 0 3 1 1 1 0 3 5 1 4 7 0 3 6 3 1 2 3 2 3 2 2 3 2 2 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 0 2 2 1 1 3 0 0 1 1 0 4 1 0 1 2 0 2 3 1 0 2 0 0 2 3 3 2 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_NULL: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -102,10 +117,10 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 1 +user_time: 0 system_time: 0 -page_reclaims: 8880 -page_faults: 0 +page_reclaims: 7050 +page_faults: 1907 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,1248 +128,1252 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 5430 43440 +total_msg_count_Response_Data: 5289 380808 +total_msg_count_ResponseL2hit_Data: 138 9936 +total_msg_count_Writeback_Data: 5151 370872 +total_msg_count_Writeback_Control: 11015 88120 +total_msg_count_Unblock_Control: 5419 43352 +total_msgs: 32442 total_bytes: 936528 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.084797 - links_utilized_percent_switch_0_link_0: 0.0292998 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.140294 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.0899934 + links_utilized_percent_switch_0_link_0: 0.0311114 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.148875 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 927 7416 [ 0 0 927 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152981 - links_utilized_percent_switch_1_link_0: 0.0632212 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.242741 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1837 14696 [ 895 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 863 6904 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.161841 + links_utilized_percent_switch_1_link_0: 0.0667992 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.256882 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 1796 14368 [ 923 873 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 926 7408 [ 0 0 926 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1876 15008 [ 923 874 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0719863 - links_utilized_percent_switch_2_link_0: 0.0313821 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.11259 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0757203 + links_utilized_percent_switch_2_link_0: 0.0331058 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.118335 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 857 6856 [ 0 857 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 952 7616 [ 0 873 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 873 6984 [ 0 873 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.165204 - links_utilized_percent_switch_3_link_0: 0.117199 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.252885 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.125528 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_3: 0.174693 + links_utilized_percent_switch_3_link_0: 0.124446 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.267197 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.132437 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 1796 14368 [ 923 873 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 926 7408 [ 0 0 926 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + + --- L1Cache --- - Event Counts - -Load 101 -Ifetch 0 -Store 887 -L1_Replacement 547308 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 898 -Writeback_Ack 0 -Writeback_Ack_Data 895 -Writeback_Nack 0 -All_acks 809 -Use_Timeout 897 +Load [45 ] 45 +Ifetch [149 ] 149 +Store [1075 ] 1075 +L1_Replacement [528774 ] 528774 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [927 ] 927 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [923 ] 923 +Writeback_Nack [0 ] 0 +All_acks [835 ] 835 +Use_Timeout [926 ] 926 - Transitions - -I Load 90 -I Ifetch 0 <-- -I Store 809 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M L1_Replacement 89 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L1_Replacement 3013 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 89 - -MM Load 10 -MM Ifetch 0 <-- -MM Store 66 -MM L1_Replacement 807 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- - -MM_W Load 1 -MM_W Ifetch 0 <-- -MM_W Store 9 -MM_W L1_Replacement 30209 -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 808 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 444777 -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 809 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 17359 -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 809 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 51054 -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 89 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 3 -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 895 -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +I Load [39 ] 39 +I Ifetch [53 ] 53 +I Store [836 ] 836 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [0 ] 0 +M Ifetch [2 ] 2 +M Store [0 ] 0 +M L1_Replacement [88 ] 88 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [1 ] 1 +M_W L1_Replacement [1040 ] 1040 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [90 ] 90 + +MM Load [5 ] 5 +MM Ifetch [0 ] 0 +MM Store [72 ] 72 +MM L1_Replacement [835 ] 835 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [1 ] 1 +MM_W Ifetch [0 ] 0 +MM_W Store [11 ] 11 +MM_W L1_Replacement [30786 ] 30786 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [836 ] 836 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [464217 ] 464217 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [835 ] 835 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [13588 ] 13588 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [835 ] 835 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [18220 ] 18220 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [92 ] 92 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [94 ] 94 +MI Store [155 ] 155 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [923 ] 923 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -L1_GETS 132 -L1_GETX 846 -L1_PUTO 0 -L1_PUTX 2074 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 777 -Data 777 -Data_Exclusive 86 -L1_WBCLEANDATA 85 -L1_WBDIRTYDATA 810 -Writeback_Ack 857 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 898 -L2_Replacement 857 +L1_GETS [141 ] 141 +L1_GETX [855 ] 855 +L1_PUTO [0 ] 0 +L1_PUTX [2239 ] 2239 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [795 ] 795 +Data [795 ] 795 +Data_Exclusive [86 ] 86 +L1_WBCLEANDATA [83 ] 83 +L1_WBDIRTYDATA [840 ] 840 +Writeback_Ack [873 ] 873 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [926 ] 926 +L2_Replacement [874 ] 874 - Transitions - -NP L1_GETS 86 -NP L1_GETX 777 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 895 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 3 -M L1_GETX 32 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 857 - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 85 -ILXW L1_WBDIRTYDATA 810 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 122 -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 86 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 86 -IGS L2_Replacement 0 <-- - -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 777 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 1052 -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 777 -IGMO Exclusive_Unblock 777 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 5 -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 32 -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 3 -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 43 -MI L1_GETX 37 -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 857 -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1635 - memory_reads: 863 - memory_writes: 772 - memory_refreshes: 798 - memory_total_request_delays: 689 - memory_delays_per_request: 0.421407 - memory_delays_in_input_queue: 101 - memory_delays_behind_head_of_bank_queue: 15 - memory_delays_stalled_at_head_of_bank_queue: 573 - memory_stalls_for_bank_busy: 170 +NP L1_GETS [86 ] 86 +NP L1_GETX [796 ] 796 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [923 ] 923 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [6 ] 6 +M L1_GETX [40 ] 40 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [874 ] 874 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [49 ] 49 +ILXW L1_GETX [1 ] 1 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [83 ] 83 +ILXW L1_WBDIRTYDATA [840 ] 840 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [62 ] 62 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [86 ] 86 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [85 ] 85 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [795 ] 795 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [1243 ] 1243 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [795 ] 795 +IGMO Exclusive_Unblock [795 ] 795 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [11 ] 11 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [40 ] 40 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [6 ] 6 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [18 ] 18 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [873 ] 873 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1676 + memory_reads: 882 + memory_writes: 794 + memory_refreshes: 776 + memory_total_request_delays: 684 + memory_delays_per_request: 0.408115 + memory_delays_in_input_queue: 96 + memory_delays_behind_head_of_bank_queue: 16 + memory_delays_stalled_at_head_of_bank_queue: 572 + memory_stalls_for_bank_busy: 161 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 35 + memory_stalls_for_arbitration: 32 memory_stalls_for_bus: 229 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 73 - memory_stalls_for_read_read_turnaround: 66 - accesses_per_bank: 29 65 49 82 66 72 63 36 52 53 42 57 62 51 33 45 44 34 49 49 50 37 55 51 60 45 63 61 47 41 45 47 + memory_stalls_for_read_write_turnaround: 92 + memory_stalls_for_read_read_turnaround: 58 + accesses_per_bank: 47 54 48 87 71 72 66 51 62 62 38 48 48 50 38 58 54 41 58 48 53 30 45 51 53 45 55 52 44 43 42 62 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 782 -GETS 98 -PUTX 857 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 862 -Clean_Writeback 85 -Dirty_Writeback 772 -Memory_Data 863 -Memory_Ack 772 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [807 ] 807 +GETS [86 ] 86 +PUTX [873 ] 873 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [880 ] 880 +Clean_Writeback [79 ] 79 +Dirty_Writeback [794 ] 794 +Memory_Data [882 ] 882 +Memory_Ack [793 ] 793 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 777 -I GETS 86 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 767 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -M GETX 0 <-- -M GETS 0 <-- -M PUTX 857 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 86 -IS Memory_Data 86 -IS Memory_Ack 1 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- - -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- - -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- - -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- - -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 776 -MM Memory_Data 777 -MM Memory_Ack 4 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- - - -MI GETX 5 -MI GETS 12 -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 85 -MI Dirty_Writeback 772 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- - -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- - -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- - -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- - -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- - -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- - -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +I GETX [796 ] 796 +I GETS [86 ] 86 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [791 ] 791 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [873 ] 873 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [85 ] 85 +IS Memory_Data [86 ] 86 +IS Memory_Ack [1 ] 1 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [795 ] 795 +MM Memory_Data [796 ] 796 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [11 ] 11 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [79 ] 79 +MI Dirty_Writeback [794 ] 794 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data
\ No newline at end of file diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 69ff17e18..f20a07162 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:39:50 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:40:19 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:40:24 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 382981 because Ruby Tester completed +Exiting @ tick 372291 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 020367bbd..c117a9137 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208684 # Number of bytes of host memory used -host_seconds 6.96 # Real time elapsed on the host -host_tick_rate 55013 # Simulator tick rate (ticks/s) +host_mem_usage 210064 # Number of bytes of host memory used +host_seconds 0.80 # Real time elapsed on the host +host_tick_rate 465329 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000383 # Number of seconds simulated -sim_ticks 382981 # Number of ticks simulated +sim_seconds 0.000372 # Number of seconds simulated +sim_ticks 372291 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index 6a6ab7a0f..e21f56989 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -5,10 +5,125 @@ dummy=0 [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +132,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,147 +173,34 @@ type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index d3e42a722..10b36c0bf 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:58:52 +Real time: Aug/05/2010 10:45:27 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.69 -Virtual_time_in_minutes: 0.0115 -Virtual_time_in_hours: 0.000191667 -Virtual_time_in_days: 7.98611e-06 +Virtual_time_in_seconds: 0.75 +Virtual_time_in_minutes: 0.0125 +Virtual_time_in_hours: 0.000208333 +Virtual_time_in_days: 8.68056e-06 -Ruby_current_time: 275491 +Ruby_current_time: 273851 Ruby_start_time: 0 -Ruby_cycles: 275491 +Ruby_cycles: 273851 -mbytes_resident: 30.7305 -mbytes_total: 203.652 -resident_ratio: 0.150935 +mbytes_resident: 31.5859 +mbytes_total: 31.5938 +resident_ratio: 1 -ruby_cycles_executed: [ 275492 ] +ruby_cycles_executed: [ 273852 ] Busy Controller Counts: L1Cache-0:0 @@ -66,13 +66,36 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 981 average: 15.8389 | standard deviation: 1.13074 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 39 928 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 24779 count: 966 average: 4458.37 | standard deviation: 6768.43 | 97 8 26 62 82 65 44 31 43 37 32 21 22 21 13 17 18 13 11 4 12 15 6 1 6 11 3 4 7 3 4 1 4 5 3 4 3 2 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 2 1 1 0 1 1 1 1 3 0 0 1 2 0 1 0 0 2 1 0 0 0 1 2 1 0 1 0 2 3 1 0 1 2 0 1 1 7 1 0 4 3 0 3 3 5 2 1 2 0 3 1 2 3 1 0 5 3 1 4 2 4 1 2 3 0 2 3 1 1 1 2 6 0 0 2 0 4 3 1 2 3 1 3 2 2 2 2 3 1 5 0 2 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 22427 count: 100 average: 4703.38 | standard deviation: 6898.45 | 12 2 2 7 12 6 4 3 6 3 1 1 1 3 1 2 2 0 1 0 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 2 2 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 128 max: 24779 count: 866 average: 4430.08 | standard deviation: 6756.74 | 85 6 24 55 70 59 40 28 37 34 31 20 21 18 12 15 16 13 10 4 11 13 6 1 4 11 3 4 7 3 4 1 3 5 3 3 3 1 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 1 1 1 0 1 1 1 1 3 0 0 1 1 0 1 0 0 1 1 0 0 0 1 2 1 0 1 0 2 2 1 0 1 2 0 1 1 5 1 0 2 1 0 2 3 4 1 1 2 0 2 1 1 3 1 0 5 3 1 4 1 3 1 2 3 0 1 3 1 1 1 1 5 0 0 2 0 4 3 0 2 3 1 3 2 1 2 2 3 1 5 0 1 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] +miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 902 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average: 4 | standard deviation: 0 | 0 0 0 0 1 ] +miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ] +miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] +miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -104,8 +127,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8875 -page_faults: 0 +page_reclaims: 7004 +page_faults: 1904 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,792 +136,918 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 5485 43880 +total_msg_count_Response_Data: 2871 206712 +total_msg_count_ResponseL2hit_Data: 51 3672 +total_msg_count_Response_Control: 9 72 +total_msg_count_Writeback_Data: 5349 385128 +total_msg_count_Writeback_Control: 246 1968 +total_msg_count_Persistent_Control: 2292 18336 +total_msgs: 16303 total_bytes: 659768 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.110194 - links_utilized_percent_switch_0_link_0: 0.0410177 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.179371 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 932 67104 [ 0 0 0 0 932 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.115928 + links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.092866 - links_utilized_percent_switch_1_link_0: 0.0408816 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.14485 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 729 52488 [ 0 0 0 0 729 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0997532 + links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0881086 - links_utilized_percent_switch_2_link_0: 0.0370475 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.13917 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.09541 + links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 845 60840 [ 0 0 0 0 845 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.156502 - links_utilized_percent_switch_3_link_0: 0.157791 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.163526 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.14819 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.167305 + links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 58 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 58 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 58 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 865 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.39306% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.6069% - --- L1Cache 0 --- + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 865 100% + + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 867 -L1_Replacement 395000 -Data_Shared 1 -Data_Owner 0 -Data_All_Tokens 965 -Ack 0 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 346 -Request_Timeout 545 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 867 +Load [41 ] 41 +Ifetch [59 ] 59 +Store [901 ] 901 +Atomic [0 ] 0 +L1_Replacement [388292 ] 388292 +Data_Shared [9 ] 9 +Data_Owner [2 ] 2 +Data_All_Tokens [998 ] 998 +Ack [2 ] 2 +Ack_All_Tokens [2 ] 2 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [382 ] 382 +Request_Timeout [674 ] 674 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [912 ] 912 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 88 -NP Ifetch 0 <-- -NP Store 781 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 97 -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 171 - -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M L1_Replacement 86 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 2 - -MM Load 12 -MM Ifetch 0 <-- -MM Store 74 -MM L1_Replacement 780 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 17 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L1_Replacement 2958 -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 2 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 86 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 11 -MM_W L1_Replacement 29196 -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 33 -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 781 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 329936 -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 780 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 112 -IM Request_Timeout 465 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 1 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 32044 -IS Data_Shared 1 -IS Data_Owner 0 <-- -IS Data_All_Tokens 87 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 9 -IS Request_Timeout 80 - -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- +NP Load [38 ] 38 +NP Ifetch [58 ] 58 +NP Store [826 ] 826 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [87 ] 87 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [175 ] 175 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S Load [0 ] 0 +S Ifetch [1 ] 1 +S Store [1 ] 1 +S Atomic [0 ] 0 +S L1_Replacement [8 ] 8 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M Load [0 ] 0 +M Ifetch [0 ] 0 +M Store [0 ] 0 +M Atomic [0 ] 0 +M L1_Replacement [83 ] 83 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [12 ] 12 + +MM Load [2 ] 2 +MM Ifetch [0 ] 0 +MM Store [64 ] 64 +MM Atomic [0 ] 0 +MM L1_Replacement [826 ] 826 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [27 ] 27 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [1 ] 1 +M_W Atomic [0 ] 0 +M_W L1_Replacement [1338 ] 1338 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [1 ] 1 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [85 ] 85 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +MM_W Load [1 ] 1 +MM_W Ifetch [0 ] 0 +MM_W Store [9 ] 9 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [30069 ] 30069 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [26 ] 26 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [827 ] 827 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [341249 ] 341249 +IM Data_Shared [0 ] 0 +IM Data_Owner [2 ] 2 +IM Data_All_Tokens [823 ] 823 +IM Ack [2 ] 2 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [124 ] 124 +IM Request_Timeout [608 ] 608 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [1 ] 1 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [2 ] 2 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [1 ] 1 +OM Request_Timeout [1 ] 1 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [14719 ] 14719 +IS Data_Shared [9 ] 9 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [87 ] 87 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [16 ] 16 +IS Request_Timeout [65 ] 65 + +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 + +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 + +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 906 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 9.60265% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.3974% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 906 100% + + --- L2Cache --- - Event Counts - -L1_GETS 88 -L1_GETS_Last_Token 0 -L1_GETX 782 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 781 -Writeback_Tokens 0 -Writeback_Shared_Data 0 -Writeback_All_Tokens 866 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 161 -Persistent_GETS 12 -Own_Lock_or_Unlock 173 +L1_GETS [95 ] 95 +L1_GETS_Last_Token [1 ] 1 +L1_GETX [826 ] 826 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [857 ] 857 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [8 ] 8 +Writeback_All_Tokens [908 ] 908 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [173 ] 173 +Persistent_GETS [18 ] 18 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [191 ] 191 - Transitions - -NP L1_GETS 87 -NP L1_GETX 756 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 0 <-- -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 783 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 145 - -I L1_GETS 0 <-- -I L1_GETS_Last_Token 0 <-- -I L1_GETX 0 <-- -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 30 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 24 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 1 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 0 <-- -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M L1_GETS 1 -M L1_GETX 25 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 751 -M Persistent_GETX 26 -M Persistent_GETS 2 -M Own_Lock_or_Unlock 0 <-- - -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 59 -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 135 -I_L Persistent_GETS 10 -I_L Own_Lock_or_Unlock 28 - -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1599 - memory_reads: 842 - memory_writes: 756 - memory_refreshes: 574 - memory_total_request_delays: 1024 - memory_delays_per_request: 0.6404 - memory_delays_in_input_queue: 172 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 850 - memory_stalls_for_bank_busy: 171 +NP L1_GETS [87 ] 87 +NP L1_GETX [816 ] 816 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [7 ] 7 +NP Writeback_All_Tokens [852 ] 852 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [168 ] 168 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [28 ] 28 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [1 ] 1 +I Writeback_All_Tokens [5 ] 5 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [1 ] 1 +S L1_GETX [2 ] 2 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [5 ] 5 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [7 ] 7 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [8 ] 8 +M L1_GETX [7 ] 7 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [814 ] 814 +M Persistent_GETX [26 ] 26 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [3 ] 3 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [51 ] 51 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [147 ] 147 +I_L Persistent_GETS [18 ] 18 +I_L Own_Lock_or_Unlock [23 ] 23 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1720 + memory_reads: 902 + memory_writes: 818 + memory_refreshes: 571 + memory_total_request_delays: 1302 + memory_delays_per_request: 0.756977 + memory_delays_in_input_queue: 202 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 1100 + memory_stalls_for_bank_busy: 220 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 68 - memory_stalls_for_bus: 354 + memory_stalls_for_arbitration: 97 + memory_stalls_for_bus: 424 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 184 - memory_stalls_for_read_read_turnaround: 73 - accesses_per_bank: 49 42 55 87 81 71 69 52 62 53 36 48 32 44 42 54 55 42 39 43 42 41 41 55 58 45 50 41 45 33 49 43 + memory_stalls_for_read_write_turnaround: 268 + memory_stalls_for_read_read_turnaround: 91 + accesses_per_bank: 61 42 48 69 122 69 58 56 55 51 54 41 43 47 55 55 46 45 53 50 43 51 55 52 43 56 60 54 49 40 40 57 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 771 -GETS 89 -Lockdown 173 -Unlockdown 173 -Own_Lock_or_Unlock 0 -Data_Owner 0 -Data_All_Tokens 766 -Ack_Owner 0 -Ack_Owner_All_Tokens 81 -Tokens 0 -Ack_All_Tokens 0 -Request_Timeout 0 -Memory_Data 842 -Memory_Ack 755 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [828 ] 828 +GETS [87 ] 87 +Lockdown [191 ] 191 +Unlockdown [191 ] 191 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [7 ] 7 +Data_All_Tokens [825 ] 825 +Ack_Owner [0 ] 0 +Ack_Owner_All_Tokens [76 ] 76 +Tokens [2 ] 2 +Ack_All_Tokens [3 ] 3 +Request_Timeout [0 ] 0 +Memory_Data [902 ] 902 +Memory_Ack [817 ] 817 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 751 -O GETS 87 -O Lockdown 5 -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- - -NO GETX 4 -NO GETS 0 <-- -NO Lockdown 151 -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 0 <-- -NO Data_All_Tokens 756 -NO Ack_Owner 0 <-- -NO Ack_Owner_All_Tokens 81 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -L GETX 2 -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 172 -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 10 -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- - -O_W GETX 4 -O_W GETS 2 -O_W Lockdown 1 -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 755 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- - -L_O_W GETX 10 -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 1 -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 5 -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- - -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 16 -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- - -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 16 -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 821 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- - -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- - -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- - -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- - -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- - -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- - -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- - -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- - +O GETX [811 ] 811 +O GETS [83 ] 83 +O Lockdown [6 ] 6 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [3 ] 3 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [8 ] 8 +NO GETS [4 ] 4 +NO Lockdown [168 ] 168 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [7 ] 7 +NO Data_All_Tokens [811 ] 811 +NO Ack_Owner [0 ] 0 +NO Ack_Owner_All_Tokens [76 ] 76 +NO Tokens [1 ] 1 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [189 ] 189 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [14 ] 14 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [1 ] 1 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [9 ] 9 +O_W GETS [0 ] 0 +O_W Lockdown [3 ] 3 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [1 ] 1 +O_W Memory_Ack [815 ] 815 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [2 ] 2 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [7 ] 7 +L_O_W Memory_Ack [2 ] 2 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [14 ] 14 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [14 ] 14 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [880 ] 880 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens
\ No newline at end of file diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index f528d26bf..5d4c3c605 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:58:42 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:58:52 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:45:27 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 275491 because Ruby Tester completed +Exiting @ tick 273851 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index e9b91bb36..a749dd61b 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208544 # Number of bytes of host memory used +host_mem_usage 210052 # Number of bytes of host memory used host_seconds 0.53 # Real time elapsed on the host -host_tick_rate 518969 # Simulator tick rate (ticks/s) +host_tick_rate 516678 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000275 # Number of seconds simulated -sim_ticks 275491 # Number of ticks simulated +sim_seconds 0.000274 # Number of seconds simulated +sim_ticks 273851 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 16aeab94e..24f058dce 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -5,10 +5,114 @@ dummy=0 [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +121,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,117 +162,26 @@ type=Topology children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index ee96f0f1f..57c443be3 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:59:23 +Real time: Aug/05/2010 14:46:32 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.7 -Virtual_time_in_minutes: 0.0116667 -Virtual_time_in_hours: 0.000194444 -Virtual_time_in_days: 8.10185e-06 +Virtual_time_in_seconds: 0.69 +Virtual_time_in_minutes: 0.0115 +Virtual_time_in_hours: 0.000191667 +Virtual_time_in_days: 7.98611e-06 -Ruby_current_time: 222961 +Ruby_current_time: 213851 Ruby_start_time: 0 -Ruby_cycles: 222961 +Ruby_cycles: 213851 -mbytes_resident: 30.5156 -mbytes_total: 203.461 -resident_ratio: 0.150021 +mbytes_resident: 31.293 +mbytes_total: 31.3008 +resident_ratio: 1 -ruby_cycles_executed: [ 222962 ] +ruby_cycles_executed: [ 213852 ] Busy Controller Counts: L1Cache-0:0 @@ -65,13 +65,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.7946 | standard deviation: 1.13528 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 84 899 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 23668 count: 983 average: 3530.64 | standard deviation: 5276.54 | 101 19 29 85 80 66 72 59 50 28 40 22 22 14 14 10 5 3 6 7 5 5 2 3 4 1 2 1 1 1 0 2 0 1 2 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 1 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 3 3 3 2 2 0 1 2 2 5 6 1 9 3 2 3 2 3 3 2 3 8 2 2 2 3 2 3 5 4 1 4 1 1 0 4 3 3 1 3 4 1 1 3 0 1 0 1 0 0 1 2 0 0 1 0 1 0 1 0 1 0 1 2 1 0 0 1 1 2 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 19690 count: 100 average: 3024.87 | standard deviation: 5133.9 | 15 3 2 5 6 12 9 4 5 2 7 1 5 2 1 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 128 max: 23668 count: 883 average: 3587.92 | standard deviation: 5292.25 | 86 16 27 80 74 54 63 55 45 26 33 21 17 12 13 10 3 3 5 7 5 4 2 3 4 1 2 1 1 1 0 2 0 1 1 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 0 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 2 2 3 2 2 0 1 2 2 5 6 1 9 3 2 1 2 3 3 2 3 6 1 2 2 3 1 3 5 4 1 4 1 1 0 3 2 3 1 3 3 1 1 2 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] +miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 854 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ] +miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,8 +125,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8816 -page_faults: 0 +page_reclaims: 6929 +page_faults: 1882 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -112,451 +134,665 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Request_Control: 2568 20544 +total_msg_count_Response_Data: 2562 184464 +total_msg_count_Writeback_Data: 2281 164232 +total_msg_count_Writeback_Control: 5351 42808 +total_msg_count_Unblock_Control: 2559 20472 +total_msgs: 15321 total_bytes: 432520 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.13187 - links_utilized_percent_switch_0_link_0: 0.0481867 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.215553 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.13593 + links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.123292 - links_utilized_percent_switch_1_link_0: 0.0538379 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.192747 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.127495 + links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 772 55584 [ 0 0 0 0 0 772 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.20415 - links_utilized_percent_switch_2_link_0: 0.192747 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.215553 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 889 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 889 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 9.67379% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 90.3262% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 889 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 889 average: 1.29021 | standard deviation: 0.887856 | 0 803 0 0 86 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 860 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 860 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 9.76744% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 90.2326% - - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 860 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 4 count: 860 average: 1.29302 | standard deviation: 0.89169 | 0 776 0 0 84 ] - - --- L1Cache 0 --- +links_utilized_percent_switch_2: 0.210637 + links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 57 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 57 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100% + +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 840 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 856 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100% + + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 887 -L2_Replacement 855 -L1_to_L2 318465 -L2_to_L1D 29 -L2_to_L1I 0 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 860 -Writeback_Ack 855 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 859 +Load [41 ] 41 +Ifetch [106 ] 106 +Store [906 ] 906 +L2_Replacement [849 ] 849 +L1_to_L2 [303164 ] 303164 +Trigger_L2_to_L1D [38 ] 38 +Trigger_L2_to_L1I [3 ] 3 +Complete_L2_to_L1 [41 ] 41 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [854 ] 854 +Writeback_Ack [848 ] 848 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [853 ] 853 - Transitions - -I Load 84 -I Ifetch 0 <-- -I Store 776 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- - -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 1 -M L2_Replacement 82 -M L1_to_L2 82 -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 0 <-- -M Other_GETS 0 <-- - -MM Load 16 -MM Ifetch 0 <-- -MM Store 102 -MM L2_Replacement 773 -MM L1_to_L2 804 -MM L2_to_L1D 29 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 276294 -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 776 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 1192 -M_W Ack 0 <-- -M_W All_acks_no_sharers 83 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 4 -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 11046 -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 776 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 29047 -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 84 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 4 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 855 - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: - memory_total_requests: 1632 - memory_reads: 860 - memory_writes: 772 - memory_refreshes: 465 - memory_total_request_delays: 1106 - memory_delays_per_request: 0.677696 - memory_delays_in_input_queue: 152 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 954 - memory_stalls_for_bank_busy: 245 +I Load [36 ] 36 +I Ifetch [54 ] 54 +I Store [766 ] 766 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 + +M Load [0 ] 0 +M Ifetch [1 ] 1 +M Store [1 ] 1 +M L2_Replacement [87 ] 87 +M L1_to_L2 [88 ] 88 +M Trigger_L2_to_L1D [1 ] 1 +M Trigger_L2_to_L1I [0 ] 0 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 + +MM Load [5 ] 5 +MM Ifetch [4 ] 4 +MM Store [82 ] 82 +MM L2_Replacement [762 ] 762 +MM L1_to_L2 [804 ] 804 +MM Trigger_L2_to_L1D [37 ] 37 +MM Trigger_L2_to_L1I [3 ] 3 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [275518 ] 275518 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [764 ] 764 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 + +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [483 ] 483 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [89 ] 89 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [1 ] 1 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [10887 ] 10887 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [764 ] 764 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [14644 ] 14644 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [90 ] 90 + +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [36 ] 36 +MI Store [5 ] 5 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [848 ] 848 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 + +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [10 ] 10 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [154 ] 154 +MT Complete_L2_to_L1 [1 ] 1 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [11 ] 11 +MMT Store [41 ] 41 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [586 ] 586 +MMT Complete_L2_to_L1 [40 ] 40 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1616 + memory_reads: 856 + memory_writes: 760 + memory_refreshes: 446 + memory_total_request_delays: 1108 + memory_delays_per_request: 0.685644 + memory_delays_in_input_queue: 161 + memory_delays_behind_head_of_bank_queue: 2 + memory_delays_stalled_at_head_of_bank_queue: 945 + memory_stalls_for_bank_busy: 192 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 77 - memory_stalls_for_bus: 374 + memory_stalls_for_arbitration: 83 + memory_stalls_for_bus: 395 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 150 - memory_stalls_for_read_read_turnaround: 108 - accesses_per_bank: 35 39 45 95 73 66 68 49 65 50 44 55 48 35 48 57 45 44 54 56 48 27 42 58 48 39 39 44 54 55 48 59 + memory_stalls_for_read_write_turnaround: 154 + memory_stalls_for_read_read_turnaround: 121 + accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 809 -GETS 84 -PUT 1454 -Unblock 858 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 82 -Writeback_Exclusive_Dirty 772 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 860 -Memory_Ack 772 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [770 ] 770 +GETS [91 ] 91 +PUT [909 ] 909 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [853 ] 853 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [86 ] 86 +Writeback_Exclusive_Dirty [760 ] 760 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [854 ] 854 +Memory_Ack [760 ] 760 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 855 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- - -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- - -E GETX 776 -E GETS 84 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- - -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 599 -NO_B Unblock 858 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- - -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- - -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 860 - -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- - -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- - -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- - -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- - -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- - -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- - -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- - -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- - -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- - -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- - -WB GETX 0 <-- -WB GETS 0 <-- -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 82 -WB Writeback_Exclusive_Dirty 772 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- - -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- - -WB_E_W GETX 33 -WB_E_W GETS 0 <-- -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 772 - +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 + +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [849 ] 849 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +E GETX [766 ] 766 +E GETS [90 ] 90 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 + +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [60 ] 60 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [853 ] 853 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 + +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 + +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 + +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 + +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [854 ] 854 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [2 ] 2 +WB GETS [1 ] 1 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [86 ] 86 +WB Writeback_Exclusive_Dirty [760 ] 760 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [2 ] 2 +WB_E_W GETS [0 ] 0 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index f0188e492..03174a5ad 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:59:19 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:59:22 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 14:43:33 +M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates +M5 started Aug 5 2010 14:46:32 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 222961 because Ruby Tester completed +Exiting @ tick 213851 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index e9601c124..6827d9d11 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208348 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host -host_tick_rate 420464 # Simulator tick rate (ticks/s) +host_mem_usage 209796 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host +host_tick_rate 485996 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000223 # Number of seconds simulated -sim_ticks 222961 # Number of ticks simulated +sim_seconds 0.000214 # Number of seconds simulated +sim_ticks 213851 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini index 1aee478d8..2e46bddba 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -5,10 +5,85 @@ dummy=0 [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl0.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +92,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,101 +133,26 @@ type=Topology children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index ba59ac498..4b8c316dc 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 13:52:47 +Real time: Aug/05/2010 10:10:57 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.27 -Virtual_time_in_minutes: 0.0045 -Virtual_time_in_hours: 7.5e-05 -Virtual_time_in_days: 3.125e-06 +Virtual_time_in_seconds: 0.29 +Virtual_time_in_minutes: 0.00483333 +Virtual_time_in_hours: 8.05556e-05 +Virtual_time_in_days: 3.35648e-06 Ruby_current_time: 281031 Ruby_start_time: 0 Ruby_cycles: 281031 -mbytes_resident: 30.418 -mbytes_total: 203.402 -resident_ratio: 0.149584 +mbytes_resident: 30.9531 +mbytes_total: 203.703 +resident_ratio: 0.15199 ruby_cycles_executed: [ 281032 ] @@ -70,8 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1014 average: 15.7801 All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 5702 count: 100 average: 4601.67 | standard deviation: 400.66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 0 3 1 1 3 4 5 2 3 1 2 2 1 1 5 2 0 2 2 2 5 2 2 3 1 3 3 1 5 4 4 2 3 3 1 1 3 3 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 32 max: 5245 count: 48 average: 4523.02 | standard deviation: 319.516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 32 max: 4572 count: 43 average: 3768.3 | standard deviation: 359.401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 4 1 3 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ] +miss_latency_Directory: [binsize: 32 max: 6068 count: 956 average: 4484.53 | standard deviation: 514.797 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 4 3 3 5 7 10 10 16 8 16 17 11 22 23 29 23 21 22 25 31 27 31 37 35 22 20 37 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 956 +miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average: 4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache: [binsize: 32 max: 3964 count: 1 average: 3964 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 5245 count: 47 average: 4534.91 | standard deviation: 312.044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST_L1Cache: [binsize: 32 max: 4572 count: 41 average: 3757.34 | standard deviation: 364.607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 3 1 2 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ] +miss_latency_ST_Directory: [binsize: 32 max: 6068 count: 858 average: 4469.73 | standard deviation: 524.902 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 3 3 3 5 6 10 9 15 8 14 16 10 19 19 24 21 18 21 23 29 26 30 32 33 22 18 35 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8779 +page_reclaims: 9003 page_faults: 0 swaps: 0 block_inputs: 0 @@ -112,6 +131,12 @@ block_outputs: 0 Network Stats ------------- +total_msg_count_Control: 2871 22968 +total_msg_count_Data: 2862 206064 +total_msg_count_Response_Data: 2870 206640 +total_msg_count_Writeback_Control: 2861 22888 +total_msgs: 11464 total_bytes: 458560 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.106147 @@ -145,59 +170,59 @@ links_utilized_percent_switch_2: 0.169999 outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 957 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 957 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 957 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 957 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.2403% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.7597% + system.l1_cntrl0.sequencer.icache_request_type_LD: 4.91118% + system.l1_cntrl0.sequencer.icache_request_type_ST: 89.7597% + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 5.32915% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 957 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 957 average: 1.30721 | standard deviation: 0.910193 | 0 859 0 0 98 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 957 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 900 -Data 956 -Fwd_GETX 0 -Inv 0 -Replacement 954 -Writeback_Ack 953 -Writeback_Nack 0 +Load [48 ] 48 +Ifetch [52 ] 52 +Store [900 ] 900 +Data [956 ] 956 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [954 ] 954 +Writeback_Ack [953 ] 953 +Writeback_Nack [0 ] 0 - Transitions - -I Load 98 -I Ifetch 0 <-- -I Store 859 -I Inv 0 <-- -I Replacement 0 <-- +I Load [47 ] 47 +I Ifetch [51 ] 51 +I Store [859 ] 859 +I Inv [0 ] 0 +I Replacement [0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 ] 0 -M Load 2 -M Ifetch 0 <-- -M Store 41 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 954 +M Load [1 ] 1 +M Ifetch [1 ] 1 +M Store [41 ] 41 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [954 ] 954 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 953 -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [953 ] 953 +MI Writeback_Nack [0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 ] 0 -IS Data 98 +IS Data [98 ] 98 -IM Data 858 +IM Data [858 ] 858 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1911 memory_reads: 957 memory_writes: 954 @@ -217,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 112 accesses_per_bank: 52 59 44 109 131 76 66 52 64 66 66 44 56 54 54 52 52 48 76 50 48 60 56 48 50 62 66 48 36 64 48 54 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 957 -GETS 0 -PUTX 954 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 957 -Memory_Ack 954 +GETX [957 ] 957 +GETS [0 ] 0 +PUTX [954 ] 954 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [957 ] 957 +Memory_Ack [954 ] 954 - Transitions - -I GETX 957 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 954 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 957 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 954 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [957 ] 957 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [954 ] 954 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [957 ] 957 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [954 ] 954 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 5ef371e45..566ba5c1a 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 13:52:42 -M5 revision 6a6bb24e484f 7041 default qtip tip brad/regress_updates -M5 started Mar 18 2010 13:52:46 -M5 executing on cabr0210 +M5 compiled Aug 4 2010 17:29:21 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:10:57 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 182f5ad99..104ae3de6 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208288 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 2919378 # Simulator tick rate (ticks/s) +host_mem_usage 208596 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 3195386 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_seconds 0.000281 # Number of seconds simulated sim_ticks 281031 # Number of ticks simulated |