diff options
Diffstat (limited to 'tests/quick')
30 files changed, 1913 insertions, 1036 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 56a68daea..f04692a1f 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 13 2009 01:40:41 -M5 revision 4c418376e894 6202 default tip -M5 started May 13 2009 01:40:42 +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:46 M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29437500 because target called exit() +Exiting @ tick 29521500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 577875f3a..a47f185bc 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23976 # Simulator instruction rate (inst/s) -host_mem_usage 152688 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 124659634 # Simulator tick rate (ticks/s) +host_inst_rate 29581 # Simulator instruction rate (inst/s) +host_mem_usage 155804 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 153369596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29437500 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 2055 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.predictedNotTaken 783 # Number of Branches Predicted As Not Taken (False). +sim_insts 5685 # Number of instructions simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29521500 # Number of ticks simulated +system.cpu.AGEN-Unit.instReqsProcessed 2058 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.predictedNotTaken 789 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 96 # Number of Branches Predicted As Taken (True). -system.cpu.Decode-Unit.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.instReqsProcessed 3598 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 515 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Decode-Unit.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.instReqsProcessed 3624 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 516 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 34 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed. system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Seq-Unit.instReqsProcessed 11315 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 5656 # Number of Instructions Requests that completed in this resource. +system.cpu.Fetch-Seq-Unit.instReqsProcessed 11373 # Number of Instructions Requests that completed in this resource. +system.cpu.Graduation-Unit.instReqsProcessed 5685 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 10420 # Number of Instructions Requests that completed in this resource. -system.cpu.committedInsts 5656 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5656 # Number of Instructions Simulated (Total) -system.cpu.cpi 10.409477 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.409477 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +system.cpu.RegFile-Manager.instReqsProcessed 10479 # Number of Instructions Requests that completed in this resource. +system.cpu.committedInsts 5685 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 5685 # Number of Instructions Simulated (Total) +system.cpu.cpi 10.385928 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 10.385928 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1134 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4609000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072502 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.072310 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072502 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072310 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency @@ -52,48 +52,48 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.568182 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.590909 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2058 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56359.589041 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1909 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1912 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8228500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.071046 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.070943 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 7790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071046 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.070943 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2058 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56359.589041 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1909 # number of overall hits +system.cpu.dcache.overall_hits 1912 # number of overall hits system.cpu.dcache.overall_miss_latency 8228500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.071046 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.070943 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 7790500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071046 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.070943 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.205216 # Cycle average of tags in use -system.cpu.dcache.total_refs 1923 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 84.209307 # Cycle average of tags in use +system.cpu.dcache.total_refs 1926 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 2054 # Number of Instructions Requests that completed in this resource. +system.cpu.dcache_port.instReqsProcessed 2057 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -103,62 +103,62 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55772.277228 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52772.277228 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16899000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15990000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55773.026316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52773.026316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 16043000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55772.277228 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency -system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16899000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55773.026316 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency +system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses +system.cpu.icache.demand_misses 304 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15990000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 16043000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55772.277228 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52772.277228 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55773.026316 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 16899000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_hits 5383 # number of overall hits +system.cpu.icache.overall_miss_latency 16955000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses +system.cpu.icache.overall_misses 304 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15990000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 16043000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.958324 # Cycle average of tags in use -system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.385131 # Cycle average of tags in use +system.cpu.icache.total_refs 5383 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 5657 # Number of Instructions Requests that completed in this resource. -system.cpu.ipc 0.096066 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.096066 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource. +system.cpu.ipc 0.096284 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.096284 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -177,16 +177,16 @@ system.cpu.l2cache.ReadExReq_misses 50 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52052.219321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.109661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52052.083333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.041667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19936000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15330000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 # average UpgradeReq mshr miss latency @@ -198,53 +198,53 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52103.926097 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52103.686636 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 22613000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17374000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52103.926097 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.332564 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52103.686636 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_miss_latency 22613000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 434 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17374000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.249501 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.672228 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 58876 # number of cpu cycles simulated +system.cpu.numCycles 59044 # number of cpu cycles simulated system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.threadCycles 58876 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 59044 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 9e32dcc7f..b3bdddcfe 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 5aef74b1c..9562c954f 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:05:29 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:08 -M5 executing on maize +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:46 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 13881500 because target called exit() +Exiting @ tick 13914500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 6d8206a5c..bdce7b5d3 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27478 # Simulator instruction rate (inst/s) -host_mem_usage 190884 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 75816661 # Simulator tick rate (ticks/s) +host_inst_rate 59567 # Simulator instruction rate (inst/s) +host_mem_usage 155776 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163592222 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5024 # Number of instructions simulated +sim_insts 5049 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13881500 # Number of ticks simulated +sim_ticks 13914500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 549 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1924 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 552 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1939 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 721 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1540 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2339 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 384 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 879 # Number of branches committed +system.cpu.BPredUnit.condIncorrect 722 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1555 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2357 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 387 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 885 # Number of branches committed system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14230 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.399438 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.125719 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% 82.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% 90.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% 94.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% 96.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% 98.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% 98.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% 99.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11753 82.59% 82.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1168 8.21% 90.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 499 3.51% 94.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 284 2.00% 96.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 291 2.04% 98.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 72 0.51% 98.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.44% 99.29% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% 99.56% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 63 0.44% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle -system.cpu.commit.COM:count 5655 # Number of instructions committed -system.cpu.commit.COM:loads 1130 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 14230 # Number of insts commited each cycle +system.cpu.commit.COM:count 5684 # Number of instructions committed +system.cpu.commit.COM:loads 1133 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2054 # Number of memory references committed +system.cpu.commit.COM:refs 2057 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5655 # The number of committed instructions +system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5684 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5936 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5024 # Number of Instructions Simulated -system.cpu.committedInsts_total 5024 # Number of Instructions Simulated -system.cpu.cpi 5.526274 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.526274 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2286 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33976.377953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36034.883721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2159 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4315000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.055556 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 127 # number of ReadReq misses +system.cpu.commit.commitSquashedInsts 5973 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5049 # Number of Instructions Simulated +system.cpu.committedInsts_total 5049 # Number of Instructions Simulated +system.cpu.cpi 5.511983 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.511983 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34007.812500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36022.988506 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2169 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.055725 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3099000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037620 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 86 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037875 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency @@ -73,54 +73,54 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.970370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.889706 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3210 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29612.709832 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36060 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2793 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12348500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.129907 # miss rate for demand accesses -system.cpu.dcache.demand_misses 417 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 3221 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29632.775120 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2803 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12386500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.129773 # miss rate for demand accesses +system.cpu.dcache.demand_misses 418 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5409000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.046729 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 5444000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.046880 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3210 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29612.709832 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36060 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 3221 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29632.775120 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2793 # number of overall hits -system.cpu.dcache.overall_miss_latency 12348500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.129907 # miss rate for overall accesses -system.cpu.dcache.overall_misses 417 # number of overall misses +system.cpu.dcache.overall_hits 2803 # number of overall hits +system.cpu.dcache.overall_miss_latency 12386500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.129773 # miss rate for overall accesses +system.cpu.dcache.overall_misses 418 # number of overall misses system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5409000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.046729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 5444000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.046880 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 136 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 87.531358 # Cycle average of tags in use -system.cpu.dcache.total_refs 2831 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.690614 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14141 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 9863 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3823 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1052 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 14211 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9912 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3839 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1056 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -131,116 +131,116 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2339 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2162 # Number of cache lines fetched -system.cpu.fetch.Cycles 6161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Branches 2357 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2171 # Number of cache lines fetched +system.cpu.fetch.Cycles 6187 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15261 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 737 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.084246 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Insts 15337 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 738 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.084693 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.551096 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.003336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.263199 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11225 73.77% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1766 11.61% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 196 1.29% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 137 0.90% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 314 2.06% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 113 0.74% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 304 2.00% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 249 1.64% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 913 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11277 73.77% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1770 11.58% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 198 1.30% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 138 0.90% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 316 2.07% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.75% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 306 2.00% 92.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 249 1.63% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 918 6.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 15286 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35436.489607 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1731 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15300500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.199352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 431 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 101 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_hits 1738 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15344000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.199447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.152636 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.152004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.245455 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.266667 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2162 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35500 # average overall miss latency +system.cpu.icache.demand_accesses 2171 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35436.489607 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency -system.cpu.icache.demand_hits 1731 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15300500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.199352 # miss rate for demand accesses -system.cpu.icache.demand_misses 431 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 101 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_hits 1738 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15344000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.199447 # miss rate for demand accesses +system.cpu.icache.demand_misses 433 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.152636 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.152004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2162 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35500 # average overall miss latency +system.cpu.icache.overall_accesses 2171 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35436.489607 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1731 # number of overall hits -system.cpu.icache.overall_miss_latency 15300500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.199352 # miss rate for overall accesses -system.cpu.icache.overall_misses 431 # number of overall misses -system.cpu.icache.overall_mshr_hits 101 # number of overall MSHR hits +system.cpu.icache.overall_hits 1738 # number of overall hits +system.cpu.icache.overall_miss_latency 15344000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.199447 # miss rate for overall accesses +system.cpu.icache.overall_misses 433 # number of overall misses +system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.152636 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.152004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.760808 # Cycle average of tags in use -system.cpu.icache.total_refs 1731 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 159.086288 # Cycle average of tags in use +system.cpu.icache.total_refs 1738 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12547 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:nop 1806 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.291349 # Inst execution rate -system.cpu.iew.EXEC:refs 3420 # number of memory reference insts executed +system.cpu.idleCycles 12544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1216 # Number of branches executed +system.cpu.iew.EXEC:nop 1820 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.292239 # Inst execution rate +system.cpu.iew.EXEC:refs 3432 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1048 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4016 # num instructions consuming a value -system.cpu.iew.WB:count 7315 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.694970 # average fanout of values written-back +system.cpu.iew.WB:consumers 4040 # num instructions consuming a value +system.cpu.iew.WB:count 7355 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.694802 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2791 # num instructions producing a value -system.cpu.iew.WB:rate 0.263471 # insts written-back per cycle -system.cpu.iew.WB:sent 7402 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 661 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2807 # num instructions producing a value +system.cpu.iew.WB:rate 0.264283 # insts written-back per cycle +system.cpu.iew.WB:sent 7444 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2783 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2795 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11594 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2372 # Number of load instructions executed +system.cpu.iew.iewDispatchedInsts 11660 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2384 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8089 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8133 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1052 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1056 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -250,30 +250,30 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1653 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1662 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 385 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.180954 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.180954 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 386 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.181423 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.181423 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 4988 57.87% 57.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 57.92% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 57.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2560 29.70% 87.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5020 57.94% 57.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2572 29.69% 87.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8620 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8664 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018794 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% 6.17% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.17% # attempts to use FU when none available @@ -288,30 +288,30 @@ system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15217 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566793 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217668 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72% 74.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99% 85.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17% 90.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71% 95.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18% 97.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30% 99.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11421 74.72% 74.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1678 10.98% 85.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 792 5.18% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 722 4.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 333 2.18% 97.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 200 1.31% 99.08% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% 99.68% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15217 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.310474 # Inst issue rate -system.cpu.iq.iqInstsAdded 9773 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8620 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.311319 # Inst issue rate +system.cpu.iq.iqInstsAdded 9825 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8664 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4182 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued -system.cpu.iq.iqSquashedOperandsExamined 2741 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -330,16 +330,16 @@ system.cpu.l2cache.ReadExReq_misses 49 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34308.252427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.854369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34307.506053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.750605 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14135000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990385 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12825500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990385 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12857000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency @@ -351,68 +351,68 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010076 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010050 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 465 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34350.325380 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 466 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34349.567100 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.991398 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 461 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 15869500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.991416 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 462 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14364500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.991398 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.991416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 462 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 465 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34350.325380 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 466 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34349.567100 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.991398 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 461 # number of overall misses +system.cpu.l2cache.overall_miss_latency 15869500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.991416 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 462 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14364500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.991398 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.991416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 208.689672 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 209.158769 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2795 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 27764 # number of cpu cycles simulated +system.cpu.numCycles 27830 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 3304 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10242 # Number of cycles rename is idle +system.cpu.rename.RENAME:CommittedMaps 3323 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 10291 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13384 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8214 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3446 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1052 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15666 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13454 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8251 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3462 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1056 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4910 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4928 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr index 187d1a0ac..aece78b32 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr @@ -1,23 +1,5 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout index a97b34ba7..7408d6fc9 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout @@ -5,14 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:05:29 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:09 -M5 executing on maize +M5 compiled Oct 6 2009 20:51:47 +M5 revision 300266bf68ec+ 6674+ default tip +M5 started Oct 6 2009 20:51:48 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 2828000 because target called exit() +Exiting @ tick 2842500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt index 8b9ded108..94d67cedd 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47334 # Simulator instruction rate (inst/s) -host_mem_usage 1362452 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 23634419 # Simulator tick rate (ticks/s) +host_inst_rate 27672 # Simulator instruction rate (inst/s) +host_mem_usage 1265116 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 13820616 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2828000 # Number of ticks simulated +sim_ticks 2842500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 5686 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 5d677c743..296171530 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -111,7 +111,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index b140ca5f4..77cc5d321 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:01:16 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:01:42 -M5 executing on zizzer +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:47 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 2828000 because target called exit() +Exiting @ tick 2842500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 60efc35e1..d36fc469a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 525065 # Simulator instruction rate (inst/s) -host_mem_usage 193736 # Number of bytes of host memory used +host_inst_rate 588083 # Simulator instruction rate (inst/s) +host_mem_usage 149516 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 257090909 # Simulator tick rate (ticks/s) +host_tick_rate 285563593 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2828000 # Number of ticks simulated +sim_ticks 2842500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 5686 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr index 187d1a0ac..aece78b32 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -1,23 +1,5 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout index 8519ea0e2..6c7350461 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -5,14 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:05:29 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:09 -M5 executing on maize +M5 compiled Oct 6 2009 20:43:14 +M5 revision 300266bf68ec 6674 default tip +M5 started Oct 6 2009 20:47:38 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 23131000 because target called exit() +Exiting @ tick 23227000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 95f42aecd..15c68a6b0 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8081 # Simulator instruction rate (inst/s) -host_mem_usage 1362552 # Number of bytes of host memory used -host_seconds 0.70 # Real time elapsed on the host -host_tick_rate 33041595 # Simulator tick rate (ticks/s) +host_inst_rate 3701 # Simulator instruction rate (inst/s) +host_mem_usage 1265204 # Number of bytes of host memory used +host_seconds 1.54 # Real time elapsed on the host +host_tick_rate 15119806 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23131000 # Number of ticks simulated +sim_ticks 23227000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 46262 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 46454 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 9f3729e92..2edca998b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -211,7 +211,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 7d691a50e..15331f633 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:36 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:19:48 -M5 executing on maize +M5 compiled Sep 24 2009 12:19:09 +M5 revision 9bc3e4611009+ 6661+ default tip +M5 started Sep 24 2009 12:19:31 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32322000 because target called exit() +Exiting @ tick 32409000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 8e4a1aeed..3bfaf3540 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,22 +1,22 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198393 # Simulator instruction rate (inst/s) -host_mem_usage 202876 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1123305762 # Simulator tick rate (ticks/s) +host_inst_rate 303832 # Simulator instruction rate (inst/s) +host_mem_usage 155376 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1703674499 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5685 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32322000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) +sim_ticks 32409000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1133 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1051 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.072374 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072374 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency @@ -30,45 +30,45 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.583333 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2057 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1911 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.070977 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.070977 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2057 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1908 # number of overall hits +system.cpu.dcache.overall_hits 1911 # number of overall hits system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.070977 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.070977 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use -system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.830110 # Cycle average of tags in use +system.cpu.dcache.total_refs 1925 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -80,57 +80,57 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55723.684211 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52723.684211 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16940000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 16028000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55723.684211 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency +system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16940000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses +system.cpu.icache.demand_misses 304 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 16028000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55723.684211 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_hits 5383 # number of overall hits +system.cpu.icache.overall_miss_latency 16940000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses +system.cpu.icache.overall_misses 304 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 16028000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use -system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 135.394401 # Cycle average of tags in use +system.cpu.icache.total_refs 5383 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -152,16 +152,16 @@ system.cpu.l2cache.ReadExReq_misses 50 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -173,51 +173,51 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433 # number of overall misses +system.cpu.l2cache.overall_miss_latency 22568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 434 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 182.412916 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 64644 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references +system.cpu.numCycles 64818 # number of cpu cycles simulated +system.cpu.num_insts 5685 # Number of instructions executed +system.cpu.num_refs 2058 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini new file mode 100644 index 000000000..6b0ea33cd --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -0,0 +1,389 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +UnifiedTLB=true +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=PowerTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList5.opList + +[system.cpu.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList7.opList + +[system.cpu.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=PowerTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=tests/test-progs/hello/bin/power/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr new file mode 100755 index 000000000..a2692a6c9 --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero. +For more information see: http://www.m5sim.org/warn/3a2134f6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout new file mode 100755 index 000000000..bc2c673ec --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 15 2009 15:43:13 +M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip +M5 started Oct 15 2009 15:49:09 +M5 executing on frontend01 +command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 11960500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt new file mode 100644 index 000000000..59c9aa334 --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -0,0 +1,421 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 103409 # Simulator instruction rate (inst/s) +host_mem_usage 271924 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 212174700 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5800 # Number of instructions simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11960500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 734 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1942 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 389 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1971 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2303 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 188 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 1038 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle::samples 10831 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.535500 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.248160 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 8265 76.31% 76.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1142 10.54% 86.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 659 6.08% 92.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 268 2.47% 95.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 226 2.09% 97.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 118 1.09% 98.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 80 0.74% 99.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 22 0.20% 99.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10831 # Number of insts commited each cycle +system.cpu.commit.COM:count 5800 # Number of instructions committed +system.cpu.commit.COM:loads 962 # Number of loads committed +system.cpu.commit.COM:membars 7 # Number of memory barriers committed +system.cpu.commit.COM:refs 2008 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 243 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 3801 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5800 # Number of Instructions Simulated +system.cpu.committedInsts_total 5800 # Number of Instructions Simulated +system.cpu.cpi 4.124483 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.124483 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1436 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33320.224719 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34437.500000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1347 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2965500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.061978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1928500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.038997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 33497.150997 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35861.538462 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 11757500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2331000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 20.048077 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2482 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33461.363636 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2042 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14723000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.177276 # miss rate for demand accesses +system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4259500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.048751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2042 # number of overall hits +system.cpu.dcache.overall_miss_latency 14723000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.177276 # miss rate for overall accesses +system.cpu.dcache.overall_misses 440 # number of overall misses +system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4259500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.048751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 66.056188 # Cycle average of tags in use +system.cpu.dcache.total_refs 2085 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1201 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 148 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 256 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10901 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7556 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2000 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 615 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 2303 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1463 # Number of cache lines fetched +system.cpu.fetch.Cycles 3604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12241 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 411 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.096271 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1463 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 922 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.511705 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.069457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 9306 81.30% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 148 1.29% 82.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 183 1.60% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 143 1.25% 85.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 197 1.72% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 135 1.18% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 371 3.24% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 95 0.83% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 868 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11446 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1463 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36616.094987 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34771.212121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1084 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13877500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.259057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 379 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11474500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.225564 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.284848 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1463 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36616.094987 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency +system.cpu.icache.demand_hits 1084 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13877500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.259057 # miss rate for demand accesses +system.cpu.icache.demand_misses 379 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 49 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11474500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.225564 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1084 # number of overall hits +system.cpu.icache.overall_miss_latency 13877500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.259057 # miss rate for overall accesses +system.cpu.icache.overall_misses 379 # number of overall misses +system.cpu.icache.overall_mshr_hits 49 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11474500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.225564 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 159.198376 # Cycle average of tags in use +system.cpu.icache.total_refs 1084 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 12476 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1260 # Number of branches executed +system.cpu.iew.EXEC:nop 0 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.324680 # Inst execution rate +system.cpu.iew.EXEC:refs 2768 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1280 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5977 # num instructions consuming a value +system.cpu.iew.WB:count 7563 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.643801 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 3848 # num instructions producing a value +system.cpu.iew.WB:rate 0.316152 # insts written-back per cycle +system.cpu.iew.WB:sent 7622 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1815 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1394 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9586 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 320 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7767 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 615 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 853 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 348 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.242455 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.242455 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5153 63.72% 63.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1611 19.92% 83.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1321 16.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8087 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 141 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017435 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.80% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 67 47.52% 55.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 63 44.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 11446 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.706535 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384911 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 8157 71.27% 71.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1172 10.24% 81.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 822 7.18% 88.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 530 4.63% 93.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 377 3.29% 96.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 216 1.89% 98.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 120 1.05% 99.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 43 0.38% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 11446 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.338057 # Inst issue rate +system.cpu.iq.iqInstsAdded 9564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8087 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3586 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34697.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.084656 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 12978000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 378 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11777000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 378 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34235.294118 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 582000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.022161 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34374.413146 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14643500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981567 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 426 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 13289000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 8 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14643500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981567 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 426 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 13289000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981567 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 180.652204 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1815 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1394 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23922 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 356 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7745 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 222 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 17199 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10376 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 9321 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1877 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 615 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 273 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4314 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 571 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 9 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini new file mode 100644 index 000000000..129c166c3 --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini @@ -0,0 +1,91 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +UnifiedTLB=true +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=PowerTLB +size=64 + +[system.cpu.itb] +type=PowerTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=tests/test-progs/hello/bin/power/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr new file mode 100755 index 000000000..a2692a6c9 --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero. +For more information see: http://www.m5sim.org/warn/3a2134f6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout new file mode 100755 index 000000000..410d89b19 --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 15 2009 15:43:13 +M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip +M5 started Oct 15 2009 15:49:56 +M5 executing on frontend01 +command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 2900000 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..325ee615a --- /dev/null +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 259216 # Simulator instruction rate (inst/s) +host_mem_usage 263696 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 128114508 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5801 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2900000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5801 # number of cpu cycles simulated +system.cpu.num_insts 5801 # Number of instructions executed +system.cpu.num_refs 2008 # Number of memory references +system.cpu.workload.PROG:num_syscalls 9 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index 99cec587f..b595ebc5e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -160,8 +160,10 @@ latency=30000 latency_var=0 null=false num_cpus=8 +num_dmas=1 phase=0 -range=0:134217727 +ports_per_core=2 +range=0:1073741823 stats_file=ruby.stats zero=false port=system.membus.port[8] diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 9cdd67a6e..98cf9b30f 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -12,7 +12,7 @@ RubySystem config: memory_size_bits: 30 DMA_Controller config: DMAController_0 version: 0 - buffer_size: 32 + buffer_size: 0 dma_sequencer: DMASequencer_0 number_of_TBEs: 256 recycle_latency: 10 @@ -20,18 +20,16 @@ DMA_Controller config: DMAController_0 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 - buffer_size: 32 + buffer_size: 0 directory_latency: 6 directory_name: DirectoryMemory_0 - dma_select_low_bit: 6 - dma_select_num_bits: 0 memory_controller_name: MemoryControl_0 number_of_TBEs: 256 recycle_latency: 10 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 - buffer_size: 32 + buffer_size: 0 cache: l1u_0 cache_response_latency: 12 issue_latency: 2 @@ -41,7 +39,7 @@ L1Cache_Controller config: L1CacheController_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 version: 1 - buffer_size: 32 + buffer_size: 0 cache: l1u_1 cache_response_latency: 12 issue_latency: 2 @@ -51,7 +49,7 @@ L1Cache_Controller config: L1CacheController_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 version: 2 - buffer_size: 32 + buffer_size: 0 cache: l1u_2 cache_response_latency: 12 issue_latency: 2 @@ -61,7 +59,7 @@ L1Cache_Controller config: L1CacheController_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 version: 3 - buffer_size: 32 + buffer_size: 0 cache: l1u_3 cache_response_latency: 12 issue_latency: 2 @@ -71,7 +69,7 @@ L1Cache_Controller config: L1CacheController_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 version: 4 - buffer_size: 32 + buffer_size: 0 cache: l1u_4 cache_response_latency: 12 issue_latency: 2 @@ -81,7 +79,7 @@ L1Cache_Controller config: L1CacheController_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 version: 5 - buffer_size: 32 + buffer_size: 0 cache: l1u_5 cache_response_latency: 12 issue_latency: 2 @@ -91,7 +89,7 @@ L1Cache_Controller config: L1CacheController_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 version: 6 - buffer_size: 32 + buffer_size: 0 cache: l1u_6 cache_response_latency: 12 issue_latency: 2 @@ -101,7 +99,7 @@ L1Cache_Controller config: L1CacheController_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 version: 7 - buffer_size: 32 + buffer_size: 0 cache: l1u_7 cache_response_latency: 12 issue_latency: 2 @@ -111,92 +109,92 @@ L1Cache_Controller config: L1CacheController_7 transitions_per_cycle: 32 Cache config: l1u_0 controller: L1CacheController_0 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_1 controller: L1CacheController_1 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_2 controller: L1CacheController_2 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_3 controller: L1CacheController_3 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_4 controller: L1CacheController_4 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_5 controller: L1CacheController_5 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_6 controller: L1CacheController_6 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 Cache config: l1u_7 controller: L1CacheController_7 - cache_associativity: 8 - num_cache_sets_bits: 2 - num_cache_sets: 4 - cache_set_size_bytes: 256 - cache_set_size_Kbytes: 0.25 - cache_set_size_Mbytes: 0.000244141 - cache_size_bytes: 2048 - cache_size_Kbytes: 2 - cache_size_Mbytes: 0.00195312 + cache_associativity: 2 + num_cache_sets_bits: 1 + num_cache_sets: 2 + cache_set_size_bytes: 128 + cache_set_size_Kbytes: 0.125 + cache_set_size_Mbytes: 0.00012207 + cache_size_bytes: 256 + cache_size_Kbytes: 0.25 + cache_size_Mbytes: 0.000244141 DirectoryMemory Global Config: number of directory memories: 1 total memory size bytes: 1073741824 @@ -261,6 +259,10 @@ virtual_net_2: active, ordered virtual_net_3: inactive virtual_net_4: active, ordered virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive --- Begin Topology Print --- @@ -386,34 +388,34 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/11/2009 14:40:39 +Real time: Nov/18/2009 17:42:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 3281 -Elapsed_time_in_minutes: 54.6833 -Elapsed_time_in_hours: 0.911389 -Elapsed_time_in_days: 0.0379745 +Elapsed_time_in_seconds: 3924 +Elapsed_time_in_minutes: 65.4 +Elapsed_time_in_hours: 1.09 +Elapsed_time_in_days: 0.0454167 -Virtual_time_in_seconds: 2972.6 -Virtual_time_in_minutes: 49.5433 -Virtual_time_in_hours: 0.825722 -Virtual_time_in_days: 0.0344051 +Virtual_time_in_seconds: 3921.96 +Virtual_time_in_minutes: 65.366 +Virtual_time_in_hours: 1.08943 +Virtual_time_in_days: 0.0453931 -Ruby_current_time: 31749699 +Ruby_current_time: 60455259 Ruby_start_time: 1 -Ruby_cycles: 31749698 +Ruby_cycles: 60455258 -mbytes_resident: 151.695 -mbytes_total: 151.898 -resident_ratio: 0.998688 +mbytes_resident: 151.762 +mbytes_total: 2381.61 +resident_ratio: 0.0637255 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] -ruby_cycles_executed: 253997592 [ 31749699 31749699 31749699 31749699 31749699 31749699 31749699 31749699 ] +ruby_cycles_executed: 483642072 [ 60455259 60455259 60455259 60455259 60455259 60455259 60455259 60455259 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ] @@ -422,40 +424,40 @@ misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] Memory control MemoryControl_0: - memory_total_requests: 1384962 - memory_reads: 692528 - memory_writes: 692278 - memory_refreshes: 66146 - memory_total_request_delays: 423608080 - memory_delays_per_request: 305.863 - memory_delays_in_input_queue: 89056027 - memory_delays_behind_head_of_bank_queue: 254719145 - memory_delays_stalled_at_head_of_bank_queue: 79832908 - memory_stalls_for_bank_busy: 12075653 + memory_total_requests: 1497259 + memory_reads: 748631 + memory_writes: 748628 + memory_refreshes: 125949 + memory_total_request_delays: 10693878 + memory_delays_per_request: 7.1423 + memory_delays_in_input_queue: 3751785 + memory_delays_behind_head_of_bank_queue: 352863 + memory_delays_stalled_at_head_of_bank_queue: 6589230 + memory_stalls_for_bank_busy: 1322551 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 24439291 - memory_stalls_for_arbitration: 15511923 - memory_stalls_for_bus: 20392505 + memory_stalls_for_anti_starvation: 8817 + memory_stalls_for_arbitration: 1317249 + memory_stalls_for_bus: 2228686 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 5977752 - memory_stalls_for_read_read_turnaround: 1435784 - accesses_per_bank: 43368 43904 43706 43665 43508 43366 43384 43354 43590 43325 43301 43542 43264 43288 43218 43319 43219 43118 43315 43079 43237 43057 43107 43328 43242 42939 43225 42922 42943 43105 42885 43139 + memory_stalls_for_read_write_turnaround: 1350744 + memory_stalls_for_read_read_turnaround: 361183 + accesses_per_bank: 46780 46744 46842 46810 46806 46792 46736 46774 46868 46766 46784 46766 46757 46844 46764 46814 46814 46756 46796 46862 46782 46782 46770 46838 46780 46720 46750 46754 46840 46760 46788 46820 Busy Controller Counts: -L1Cache-0:0 L1Cache-1:0 L1Cache-2:1 L1Cache-3:0 L1Cache-4:0 L1Cache-5:1 L1Cache-6:0 L1Cache-7:1 +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 Directory-0:0 DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 746700 average: 11.7618 | standard deviation: 3.42904 | 0 1181 3107 5986 10114 16132 24128 33710 44657 55083 64138 69988 72441 71345 68309 64111 142270 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 749581 average: 15.7532 | standard deviation: 1.38784 | 0 475 726 892 999 1179 1408 1673 2066 2371 2666 3000 3297 3618 4065 5733 715413 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 21029 count: 746603 average: 3851.15 | standard deviation: 2350.44 | 21624 2037 3827 6735 8744 8494 7742 8727 10265 12114 13603 13888 12189 13262 16379 16977 16477 16214 17513 17457 16778 18444 19486 16712 16151 17669 18008 15987 15648 16356 15357 14058 14375 15390 13471 12148 12876 13458 11534 10630 11403 10961 9404 9160 10054 8956 7565 7967 8417 7419 6268 6810 6747 5598 5106 5611 5301 4304 4253 4461 4055 3421 3498 3461 3011 2534 2720 2664 2157 1912 2028 1911 1498 1441 1519 1315 1010 1086 1032 937 690 761 739 551 470 511 494 399 364 334 302 239 267 269 203 196 181 186 121 145 135 120 82 83 82 77 58 67 56 72 50 39 33 27 28 31 32 22 29 30 17 15 24 9 20 12 8 10 23 5 12 6 9 6 8 8 9 5 1 3 3 4 1 2 2 4 1 1 5 3 2 0 3 0 2 3 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 20539 count: 484935 average: 3851.68 | standard deviation: 2350.63 | 13904 1332 2494 4329 5749 5607 5063 5713 6766 7842 8848 9053 7883 8567 10537 10962 10638 10565 11405 11350 10806 12022 12693 10961 10540 11414 11604 10373 10192 10631 9965 9143 9337 9992 8755 7843 8355 8762 7428 6918 7435 7161 6157 5981 6496 5813 4849 5172 5493 4828 4049 4428 4328 3623 3316 3646 3442 2848 2798 2919 2659 2252 2225 2229 1937 1638 1781 1744 1433 1232 1308 1290 987 935 1010 866 664 696 662 603 432 499 463 350 290 332 316 246 240 209 206 142 174 178 129 124 108 122 77 99 92 77 54 48 58 48 32 42 37 50 33 28 24 17 20 23 25 15 22 20 14 10 13 5 16 9 5 5 14 3 7 3 2 4 4 5 6 4 1 3 3 3 0 1 2 3 0 1 4 1 0 0 3 0 2 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 128 max: 21029 count: 261668 average: 3850.17 | standard deviation: 2350.1 | 7720 705 1333 2406 2995 2887 2679 3014 3499 4272 4755 4835 4306 4695 5842 6015 5839 5649 6108 6107 5972 6422 6793 5751 5611 6255 6404 5614 5456 5725 5392 4915 5038 5398 4716 4305 4521 4696 4106 3712 3968 3800 3247 3179 3558 3143 2716 2795 2924 2591 2219 2382 2419 1975 1790 1965 1859 1456 1455 1542 1396 1169 1273 1232 1074 896 939 920 724 680 720 621 511 506 509 449 346 390 370 334 258 262 276 201 180 179 178 153 124 125 96 97 93 91 74 72 73 64 44 46 43 43 28 35 24 29 26 25 19 22 17 11 9 10 8 8 7 7 7 10 3 5 11 4 4 3 3 5 9 2 5 3 7 2 4 3 3 1 0 0 0 1 1 1 0 1 1 0 1 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 16 max: 2089 count: 749568 average: 1269.27 | standard deviation: 184.346 | 706 46 2 38 9 9 11 1 3 18 234 183 253 263 195 167 114 113 80 74 124 134 192 223 283 302 368 333 358 349 310 281 264 303 303 313 381 411 416 435 426 499 501 538 535 532 518 525 525 512 542 549 555 659 781 726 1112 1090 2204 3346 2562 5313 3505 7093 8407 5152 11332 6998 16292 21050 13121 29097 16803 34587 35992 18551 36492 19051 36733 37381 19033 37972 19036 35937 33738 16101 29532 14057 25324 22428 10173 18224 7932 13852 11409 4860 8441 3641 6175 4984 2172 3417 1391 2332 1751 697 1089 457 745 556 215 291 123 215 137 63 94 40 57 28 9 19 5 8 5 5 4 2 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 16 max: 2059 count: 487448 average: 1269.28 | standard deviation: 183.834 | 432 31 2 21 7 7 8 1 1 8 150 118 169 171 119 101 77 70 54 51 73 78 128 142 175 205 218 217 223 230 208 191 173 202 219 188 238 265 274 281 284 338 317 343 345 351 350 322 342 355 341 355 368 421 494 491 737 709 1423 2160 1690 3504 2280 4639 5415 3375 7314 4535 10511 13782 8565 18932 10987 22355 23465 12092 23641 12545 24045 24209 12417 24627 12375 23363 21911 10475 19320 9131 16506 14610 6581 11831 5169 8995 7363 3196 5492 2339 3969 3226 1448 2182 890 1520 1118 446 700 293 484 359 146 173 86 141 81 42 61 28 39 21 7 13 3 7 2 3 3 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 16 max: 2089 count: 262120 average: 1269.26 | standard deviation: 185.295 | 274 15 0 17 2 2 3 0 2 10 84 65 84 92 76 66 37 43 26 23 51 56 64 81 108 97 150 116 135 119 102 90 91 101 84 125 143 146 142 154 142 161 184 195 190 181 168 203 183 157 201 194 187 238 287 235 375 381 781 1186 872 1809 1225 2454 2992 1777 4018 2463 5781 7268 4556 10165 5816 12232 12527 6459 12851 6506 12688 13172 6616 13345 6661 12574 11827 5626 10212 4926 8818 7818 3592 6393 2763 4857 4046 1664 2949 1302 2206 1758 724 1235 501 812 633 251 389 164 261 197 69 118 37 74 56 21 33 12 18 7 2 6 2 1 3 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -469,22 +471,26 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 34 count: 1493362 average: 0.00198612 | standard deviation: 0.174419 | 1493159 0 2 0 0 0 4 0 2 0 15 0 25 0 45 0 77 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 34 count: 1493362 average: 0.00198612 | standard deviation: 0.174419 | 1493159 0 2 0 0 0 4 0 2 0 15 0 25 0 45 0 77 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 0 count: 1497256 average: 0 | standard deviation: 0 | 1497256 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1497256 average: 0 | standard deviation: 0 | 1497256 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 746603 average: 0 | standard deviation: 0 | 746603 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 34 count: 746759 average: 0.00397183 | standard deviation: 0.246637 | 746556 0 2 0 0 0 4 0 2 0 15 0 25 0 45 0 77 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748630 average: 0 | standard deviation: 0 | 748630 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 748626 average: 0 | standard deviation: 0 | 748626 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 -user_time: 2896 -system_time: 75 -page_reclaims: 38173 -page_faults: 1923 +user_time: 3921 +system_time: 0 +page_reclaims: 40455 +page_faults: 3 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -494,110 +500,74 @@ Network Stats switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0918637 - links_utilized_percent_switch_0_link_0: 0.0367355 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.146992 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.386974 + links_utilized_percent_switch_0_link_0: 0.15479 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.619159 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 93305 6717960 [ 0 93305 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 93328 746624 [ 0 0 93328 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 93321 746568 [ 93321 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 86792 6249024 [ 86792 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 6549 471528 [ 0 6549 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0918631 - links_utilized_percent_switch_1_link_0: 0.0367386 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.146988 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0 + links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 93314 6718608 [ 0 93314 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 93325 746600 [ 0 0 93325 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 93321 746568 [ 93321 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 86443 6223896 [ 86443 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 6895 496440 [ 0 6895 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0918489 - links_utilized_percent_switch_2_link_0: 0.0367347 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.146963 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0 + links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 93304 6717888 [ 0 93304 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 93317 746536 [ 0 0 93317 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 93309 746472 [ 93309 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 86441 6223752 [ 86441 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 6881 495432 [ 0 6881 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0918764 - links_utilized_percent_switch_3_link_0: 0.0367424 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.14701 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0 + links_utilized_percent_switch_3_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 93323 6719256 [ 0 93323 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 93340 746720 [ 0 0 93340 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 93330 746640 [ 93330 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 86471 6225912 [ 86471 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 6882 495504 [ 0 6882 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.091891 - links_utilized_percent_switch_4_link_0: 0.0367495 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.147032 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0 + links_utilized_percent_switch_4_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 93342 6720624 [ 0 93342 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 93350 746800 [ 0 0 93350 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 93353 746824 [ 93353 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 86738 6245136 [ 86738 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 6628 477216 [ 0 6628 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.0918769 - links_utilized_percent_switch_5_link_0: 0.0367404 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.147013 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0 + links_utilized_percent_switch_5_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 93317 6718824 [ 0 93317 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 93344 746752 [ 0 0 93344 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 93331 746648 [ 93331 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 86620 6236640 [ 86620 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 6735 484920 [ 0 6735 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.0919038 - links_utilized_percent_switch_6_link_0: 0.0367512 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.147057 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0 + links_utilized_percent_switch_6_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 93344 6720768 [ 0 93344 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 93375 747000 [ 0 0 93375 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 93353 746824 [ 93353 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 86552 6231744 [ 86552 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 6831 491832 [ 0 6831 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.0919101 - links_utilized_percent_switch_7_link_0: 0.0367549 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.147065 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0 + links_utilized_percent_switch_7_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 93354 6721488 [ 0 93354 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 93380 747040 [ 0 0 93380 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 93364 746912 [ 93364 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 86714 6243408 [ 86714 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 6674 480528 [ 0 6674 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.687008 - links_utilized_percent_switch_8_link_0: 0.27487 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 1.09915 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.386975 + links_utilized_percent_switch_8_link_0: 0.15479 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.61916 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 746682 5973456 [ 746682 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 692771 49879512 [ 692771 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 692528 49862016 [ 0 692528 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 746759 5974072 [ 0 0 746759 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 @@ -608,148 +578,106 @@ links_utilized_percent_switch_9: 0 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.227527 - links_utilized_percent_switch_10_link_0: 0.146942 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.146954 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.146939 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.146969 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.146998 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.146962 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.147005 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.14702 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 1.09948 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.123832 + links_utilized_percent_switch_10_link_0: 0.61916 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.619159 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 93305 6717960 [ 0 93305 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 93328 746624 [ 0 0 93328 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 93314 6718608 [ 0 93314 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 93325 746600 [ 0 0 93325 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 93304 6717888 [ 0 93304 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 93317 746536 [ 0 0 93317 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 93323 6719256 [ 0 93323 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 93340 746720 [ 0 0 93340 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 93342 6720624 [ 0 93342 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 93350 746800 [ 0 0 93350 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 93317 6718824 [ 0 93317 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 93344 746752 [ 0 0 93344 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 93344 6720768 [ 0 93344 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 93375 747000 [ 0 0 93375 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 93354 6721488 [ 0 93354 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 93380 747040 [ 0 0 93380 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 746682 5973456 [ 746682 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 692771 49879512 [ 692771 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 l1u_0 cache stats: - l1u_0_total_misses: 93321 - l1u_0_total_demand_misses: 93321 + l1u_0_total_misses: 748631 + l1u_0_total_demand_misses: 748631 l1u_0_total_prefetches: 0 l1u_0_total_sw_prefetches: 0 l1u_0_total_hw_prefetches: 0 l1u_0_misses_per_transaction: inf - l1u_0_request_type_LD: 65.0004% - l1u_0_request_type_ST: 34.9996% + l1u_0_request_type_LD: 65.0336% + l1u_0_request_type_ST: 34.9664% - l1u_0_access_mode_type_SupervisorMode: 93321 100% - l1u_0_request_size: [binsize: log2 max: 1 count: 93321 average: 1 | standard deviation: 0 | 0 93321 ] + l1u_0_access_mode_type_SupervisorMode: 748631 100% + l1u_0_request_size: [binsize: log2 max: 1 count: 748631 average: 1 | standard deviation: 0 | 0 748631 ] l1u_1 cache stats: - l1u_1_total_misses: 93321 - l1u_1_total_demand_misses: 93321 + l1u_1_total_misses: 0 + l1u_1_total_demand_misses: 0 l1u_1_total_prefetches: 0 l1u_1_total_sw_prefetches: 0 l1u_1_total_hw_prefetches: 0 - l1u_1_misses_per_transaction: inf + l1u_1_misses_per_transaction: nan - l1u_1_request_type_LD: 65.1536% - l1u_1_request_type_ST: 34.8464% - - l1u_1_access_mode_type_SupervisorMode: 93321 100% - l1u_1_request_size: [binsize: log2 max: 1 count: 93321 average: 1 | standard deviation: 0 | 0 93321 ] + l1u_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_2 cache stats: - l1u_2_total_misses: 93309 - l1u_2_total_demand_misses: 93309 + l1u_2_total_misses: 0 + l1u_2_total_demand_misses: 0 l1u_2_total_prefetches: 0 l1u_2_total_sw_prefetches: 0 l1u_2_total_hw_prefetches: 0 - l1u_2_misses_per_transaction: inf - - l1u_2_request_type_LD: 65.0002% - l1u_2_request_type_ST: 34.9998% + l1u_2_misses_per_transaction: nan - l1u_2_access_mode_type_SupervisorMode: 93309 100% - l1u_2_request_size: [binsize: log2 max: 1 count: 93309 average: 1 | standard deviation: 0 | 0 93309 ] + l1u_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_3 cache stats: - l1u_3_total_misses: 93330 - l1u_3_total_demand_misses: 93330 + l1u_3_total_misses: 0 + l1u_3_total_demand_misses: 0 l1u_3_total_prefetches: 0 l1u_3_total_sw_prefetches: 0 l1u_3_total_hw_prefetches: 0 - l1u_3_misses_per_transaction: inf - - l1u_3_request_type_LD: 64.663% - l1u_3_request_type_ST: 35.337% + l1u_3_misses_per_transaction: nan - l1u_3_access_mode_type_SupervisorMode: 93330 100% - l1u_3_request_size: [binsize: log2 max: 1 count: 93330 average: 1 | standard deviation: 0 | 0 93330 ] + l1u_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_4 cache stats: - l1u_4_total_misses: 93353 - l1u_4_total_demand_misses: 93353 + l1u_4_total_misses: 0 + l1u_4_total_demand_misses: 0 l1u_4_total_prefetches: 0 l1u_4_total_sw_prefetches: 0 l1u_4_total_hw_prefetches: 0 - l1u_4_misses_per_transaction: inf + l1u_4_misses_per_transaction: nan - l1u_4_request_type_LD: 65.2555% - l1u_4_request_type_ST: 34.7445% - - l1u_4_access_mode_type_SupervisorMode: 93353 100% - l1u_4_request_size: [binsize: log2 max: 1 count: 93353 average: 1 | standard deviation: 0 | 0 93353 ] + l1u_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_5 cache stats: - l1u_5_total_misses: 93331 - l1u_5_total_demand_misses: 93331 + l1u_5_total_misses: 0 + l1u_5_total_demand_misses: 0 l1u_5_total_prefetches: 0 l1u_5_total_sw_prefetches: 0 l1u_5_total_hw_prefetches: 0 - l1u_5_misses_per_transaction: inf - - l1u_5_request_type_LD: 64.7148% - l1u_5_request_type_ST: 35.2852% + l1u_5_misses_per_transaction: nan - l1u_5_access_mode_type_SupervisorMode: 93331 100% - l1u_5_request_size: [binsize: log2 max: 1 count: 93331 average: 1 | standard deviation: 0 | 0 93331 ] + l1u_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_6 cache stats: - l1u_6_total_misses: 93353 - l1u_6_total_demand_misses: 93353 + l1u_6_total_misses: 0 + l1u_6_total_demand_misses: 0 l1u_6_total_prefetches: 0 l1u_6_total_sw_prefetches: 0 l1u_6_total_hw_prefetches: 0 - l1u_6_misses_per_transaction: inf + l1u_6_misses_per_transaction: nan - l1u_6_request_type_LD: 64.916% - l1u_6_request_type_ST: 35.084% - - l1u_6_access_mode_type_SupervisorMode: 93353 100% - l1u_6_request_size: [binsize: log2 max: 1 count: 93353 average: 1 | standard deviation: 0 | 0 93353 ] + l1u_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] l1u_7 cache stats: - l1u_7_total_misses: 93364 - l1u_7_total_demand_misses: 93364 + l1u_7_total_misses: 0 + l1u_7_total_demand_misses: 0 l1u_7_total_prefetches: 0 l1u_7_total_sw_prefetches: 0 l1u_7_total_hw_prefetches: 0 - l1u_7_misses_per_transaction: inf - - l1u_7_request_type_LD: 64.9201% - l1u_7_request_type_ST: 35.0799% + l1u_7_misses_per_transaction: nan - l1u_7_access_mode_type_SupervisorMode: 93364 100% - l1u_7_request_size: [binsize: log2 max: 1 count: 93364 average: 1 | standard deviation: 0 | 0 93364 ] + l1u_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- DMA 0 --- - Event Counts - @@ -768,24 +696,24 @@ BUSY_WR Ack 0 <-- --- Directory 0 --- - Event Counts - -GETX 7453001 +GETX 748631 GETS 0 -PUTX 692359 -PUTX_NotOwner 411 +PUTX 748628 +PUTX_NotOwner 0 DMA_READ 0 DMA_WRITE 0 -Memory_Data 692528 -Memory_Ack 692273 +Memory_Data 748630 +Memory_Ack 748626 - Transitions - -I GETX 692603 +I GETX 748631 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- -M GETX 54075 -M PUTX 692359 -M PUTX_NotOwner 411 +M GETX 0 <-- +M PUTX 748628 +M PUTX_NotOwner 0 <-- M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -795,23 +723,27 @@ M_DRD PUTX 0 <-- M_DWR GETX 0 <-- M_DWR PUTX 0 <-- +M_DWRI GETX 0 <-- M_DWRI Memory_Ack 0 <-- -IM GETX 3217979 +M_DRDI GETX 0 <-- +M_DRDI Memory_Ack 0 <-- + +IM GETX 0 <-- IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 692528 +IM Memory_Data 748630 -MI GETX 3488344 +MI GETX 0 <-- MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 692273 +MI Memory_Ack 748626 ID GETX 0 <-- ID GETS 0 <-- @@ -831,289 +763,289 @@ ID_W Memory_Ack 0 <-- --- L1Cache 0 --- - Event Counts - -Load 60659 +Load 487449 Ifetch 0 -Store 32662 -Data 93305 -Fwd_GETX 6549 +Store 262120 +Data 748630 +Fwd_GETX 0 Inv 0 -Replacement 93289 -Writeback_Ack 86728 -Writeback_Nack 51 +Replacement 748628 +Writeback_Ack 748626 +Writeback_Nack 0 - Transitions - -I Load 60659 +I Load 486862 I Ifetch 0 <-- -I Store 32662 +I Store 261769 I Inv 0 <-- -I Replacement 6497 +I Replacement 0 <-- -II Writeback_Nack 51 +II Writeback_Nack 0 <-- -M Load 0 <-- +M Load 587 M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 6498 +M Store 351 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86792 +M Replacement 748628 -MI Fwd_GETX 51 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86728 +MI Writeback_Ack 748626 -IS Data 60648 +IS Data 486861 -IM Data 32657 +IM Data 261769 --- L1Cache 1 --- - Event Counts - -Load 60802 +Load 0 Ifetch 0 -Store 32519 -Data 93314 -Fwd_GETX 6895 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93289 -Writeback_Ack 86383 -Writeback_Nack 47 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60802 +I Load 0 <-- I Ifetch 0 <-- -I Store 32519 +I Store 0 <-- I Inv 0 <-- -I Replacement 6846 +I Replacement 0 <-- -II Writeback_Nack 47 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6848 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86443 +M Replacement 0 <-- -MI Fwd_GETX 47 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86383 +MI Writeback_Ack 0 <-- -IS Data 60797 +IS Data 0 <-- -IM Data 32517 +IM Data 0 <-- --- L1Cache 2 --- - Event Counts - -Load 60651 +Load 0 Ifetch 0 -Store 32658 -Data 93304 -Fwd_GETX 6881 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93277 -Writeback_Ack 86393 -Writeback_Nack 43 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60651 +I Load 0 <-- I Ifetch 0 <-- -I Store 32658 +I Store 0 <-- I Inv 0 <-- -I Replacement 6836 +I Replacement 0 <-- -II Writeback_Nack 43 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6838 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86441 +M Replacement 0 <-- -MI Fwd_GETX 43 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86393 +MI Writeback_Ack 0 <-- -IS Data 60647 +IS Data 0 <-- -IM Data 32657 +IM Data 0 <-- --- L1Cache 3 --- - Event Counts - -Load 60350 +Load 0 Ifetch 0 -Store 32980 -Data 93323 -Fwd_GETX 6882 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93298 -Writeback_Ack 86405 -Writeback_Nack 53 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60350 +I Load 0 <-- I Ifetch 0 <-- -I Store 32980 +I Store 0 <-- I Inv 0 <-- -I Replacement 6827 +I Replacement 0 <-- -II Writeback_Nack 53 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6829 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86471 +M Replacement 0 <-- -MI Fwd_GETX 53 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86405 +MI Writeback_Ack 0 <-- -IS Data 60347 +IS Data 0 <-- -IM Data 32976 +IM Data 0 <-- --- L1Cache 4 --- - Event Counts - -Load 60918 +Load 0 Ifetch 0 -Store 32435 -Data 93342 -Fwd_GETX 6628 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93321 -Writeback_Ack 86677 -Writeback_Nack 45 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60918 +I Load 0 <-- I Ifetch 0 <-- -I Store 32435 +I Store 0 <-- I Inv 0 <-- -I Replacement 6583 +I Replacement 0 <-- -II Writeback_Nack 45 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6583 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86738 +M Replacement 0 <-- -MI Fwd_GETX 45 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86677 +MI Writeback_Ack 0 <-- -IS Data 60909 +IS Data 0 <-- -IM Data 32433 +IM Data 0 <-- --- L1Cache 5 --- - Event Counts - -Load 60399 +Load 0 Ifetch 0 -Store 32932 -Data 93317 -Fwd_GETX 6735 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93299 -Writeback_Ack 86554 -Writeback_Nack 55 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60399 +I Load 0 <-- I Ifetch 0 <-- -I Store 32932 +I Store 0 <-- I Inv 0 <-- -I Replacement 6679 +I Replacement 0 <-- -II Writeback_Nack 55 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6680 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86620 +M Replacement 0 <-- -MI Fwd_GETX 55 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86554 +MI Writeback_Ack 0 <-- -IS Data 60389 +IS Data 0 <-- -IM Data 32928 +IM Data 0 <-- --- L1Cache 6 --- - Event Counts - -Load 60601 +Load 0 Ifetch 0 -Store 32752 -Data 93344 -Fwd_GETX 6831 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93321 -Writeback_Ack 86483 -Writeback_Nack 61 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60601 +I Load 0 <-- I Ifetch 0 <-- -I Store 32752 +I Store 0 <-- I Inv 0 <-- -I Replacement 6769 +I Replacement 0 <-- -II Writeback_Nack 61 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6770 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86552 +M Replacement 0 <-- -MI Fwd_GETX 61 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86483 +MI Writeback_Ack 0 <-- -IS Data 60595 +IS Data 0 <-- -IM Data 32749 +IM Data 0 <-- --- L1Cache 7 --- - Event Counts - -Load 60612 +Load 0 Ifetch 0 -Store 32752 -Data 93354 -Fwd_GETX 6674 +Store 0 +Data 0 +Fwd_GETX 0 Inv 0 -Replacement 93332 -Writeback_Ack 86650 -Writeback_Nack 56 +Replacement 0 +Writeback_Ack 0 +Writeback_Nack 0 - Transitions - -I Load 60612 +I Load 0 <-- I Ifetch 0 <-- -I Store 32752 +I Store 0 <-- I Inv 0 <-- -I Replacement 6618 +I Replacement 0 <-- -II Writeback_Nack 56 +II Writeback_Nack 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6618 +M Fwd_GETX 0 <-- M Inv 0 <-- -M Replacement 86714 +M Replacement 0 <-- -MI Fwd_GETX 56 +MI Fwd_GETX 0 <-- MI Inv 0 <-- -MI Writeback_Ack 86650 +MI Writeback_Ack 0 <-- -IS Data 60603 +IS Data 0 <-- -IM Data 32751 +IM Data 0 <-- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index af2769339..8fe2d4613 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,76 +1,76 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"] +["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024", "-C", "256", "-A", "2", "-D", "1"] print config: 1 -system.cpu4: completed 10000 read accesses @3654068 -system.cpu1: completed 10000 read accesses @3658672 -system.cpu6: completed 10000 read accesses @3667702 -system.cpu0: completed 10000 read accesses @3693712 -system.cpu2: completed 10000 read accesses @3695692 -system.cpu7: completed 10000 read accesses @3702934 -system.cpu3: completed 10000 read accesses @3713843 -system.cpu5: completed 10000 read accesses @3747976 -system.cpu4: completed 20000 read accesses @6783252 -system.cpu6: completed 20000 read accesses @6788574 -system.cpu1: completed 20000 read accesses @6811444 -system.cpu2: completed 20000 read accesses @6811575 -system.cpu7: completed 20000 read accesses @6823208 -system.cpu3: completed 20000 read accesses @6833412 -system.cpu0: completed 20000 read accesses @6842332 -system.cpu5: completed 20000 read accesses @6892128 -system.cpu4: completed 30000 read accesses @9900552 -system.cpu6: completed 30000 read accesses @9919466 -system.cpu7: completed 30000 read accesses @9934195 -system.cpu3: completed 30000 read accesses @9940524 -system.cpu2: completed 30000 read accesses @9940526 -system.cpu0: completed 30000 read accesses @9949032 -system.cpu1: completed 30000 read accesses @10008962 -system.cpu5: completed 30000 read accesses @10013847 -system.cpu0: completed 40000 read accesses @12997824 -system.cpu3: completed 40000 read accesses @13026659 -system.cpu4: completed 40000 read accesses @13029141 -system.cpu6: completed 40000 read accesses @13053052 -system.cpu7: completed 40000 read accesses @13057445 -system.cpu2: completed 40000 read accesses @13075320 -system.cpu5: completed 40000 read accesses @13152513 -system.cpu1: completed 40000 read accesses @13163064 -system.cpu3: completed 50000 read accesses @16170822 -system.cpu0: completed 50000 read accesses @16183660 -system.cpu4: completed 50000 read accesses @16197183 -system.cpu6: completed 50000 read accesses @16212971 -system.cpu7: completed 50000 read accesses @16214970 -system.cpu5: completed 50000 read accesses @16230286 -system.cpu2: completed 50000 read accesses @16247930 -system.cpu1: completed 50000 read accesses @16329114 -system.cpu3: completed 60000 read accesses @19270542 -system.cpu0: completed 60000 read accesses @19311899 -system.cpu6: completed 60000 read accesses @19330724 -system.cpu4: completed 60000 read accesses @19371866 -system.cpu5: completed 60000 read accesses @19382898 -system.cpu7: completed 60000 read accesses @19384231 -system.cpu2: completed 60000 read accesses @19408394 -system.cpu1: completed 60000 read accesses @19459020 -system.cpu3: completed 70000 read accesses @22372299 -system.cpu6: completed 70000 read accesses @22442853 -system.cpu4: completed 70000 read accesses @22471794 -system.cpu0: completed 70000 read accesses @22486932 -system.cpu7: completed 70000 read accesses @22490492 -system.cpu5: completed 70000 read accesses @22527204 -system.cpu2: completed 70000 read accesses @22582036 -system.cpu1: completed 70000 read accesses @22588150 -system.cpu3: completed 80000 read accesses @25508231 -system.cpu6: completed 80000 read accesses @25562794 -system.cpu5: completed 80000 read accesses @25572200 -system.cpu0: completed 80000 read accesses @25620392 -system.cpu7: completed 80000 read accesses @25639710 -system.cpu4: completed 80000 read accesses @25649778 -system.cpu1: completed 80000 read accesses @25686718 -system.cpu2: completed 80000 read accesses @25733199 -system.cpu3: completed 90000 read accesses @28604804 -system.cpu6: completed 90000 read accesses @28707428 -system.cpu5: completed 90000 read accesses @28713115 -system.cpu0: completed 90000 read accesses @28743912 -system.cpu4: completed 90000 read accesses @28780814 -system.cpu7: completed 90000 read accesses @28781814 -system.cpu1: completed 90000 read accesses @28787396 -system.cpu2: completed 90000 read accesses @28868162 -system.cpu3: completed 100000 read accesses @31749698 +system.cpu7: completed 10000 read accesses @7023642 +system.cpu5: completed 10000 read accesses @7028438 +system.cpu3: completed 10000 read accesses @7034626 +system.cpu1: completed 10000 read accesses @7035790 +system.cpu2: completed 10000 read accesses @7062558 +system.cpu6: completed 10000 read accesses @7078882 +system.cpu0: completed 10000 read accesses @7080455 +system.cpu4: completed 10000 read accesses @7095500 +system.cpu1: completed 20000 read accesses @12915324 +system.cpu3: completed 20000 read accesses @12958052 +system.cpu5: completed 20000 read accesses @12993554 +system.cpu2: completed 20000 read accesses @13010879 +system.cpu4: completed 20000 read accesses @13014760 +system.cpu6: completed 20000 read accesses @13031684 +system.cpu7: completed 20000 read accesses @13051162 +system.cpu0: completed 20000 read accesses @13128234 +system.cpu3: completed 30000 read accesses @18784435 +system.cpu1: completed 30000 read accesses @18859194 +system.cpu5: completed 30000 read accesses @18903265 +system.cpu7: completed 30000 read accesses @18952860 +system.cpu4: completed 30000 read accesses @18981745 +system.cpu6: completed 30000 read accesses @18987772 +system.cpu0: completed 30000 read accesses @18993365 +system.cpu2: completed 30000 read accesses @18994061 +system.cpu3: completed 40000 read accesses @24748372 +system.cpu2: completed 40000 read accesses @24758090 +system.cpu1: completed 40000 read accesses @24768884 +system.cpu7: completed 40000 read accesses @24891866 +system.cpu0: completed 40000 read accesses @24907680 +system.cpu6: completed 40000 read accesses @24933908 +system.cpu5: completed 40000 read accesses @24949374 +system.cpu4: completed 40000 read accesses @24963853 +system.cpu3: completed 50000 read accesses @30655893 +system.cpu2: completed 50000 read accesses @30705287 +system.cpu1: completed 50000 read accesses @30752130 +system.cpu0: completed 50000 read accesses @30795942 +system.cpu5: completed 50000 read accesses @30809328 +system.cpu7: completed 50000 read accesses @30857254 +system.cpu6: completed 50000 read accesses @30935432 +system.cpu4: completed 50000 read accesses @30960853 +system.cpu3: completed 60000 read accesses @36647735 +system.cpu2: completed 60000 read accesses @36648110 +system.cpu1: completed 60000 read accesses @36690971 +system.cpu7: completed 60000 read accesses @36746000 +system.cpu5: completed 60000 read accesses @36746430 +system.cpu0: completed 60000 read accesses @36840602 +system.cpu6: completed 60000 read accesses @36900332 +system.cpu4: completed 60000 read accesses @36954562 +system.cpu2: completed 70000 read accesses @42614948 +system.cpu1: completed 70000 read accesses @42616200 +system.cpu5: completed 70000 read accesses @42679549 +system.cpu7: completed 70000 read accesses @42707038 +system.cpu3: completed 70000 read accesses @42725206 +system.cpu0: completed 70000 read accesses @42774272 +system.cpu6: completed 70000 read accesses @42850956 +system.cpu4: completed 70000 read accesses @42872700 +system.cpu5: completed 80000 read accesses @48577066 +system.cpu7: completed 80000 read accesses @48608169 +system.cpu2: completed 80000 read accesses @48616581 +system.cpu1: completed 80000 read accesses @48637808 +system.cpu0: completed 80000 read accesses @48726360 +system.cpu3: completed 80000 read accesses @48754087 +system.cpu4: completed 80000 read accesses @48848416 +system.cpu6: completed 80000 read accesses @48849321 +system.cpu5: completed 90000 read accesses @54536042 +system.cpu0: completed 90000 read accesses @54536954 +system.cpu7: completed 90000 read accesses @54554538 +system.cpu1: completed 90000 read accesses @54575168 +system.cpu2: completed 90000 read accesses @54648034 +system.cpu3: completed 90000 read accesses @54719200 +system.cpu6: completed 90000 read accesses @54807510 +system.cpu4: completed 90000 read accesses @54840954 +system.cpu1: completed 100000 read accesses @60455258 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 465be4e7d..96bce5cec 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 11 2009 13:41:17 -M5 revision be123e27612f+ 6494+ default tip -M5 started Aug 11 2009 13:45:58 -M5 executing on svvint01 +M5 compiled Nov 18 2009 16:36:52 +M5 revision c1d634e76817 6798 default qtip tip brad/ruby_memtest_refresh +M5 started Nov 18 2009 16:37:05 +M5 executing on cabr0354 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31749698 because maximum number of loads reached +Exiting @ tick 60455258 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index db2f23ad9..9b0c24527 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1507496 # Number of bytes of host memory used -host_seconds 3280.71 # Real time elapsed on the host -host_tick_rate 9678 # Simulator tick rate (ticks/s) +host_mem_usage 2438776 # Number of bytes of host memory used +host_seconds 3924.24 # Real time elapsed on the host +host_tick_rate 15406 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31749698 # Number of ticks simulated +sim_seconds 0.000060 # Number of seconds simulated +sim_ticks 60455258 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99565 # number of read accesses completed -system.cpu0.num_writes 53743 # number of write accesses completed +system.cpu0.num_reads 99982 # number of read accesses completed +system.cpu0.num_writes 53168 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99657 # number of read accesses completed -system.cpu1.num_writes 53715 # number of write accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 53657 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99204 # number of read accesses completed -system.cpu2.num_writes 53874 # number of write accesses completed +system.cpu2.num_reads 99758 # number of read accesses completed +system.cpu2.num_writes 53630 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53515 # number of write accesses completed +system.cpu3.num_reads 99707 # number of read accesses completed +system.cpu3.num_writes 53628 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99473 # number of read accesses completed -system.cpu4.num_writes 53442 # number of write accesses completed +system.cpu4.num_reads 99425 # number of read accesses completed +system.cpu4.num_writes 53969 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99627 # number of read accesses completed -system.cpu5.num_writes 53511 # number of write accesses completed +system.cpu5.num_reads 99810 # number of read accesses completed +system.cpu5.num_writes 53444 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99662 # number of read accesses completed -system.cpu6.num_writes 53565 # number of write accesses completed +system.cpu6.num_reads 99532 # number of read accesses completed +system.cpu6.num_writes 53907 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99533 # number of read accesses completed -system.cpu7.num_writes 53739 # number of write accesses completed +system.cpu7.num_reads 99819 # number of read accesses completed +system.cpu7.num_writes 53668 # number of write accesses completed ---------- End Simulation Statistics ---------- |