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-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini2
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt553
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout12
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt116
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout12
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini3
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt492
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini3
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt114
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout10
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini3
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt116
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stdout10
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt116
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr2
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout12
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini2
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt816
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr4
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout12
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini2
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt499
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr2
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout12
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt116
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr2
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini2
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt248
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr6
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout10
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini2
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt194
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr4
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout10
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini2
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt822
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr8
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout10
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal1
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini2
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt488
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr4
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout10
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini3
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt116
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr2
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout10
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini4
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt1002
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/stderr146
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/stdout10
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini8
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt92
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr10
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout10
66 files changed, 3165 insertions, 3153 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index f857ba9ca..80cb33a4e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index dd4839763..684f7196b 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 665 # Number of BTB hits
-global.BPredUnit.BTBLookups 1852 # Number of BTB lookups
+global.BPredUnit.BTBHits 649 # Number of BTB hits
+global.BPredUnit.BTBLookups 1748 # Number of BTB lookups
global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted
-global.BPredUnit.lookups 2168 # Number of BP lookups
-global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target.
-host_inst_rate 54768 # Simulator instruction rate (inst/s)
-host_mem_usage 209744 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-host_tick_rate 47820234 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 112 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted
+global.BPredUnit.lookups 2108 # Number of BP lookups
+global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target.
+host_inst_rate 87257 # Simulator instruction rate (inst/s)
+host_mem_usage 198272 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 171219532 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 28 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6297 # Number of instructions simulated
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5506500 # Number of ticks simulated
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 12391500 # Number of ticks simulated
system.cpu.commit.COM:branches 1012 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 9764
+system.cpu.commit.COM:committed_per_cycle.samples 12114
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 7128 7300.29%
- 1 1385 1418.48%
- 2 452 462.93%
- 3 225 230.44%
- 4 157 160.79%
- 5 102 104.47%
- 6 106 108.56%
- 7 96 98.32%
- 8 113 115.73%
+ 0 9249 7634.97%
+ 1 1607 1326.56%
+ 2 479 395.41%
+ 3 271 223.71%
+ 4 137 113.09%
+ 5 121 99.88%
+ 6 87 71.82%
+ 7 43 35.50%
+ 8 120 99.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 1168 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2030 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit
system.cpu.committedInsts 6297 # Number of Instructions Simulated
system.cpu.committedInsts_total 6297 # Number of Instructions Simulated
-system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
+system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2117 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 503 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2058 # number of overall hits
+system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 542 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -119,103 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 2901 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 2892 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2837 # DTB hits
-system.cpu.dtb.misses 64 # DTB misses
-system.cpu.dtb.read_accesses 1842 # DTB read accesses
+system.cpu.dtb.hits 2831 # DTB hits
+system.cpu.dtb.misses 61 # DTB misses
+system.cpu.dtb.read_accesses 1821 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1799 # DTB read hits
-system.cpu.dtb.read_misses 43 # DTB read misses
-system.cpu.dtb.write_accesses 1059 # DTB write accesses
+system.cpu.dtb.read_hits 1785 # DTB read hits
+system.cpu.dtb.read_misses 36 # DTB read misses
+system.cpu.dtb.write_accesses 1071 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 1038 # DTB write hits
-system.cpu.dtb.write_misses 21 # DTB write misses
-system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched
-system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle
+system.cpu.dtb.write_hits 1046 # DTB write hits
+system.cpu.dtb.write_misses 25 # DTB write misses
+system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched
+system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 10556
+system.cpu.fetch.rateDist.samples 12970
system.cpu.fetch.rateDist.min_value 0
- 0 8192 7760.52%
- 1 236 223.57%
- 2 214 202.73%
- 3 172 162.94%
- 4 242 229.25%
- 5 149 141.15%
- 6 203 192.31%
- 7 118 111.78%
- 8 1030 975.75%
+ 0 10663 8221.28%
+ 1 241 185.81%
+ 2 214 165.00%
+ 3 169 130.30%
+ 4 208 160.37%
+ 5 163 125.67%
+ 6 215 165.77%
+ 7 128 98.69%
+ 8 969 747.11%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses
-system.cpu.icache.demand_misses 345 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1325 # number of overall hits
-system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses
-system.cpu.icache.overall_misses 345 # number of overall misses
-system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1278 # number of overall hits
+system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 426 # number of overall misses
+system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use
-system.cpu.icache.total_refs 1325 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use
+system.cpu.icache.total_refs 1278 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1365 # Number of branches executed
-system.cpu.iew.EXEC:nop 69 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate
-system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1061 # Number of stores executed
+system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1375 # Number of branches executed
+system.cpu.iew.EXEC:nop 76 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate
+system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1073 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5886 # num instructions consuming a value
-system.cpu.iew.WB:count 8407 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back
+system.cpu.iew.WB:consumers 5878 # num instructions consuming a value
+system.cpu.iew.WB:count 8512 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4386 # num instructions producing a value
-system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle
-system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 4396 # num instructions producing a value
+system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle
+system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued
+system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6020 66.28% # Type of FU issued
+ IntAlu 6072 66.72% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
@@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1973 21.72% # Type of FU issued
- MemWrite 1085 11.95% # Type of FU issued
+ MemRead 1928 21.18% # Type of FU issued
+ MemWrite 1096 12.04% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.93% # attempts to use FU when none available
+ IntAlu 2 2.15% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 72 67.29% # attempts to use FU when none available
- MemWrite 34 31.78% # attempts to use FU when none available
+ MemRead 56 60.22% # attempts to use FU when none available
+ MemWrite 35 37.63% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 10556
+system.cpu.iq.ISSUE:issued_per_cycle.samples 12970
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 6842 6481.62%
- 1 1288 1220.16%
- 2 888 841.23%
- 3 723 684.92%
- 4 456 431.98%
- 5 198 187.57%
- 6 106 100.42%
- 7 40 37.89%
- 8 15 14.21%
+ 0 8890 6854.28%
+ 1 1667 1285.27%
+ 2 1037 799.54%
+ 3 696 536.62%
+ 4 340 262.14%
+ 5 189 145.72%
+ 6 103 79.41%
+ 7 35 26.99%
+ 8 13 10.02%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate
-system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 1700 # ITB accesses
+system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate
+system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 1737 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1670 # ITB hits
-system.cpu.itb.misses 30 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles
+system.cpu.itb.hits 1704 # ITB hits
+system.cpu.itb.misses 33 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 480 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 479 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -415,29 +415,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 11014 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking
+system.cpu.numCycles 24784 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
+system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
index 5992f7131..337694eda 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7004
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 2c5a26de6..d863a4704 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 15:48:11
-M5 started Wed Jul 23 15:48:39 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:08:49 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 5506500 because target called exit()
+Exiting @ tick 12391500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 43431aef9..1ee191af5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 22e685732..7935839f7 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 65172 # Simulator instruction rate (inst/s)
-host_mem_usage 209040 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 208535003 # Simulator tick rate (ticks/s)
+host_inst_rate 496189 # Simulator instruction rate (inst/s)
+host_mem_usage 197472 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 2580329636 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6315 # Number of instructions simulated
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20250000 # Number of ticks simulated
+sim_seconds 0.000034 # Number of seconds simulated
+sim_ticks 33503000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1851 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses
system.cpu.dcache.overall_misses 179 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use
system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 862 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 6047 # number of overall hits
-system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses
system.cpu.icache.overall_misses 279 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use
system.cpu.icache.total_refs 6047 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
system.cpu.itb.hits 6326 # ITB hits
system.cpu.itb.misses 17 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -196,29 +196,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 443 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 40500 # number of cpu cycles simulated
+system.cpu.numCycles 67006 # number of cpu cycles simulated
system.cpu.num_insts 6315 # Number of instructions executed
system.cpu.num_refs 2040 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
index 5992f7131..598fc86c0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7006
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index a4ec269db..90b25945e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 15:48:11
-M5 started Wed Jul 23 15:50:09 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:10:34 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 20250000 because target called exit()
+Exiting @ tick 33503000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 2971dacfa..a04865714 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -368,6 +368,7 @@ cmd=hello
cwd=
egid=100
env=
+errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
@@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index b9f64c44d..110788930 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 155 # Number of BTB hits
-global.BPredUnit.BTBLookups 639 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
+global.BPredUnit.BTBHits 198 # Number of BTB hits
+global.BPredUnit.BTBLookups 684 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 405 # Number of conditional branches predicted
-global.BPredUnit.lookups 821 # Number of BP lookups
-global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
-host_inst_rate 39438 # Simulator instruction rate (inst/s)
-host_mem_usage 151264 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 44410086 # Simulator tick rate (ticks/s)
+global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
+global.BPredUnit.lookups 859 # Number of BP lookups
+global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
+host_inst_rate 67408 # Simulator instruction rate (inst/s)
+host_mem_usage 197188 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 201701674 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2700000 # Number of ticks simulated
+sim_seconds 0.000007 # Number of seconds simulated
+sim_ticks 7183000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 4866
+system.cpu.commit.COM:committed_per_cycle.samples 6196
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3922 8060.01%
- 1 255 524.04%
- 2 327 672.01%
- 3 133 273.33%
- 4 67 137.69%
- 5 70 143.86%
- 6 33 67.82%
- 7 20 41.10%
- 8 39 80.15%
+ 0 5239 8455.46%
+ 1 263 424.47%
+ 2 334 539.06%
+ 3 134 216.27%
+ 4 73 117.82%
+ 5 63 101.68%
+ 6 32 51.65%
+ 7 20 32.28%
+ 8 38 61.33%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 709 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses
+system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 663 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 173 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_hits 674 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 193 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use
-system.cpu.dcache.total_refs 694 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use
+system.cpu.dcache.total_refs 715 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 936 # DTB accesses
+system.cpu.dtb.accesses 971 # DTB accesses
system.cpu.dtb.acv 1 # DTB access violations
-system.cpu.dtb.hits 911 # DTB hits
+system.cpu.dtb.hits 946 # DTB hits
system.cpu.dtb.misses 25 # DTB misses
-system.cpu.dtb.read_accesses 578 # DTB read accesses
+system.cpu.dtb.read_accesses 611 # DTB read accesses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_hits 567 # DTB read hits
+system.cpu.dtb.read_hits 600 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
-system.cpu.dtb.write_accesses 358 # DTB write accesses
+system.cpu.dtb.write_accesses 360 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 344 # DTB write hits
+system.cpu.dtb.write_hits 346 # DTB write hits
system.cpu.dtb.write_misses 14 # DTB write misses
-system.cpu.fetch.Branches 821 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 705 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle
+system.cpu.fetch.Branches 859 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 747 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 5157
+system.cpu.fetch.rateDist.samples 6528
system.cpu.fetch.rateDist.min_value 0
- 0 4266 8272.25%
- 1 34 65.93%
- 2 85 164.82%
- 3 67 129.92%
- 4 115 223.00%
- 5 55 106.65%
- 6 41 79.50%
- 7 48 93.08%
- 8 446 864.84%
+ 0 5595 8570.77%
+ 1 36 55.15%
+ 2 100 153.19%
+ 3 69 105.70%
+ 4 130 199.14%
+ 5 72 110.29%
+ 6 45 68.93%
+ 7 48 73.53%
+ 8 433 663.30%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
-system.cpu.icache.demand_hits 500 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses
-system.cpu.icache.demand_misses 205 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
+system.cpu.icache.demand_hits 512 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses
+system.cpu.icache.demand_misses 235 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 500 # number of overall hits
-system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses
-system.cpu.icache.overall_misses 205 # number of overall misses
-system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses
+system.cpu.icache.overall_hits 512 # number of overall hits
+system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses
+system.cpu.icache.overall_misses 235 # number of overall misses
+system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use
-system.cpu.icache.total_refs 500 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use
+system.cpu.icache.total_refs 512 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 542 # Number of branches executed
-system.cpu.iew.EXEC:nop 277 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate
-system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 358 # Number of stores executed
+system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 584 # Number of branches executed
+system.cpu.iew.EXEC:nop 286 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate
+system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 360 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1788 # num instructions consuming a value
-system.cpu.iew.WB:count 3104 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1896 # num instructions consuming a value
+system.cpu.iew.WB:count 3311 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1414 # num instructions producing a value
-system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle
-system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 1509 # num instructions producing a value
+system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle
+system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued
+system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 2327 70.71% # Type of FU issued
+ IntAlu 2506 71.31% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 599 18.20% # Type of FU issued
- MemWrite 364 11.06% # Type of FU issued
+ MemRead 639 18.18% # Type of FU issued
+ MemWrite 368 10.47% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 1 2.86% # attempts to use FU when none available
+ IntAlu 1 2.94% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -309,63 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 12 34.29% # attempts to use FU when none available
- MemWrite 22 62.86% # attempts to use FU when none available
+ MemRead 11 32.35% # attempts to use FU when none available
+ MemWrite 22 64.71% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 5157
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6528
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3776 7322.09%
- 1 540 1047.12%
- 2 304 589.49%
- 3 226 438.24%
- 4 166 321.89%
- 5 89 172.58%
- 6 40 77.56%
- 7 12 23.27%
- 8 4 7.76%
+ 0 5051 7737.44%
+ 1 569 871.63%
+ 2 331 507.05%
+ 3 253 387.56%
+ 4 172 263.48%
+ 5 97 148.59%
+ 6 39 59.74%
+ 7 11 16.85%
+ 8 5 7.66%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate
-system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 734 # ITB accesses
+system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 776 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 705 # ITB hits
+system.cpu.itb.hits 747 # ITB hits
system.cpu.itb.misses 29 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -376,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 267 # number of overall misses
+system.cpu.l2cache.overall_misses 266 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -414,28 +414,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 5401 # number of cpu cycles simulated
+system.cpu.numCycles 14367 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
index 298b6fba0..19df33f11 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
@@ -1,4 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7007
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index abedce50c..c1c2d8a89 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:12:59 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:08:50 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 2700000 because target called exit()
+Exiting @ tick 7183000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 7d543f47c..d146bb3c1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -166,6 +166,7 @@ cmd=hello
cwd=
egid=100
env=
+errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
@@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index c93b1f19c..ae6876b28 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 99969 # Simulator instruction rate (inst/s)
-host_mem_usage 193012 # Number of bytes of host memory used
+host_inst_rate 96492 # Simulator instruction rate (inst/s)
+host_mem_usage 196528 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 383001655 # Simulator tick rate (ticks/s)
+host_tick_rate 644436202 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 9950000 # Number of ticks simulated
+sim_seconds 0.000017 # Number of seconds simulated
+sim_ticks 17374000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 616 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
system.cpu.dcache.overall_misses 93 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2423 # number of overall hits
-system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT
system.cpu.itb.hits 2586 # ITB hits
system.cpu.itb.misses 11 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 19900 # number of cpu cycles simulated
+system.cpu.numCycles 34748 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
index f26dcb93f..bc68d7b07 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
@@ -1,4 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
+0: system.remote_gdb.listener: listening for remote gdb on port 7004
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index d1bbc80b8..97ac18bed 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:24:22 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:07:25 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 9950000 because target called exit()
+Exiting @ tick 17374000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index e5f76a0a8..fa2de5431 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -226,6 +226,7 @@ cmd=hello
cwd=
egid=100
env=
+errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
@@ -251,7 +252,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index d3bab9d0b..c07fb7a13 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 11117 # Simulator instruction rate (inst/s)
-host_mem_usage 195308 # Number of bytes of host memory used
-host_seconds 0.51 # Real time elapsed on the host
-host_tick_rate 38035865 # Simulator tick rate (ticks/s)
+host_inst_rate 142745 # Simulator instruction rate (inst/s)
+host_mem_usage 198836 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 810420480 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
-sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 19359000 # Number of ticks simulated
+sim_seconds 0.000032 # Number of seconds simulated
+sim_ticks 32322000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1908 # number of overall hits
-system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
system.cpu.dcache.overall_misses 146 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@@ -90,13 +90,13 @@ system.cpu.dtb.write_accesses 0 # DT
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -108,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5355 # number of overall hits
-system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -147,7 +147,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -162,31 +162,31 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 38718 # number of cpu cycles simulated
+system.cpu.numCycles 64644 # number of cpu cycles simulated
system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.tlb.accesses 0 # DTB accesses
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
index 5992f7131..1ad466eb8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7007
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index 37be8fb0c..4c9c838f5 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:31:07
-M5 started Mon Jul 21 20:31:09 2008
+M5 compiled Aug 2 2008 17:07:38
+M5 started Sat Aug 2 17:07:42 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Hello World!
-Exiting @ tick 19359000 because target called exit()
+Exiting @ tick 32322000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 834e9fbf3..1194cf323 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
index 132891c92..39cffe2aa 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 56962 # Simulator instruction rate (inst/s)
-host_mem_usage 210220 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 184294275 # Simulator tick rate (ticks/s)
+host_inst_rate 288337 # Simulator instruction rate (inst/s)
+host_mem_usage 198672 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1546587822 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17315000 # Number of ticks simulated
+sim_seconds 0.000029 # Number of seconds simulated
+sim_ticks 29031000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses
system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1239 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses
system.cpu.dcache.overall_misses 150 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use
system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses
system.cpu.icache.demand_misses 257 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5127 # number of overall hits
-system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses
system.cpu.icache.overall_misses 257 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,37 +138,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use
system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -180,29 +180,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 389 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 34630 # number of cpu cycles simulated
+system.cpu.numCycles 58062 # number of cpu cycles simulated
system.cpu.num_insts 5340 # Number of instructions executed
system.cpu.num_refs 1402 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr
index 2a6ac4135..320065be7 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr
@@ -1,2 +1,2 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
index 9fab97574..85eaa5038 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 16:00:51
-M5 started Wed Jul 23 16:00:56 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:21:13
+M5 started Sat Aug 2 17:29:40 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Hello World!Exiting @ tick 17315000 because target called exit()
+Hello World!Exiting @ tick 29031000 because target called exit()
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index fc5cea346..6c266b8a4 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -413,7 +413,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
index 28f9f7577..1ece980d2 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 817 # Number of BTB hits
-global.BPredUnit.BTBLookups 4239 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 150 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1415 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 2870 # Number of conditional branches predicted
-global.BPredUnit.lookups 4960 # Number of BP lookups
-global.BPredUnit.usedRAS 590 # Number of times the RAS was used to get a target.
-host_inst_rate 59476 # Simulator instruction rate (inst/s)
-host_mem_usage 210328 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
-host_tick_rate 33433367 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 46 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 54 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2257 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 2354 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1267 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1298 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 849 # Number of BTB hits
+global.BPredUnit.BTBLookups 4531 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 176 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1493 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 2930 # Number of conditional branches predicted
+global.BPredUnit.lookups 5203 # Number of BP lookups
+global.BPredUnit.usedRAS 663 # Number of times the RAS was used to get a target.
+host_inst_rate 79876 # Simulator instruction rate (inst/s)
+host_mem_usage 198844 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+host_tick_rate 88938501 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 48 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 32 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2378 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 2381 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1235 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12595 # Number of instructions simulated
-sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 7085500 # Number of ticks simulated
+sim_seconds 0.000014 # Number of seconds simulated
+sim_ticks 14042500 # Number of ticks simulated
system.cpu.commit.COM:branches 2024 # Number of branches committed
system.cpu.commit.COM:branches_0 1012 # Number of branches committed
system.cpu.commit.COM:branches_1 1012 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 152 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 138 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 14074
+system.cpu.commit.COM:committed_per_cycle.samples 22161
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 8763 6226.37%
- 1 2528 1796.22%
- 2 1133 805.03%
- 3 504 358.11%
- 4 369 262.19%
- 5 263 186.87%
- 6 218 154.90%
- 7 144 102.32%
- 8 152 108.00%
+ 0 16399 7399.94%
+ 1 2912 1314.02%
+ 2 1246 562.25%
+ 3 587 264.88%
+ 4 387 174.63%
+ 5 231 104.24%
+ 6 170 76.71%
+ 7 91 41.06%
+ 8 138 62.27%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 12629 # Number of instructions committed
-system.cpu.commit.COM:count_0 6314 # Number of instructions committed
-system.cpu.commit.COM:count_1 6315 # Number of instructions committed
+system.cpu.commit.COM:count_0 6315 # Number of instructions committed
+system.cpu.commit.COM:count_1 6314 # Number of instructions committed
system.cpu.commit.COM:loads 2336 # Number of loads committed
system.cpu.commit.COM:loads_0 1168 # Number of loads committed
system.cpu.commit.COM:loads_1 1168 # Number of loads committed
@@ -61,133 +61,133 @@ system.cpu.commit.COM:refs_1 2030 # Nu
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1036 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1089 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 9674 # The number of squashed insts skipped by commit
-system.cpu.committedInsts_0 6297 # Number of Instructions Simulated
-system.cpu.committedInsts_1 6298 # Number of Instructions Simulated
+system.cpu.commit.commitSquashedInsts 10184 # The number of squashed insts skipped by commit
+system.cpu.committedInsts_0 6298 # Number of Instructions Simulated
+system.cpu.committedInsts_1 6297 # Number of Instructions Simulated
system.cpu.committedInsts_total 12595 # Number of Instructions Simulated
-system.cpu.cpi_0 2.250596 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 2.250238 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.125208 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3671 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 3671 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency_0 12250.889680 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10641.025641 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3390 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 3390 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3442500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 3442500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate_0 0.076546 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 281 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 281 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 86 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 86 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2075000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 2075000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.053119 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses_0 195 # number of ReadReq MSHR misses
+system.cpu.cpi_0 4.459511 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 4.460219 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.229933 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3753 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 3753 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency_0 35747.734139 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 37101.010101 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3422 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 3422 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11832500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 11832500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate_0 0.088196 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 331 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 331 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 133 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 7346000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 7346000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052758 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency_0 9093.800979 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8701.149425 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1111 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits_0 1111 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5574500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 5574500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate_0 0.355568 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 613 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses_0 613 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 439 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits_0 439 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1514000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 1514000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency_0 33945.394737 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36212.643678 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 964 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits_0 964 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 25798500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 25798500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate_0 0.440835 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 6301000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 6301000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.379412 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.933140 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5395 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 5395 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 5477 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 5477 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 10086.129754 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 34492.208983 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4501 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 4501 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 4386 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 4386 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 9017000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 9017000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 37631000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 37631000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.165709 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.199197 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_misses 894 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 894 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 1091 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 1091 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 525 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 719 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 719 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3589000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 3589000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 13647000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 13647000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.068397 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.067920 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 369 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses_0 369 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses_0 372 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 5395 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 5395 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 5477 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 5477 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 10086.129754 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 34492.208983 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 36685.483871 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4501 # number of overall hits
-system.cpu.dcache.overall_hits_0 4501 # number of overall hits
+system.cpu.dcache.overall_hits 4386 # number of overall hits
+system.cpu.dcache.overall_hits_0 4386 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 9017000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 9017000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 37631000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 37631000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.165709 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.199197 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_misses 894 # number of overall misses
-system.cpu.dcache.overall_misses_0 894 # number of overall misses
+system.cpu.dcache.overall_misses 1091 # number of overall misses
+system.cpu.dcache.overall_misses_0 1091 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 525 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 525 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 719 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 719 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3589000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 3589000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 13647000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 13647000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.068397 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.067920 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 369 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses_0 369 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 372 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses_0 372 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
@@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.replacements_0 0 # number of replacements
system.cpu.dcache.replacements_1 0 # number of replacements
-system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 223.357154 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4549 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 220.225325 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4449 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2189 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 393 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 537 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 25750 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 19285 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 4519 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1860 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 5942 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 4888 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 421 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 556 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 26407 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 32471 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 4675 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2005 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 667 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 168 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 6113 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 5817 # DTB hits
-system.cpu.dtb.misses 125 # DTB misses
-system.cpu.dtb.read_accesses 3857 # DTB read accesses
+system.cpu.dtb.hits 5960 # DTB hits
+system.cpu.dtb.misses 153 # DTB misses
+system.cpu.dtb.read_accesses 3958 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 3775 # DTB read hits
-system.cpu.dtb.read_misses 82 # DTB read misses
-system.cpu.dtb.write_accesses 2085 # DTB write accesses
+system.cpu.dtb.read_hits 3865 # DTB read hits
+system.cpu.dtb.read_misses 93 # DTB read misses
+system.cpu.dtb.write_accesses 2155 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 2042 # DTB write hits
-system.cpu.dtb.write_misses 43 # DTB write misses
-system.cpu.fetch.Branches 4960 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 3670 # Number of cache lines fetched
-system.cpu.fetch.Cycles 8581 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 538 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 28943 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1537 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.349986 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 3670 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1407 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.042266 # Number of inst fetches per cycle
+system.cpu.dtb.write_hits 2095 # DTB write hits
+system.cpu.dtb.write_misses 60 # DTB write misses
+system.cpu.fetch.Branches 5203 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 3861 # Number of cache lines fetched
+system.cpu.fetch.Cycles 8930 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 591 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 29621 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.185252 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 3861 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1512 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.054654 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 14126
+system.cpu.fetch.rateDist.samples 22207
system.cpu.fetch.rateDist.min_value 0
- 0 9265 6558.83%
- 1 397 281.04%
- 2 297 210.25%
- 3 373 264.05%
- 4 393 278.21%
- 5 288 203.88%
- 6 408 288.83%
- 7 267 189.01%
- 8 2438 1725.90%
+ 0 17188 7739.90%
+ 1 414 186.43%
+ 2 327 147.25%
+ 3 389 175.17%
+ 4 409 184.18%
+ 5 315 141.85%
+ 6 447 201.29%
+ 7 251 113.03%
+ 8 2467 1110.91%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 3670 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 3670 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency_0 10197.443182 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7726.171244 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2966 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 2966 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 7179000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 7179000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate_0 0.191826 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits_0 85 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4782500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 4782500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.168665 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 3861 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 3861 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency_0 36045.289855 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35597.896440 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3033 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 3033 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 29845500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 29845500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate_0 0.214452 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 828 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses_0 828 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits_0 210 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 21999500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 21999500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.160062 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 618 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 618 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.791599 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.907767 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 3670 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 3670 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 3861 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 3861 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 10197.443182 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 36045.289855 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 2966 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 2966 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 3033 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 3033 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 7179000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 7179000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 29845500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 29845500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.191826 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.214452 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_misses 704 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 828 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_0 828 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 85 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_0 85 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_0 210 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4782500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 4782500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 21999500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 21999500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.168665 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.160062 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 618 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 618 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 3670 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 3670 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 3861 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 3861 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 10197.443182 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 36045.289855 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 35597.896440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2966 # number of overall hits
-system.cpu.icache.overall_hits_0 2966 # number of overall hits
+system.cpu.icache.overall_hits 3033 # number of overall hits
+system.cpu.icache.overall_hits_0 3033 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 7179000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 7179000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 29845500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 29845500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.191826 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.214452 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_misses 704 # number of overall misses
-system.cpu.icache.overall_misses_0 704 # number of overall misses
+system.cpu.icache.overall_misses 828 # number of overall misses
+system.cpu.icache.overall_misses_0 828 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
-system.cpu.icache.overall_mshr_hits 85 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_0 85 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_0 210 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4782500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 4782500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 21999500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 21999500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.168665 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.160062 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 618 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 618 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
@@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 7 # number of replacements
-system.cpu.icache.replacements_0 7 # number of replacements
+system.cpu.icache.replacements 6 # number of replacements
+system.cpu.icache.replacements_0 6 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 335.078862 # Cycle average of tags in use
-system.cpu.icache.total_refs 2966 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 322.695837 # Cycle average of tags in use
+system.cpu.icache.total_refs 3033 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
-system.cpu.idleCycles 46 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 2896 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 1452 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1444 # Number of branches executed
-system.cpu.iew.EXEC:nop 125 # number of nop insts executed
+system.cpu.idleCycles 5879 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 2965 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1479 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1486 # Number of branches executed
+system.cpu.iew.EXEC:nop 135 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed
-system.cpu.iew.EXEC:nop_1 59 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.282811 # Inst execution rate
-system.cpu.iew.EXEC:refs 5961 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 2937 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 3024 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2102 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 1047 # Number of stores executed
-system.cpu.iew.EXEC:stores_1 1055 # Number of stores executed
+system.cpu.iew.EXEC:nop_1 69 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.661860 # Inst execution rate
+system.cpu.iew.EXEC:refs 6137 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 3077 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 3060 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2176 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 1094 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 1082 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 11655 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 5835 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5820 # num instructions consuming a value
-system.cpu.iew.WB:count 17454 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 8729 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 8725 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 1.541828 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.770865 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.770962 # average fanout of values written-back
+system.cpu.iew.WB:consumers 11623 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 5794 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 5829 # num instructions consuming a value
+system.cpu.iew.WB:count 17865 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 8901 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 8964 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 1.541951 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.772351 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.769600 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 8985 # num instructions producing a value
-system.cpu.iew.WB:producers_0 4498 # num instructions producing a value
-system.cpu.iew.WB:producers_1 4487 # num instructions producing a value
-system.cpu.iew.WB:rate 1.231583 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.615933 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.615651 # insts written-back per cycle
-system.cpu.iew.WB:sent 17676 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 8819 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 8857 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 1177 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4611 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 8961 # num instructions producing a value
+system.cpu.iew.WB:producers_0 4475 # num instructions producing a value
+system.cpu.iew.WB:producers_1 4486 # num instructions producing a value
+system.cpu.iew.WB:rate 0.636082 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.316919 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.319163 # insts written-back per cycle
+system.cpu.iew.WB:sent 18110 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 9029 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 9081 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 1169 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 4759 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 648 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 2565 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 22432 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 3859 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 1890 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 1969 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1127 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 18180 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 18 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 598 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2527 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 22890 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 3961 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 1983 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 1978 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 18589 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1860 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2005 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1089 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 405 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1210 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 430 # Number of stores squashed
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 57 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 70 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 1186 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 436 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 137 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.444327 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.444397 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.888724 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 9630 # Type of FU issued
+system.cpu.iew.lsq.thread.1.squashedLoads 1213 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 373 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 139 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 999 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 250 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.224240 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.224204 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.448444 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 9805 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6491 67.40% # Type of FU issued
+ IntAlu 6546 66.76% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
@@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2024 21.02% # Type of FU issued
- MemWrite 1110 11.53% # Type of FU issued
+ MemRead 2114 21.56% # Type of FU issued
+ MemWrite 1140 11.63% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 9677 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1 9829 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6446 66.61% # Type of FU issued
+ IntAlu 6612 67.27% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
@@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2105 21.75% # Type of FU issued
- MemWrite 1121 11.58% # Type of FU issued
+ MemRead 2096 21.32% # Type of FU issued
+ MemWrite 1116 11.35% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 19307 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type 19634 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
No_OpClass 4 0.02% # Type of FU issued
- IntAlu 12937 67.01% # Type of FU issued
+ IntAlu 13158 67.02% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.02% # Type of FU issued
@@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4129 21.39% # Type of FU issued
- MemWrite 2231 11.56% # Type of FU issued
+ MemRead 4210 21.44% # Type of FU issued
+ MemWrite 2256 11.49% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 191 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.009893 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.004558 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.005335 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 163 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 81 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 82 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.008302 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.004125 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.004176 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 10 5.24% # attempts to use FU when none available
+ IntAlu 10 6.13% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -543,163 +543,163 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 116 60.73% # attempts to use FU when none available
- MemWrite 65 34.03% # attempts to use FU when none available
+ MemRead 92 56.44% # attempts to use FU when none available
+ MemWrite 61 37.42% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 14126
+system.cpu.iq.ISSUE:issued_per_cycle.samples 22207
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 6647 4705.51%
- 1 2379 1684.13%
- 2 1804 1277.08%
- 3 1327 939.40%
- 4 983 695.88%
- 5 624 441.74%
- 6 265 187.60%
- 7 79 55.93%
- 8 18 12.74%
+ 0 13725 6180.48%
+ 1 3247 1462.15%
+ 2 2190 986.18%
+ 3 1374 618.72%
+ 4 899 404.83%
+ 5 454 204.44%
+ 6 231 104.02%
+ 7 63 28.37%
+ 8 24 10.81%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.362334 # Inst issue rate
-system.cpu.iq.iqInstsAdded 22262 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 19307 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.699067 # Inst issue rate
+system.cpu.iq.iqInstsAdded 22710 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 19634 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 8627 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8828 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 5151 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 3720 # ITB accesses
+system.cpu.iq.iqSquashedOperandsExamined 5121 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 3911 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 3670 # ITB hits
+system.cpu.itb.hits 3861 # ITB hits
system.cpu.itb.misses 50 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6824.137931 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3824.137931 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 989500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency_0 989500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34636.986301 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31585.616438 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5057000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency_0 5057000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 554500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 554500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4611500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4611500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 814 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 6515.413070 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3515.413070 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 5284000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 5284000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate_0 0.996314 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 2851000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2851000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996314 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6344.827586 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3344.827586 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 184000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency_0 184000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 816 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 816 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 34609.950860 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31482.800983 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 28172500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 28172500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate_0 0.997549 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 814 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 814 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25627000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997549 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 814 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 814 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34303.571429 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31178.571429 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 960500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency_0 960500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 97000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 873000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 873000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6200 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.003836 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 31000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 959 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 959 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 6562.238494 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 34614.062500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6273500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 6273500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 33229500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 33229500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0 0.996872 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0 0.997921 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 960 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_0 960 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 3405500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 3405500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 30238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 30238500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0 0.996872 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0 0.997921 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 960 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_0 960 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 959 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 959 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 6562.238494 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 34614.062500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31498.437500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.overall_hits_0 3 # number of overall hits
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_hits_0 2 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6273500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 6273500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 33229500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 33229500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0 0.996872 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0 0.997921 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 956 # number of overall misses
-system.cpu.l2cache.overall_misses_0 956 # number of overall misses
+system.cpu.l2cache.overall_misses 960 # number of overall misses
+system.cpu.l2cache.overall_misses_0 960 # number of overall misses
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3405500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 3405500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 30238500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 30238500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0 0.996872 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0 0.997921 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 960 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_0 960 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
@@ -719,34 +719,34 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 782 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 786 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 444.416250 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 433.129952 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 14172 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 760 # Number of cycles rename is blocking
+system.cpu.numCycles 28086 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2865 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 19739 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 868 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 30813 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 24390 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 18197 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 4242 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1860 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 926 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 9123 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2524 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
-system.cpu.timesIdled 15 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IdleCycles 32955 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1341 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 31504 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 25059 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 18781 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 4307 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2005 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1387 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 9707 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 688 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 3332 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed
+system.cpu.timesIdled 252 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
index 0ce82a0be..792313cca 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
@@ -1,5 +1,5 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+0: system.remote_gdb.listener: listening for remote gdb on port 7003
+0: system.remote_gdb.listener: listening for remote gdb on port 7008
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
index 1c27475d4..35ba3f4fd 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 15:48:11
-M5 started Wed Jul 23 15:49:40 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:13:24 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
Hello world!
-Exiting @ tick 7085500 because target called exit()
+Exiting @ tick 14042500 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 13cb0931f..6ee9f16a8 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
index d4ce934cb..f90003dbb 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 4364 # Number of BTB hits
-global.BPredUnit.BTBLookups 10024 # Number of BTB lookups
+global.BPredUnit.BTBHits 4398 # Number of BTB hits
+global.BPredUnit.BTBLookups 9844 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2911 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 11601 # Number of conditional branches predicted
-global.BPredUnit.lookups 11601 # Number of BP lookups
+global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted
+global.BPredUnit.lookups 11413 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 6832 # Simulator instruction rate (inst/s)
-host_mem_usage 210732 # Number of bytes of host memory used
-host_seconds 2.11 # Real time elapsed on the host
-host_tick_rate 10370738 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads.
+host_inst_rate 50656 # Simulator instruction rate (inst/s)
+host_mem_usage 199212 # Number of bytes of host memory used
+host_seconds 0.29 # Real time elapsed on the host
+host_tick_rate 97240761 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 4977 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 3503 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
-sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21933500 # Number of ticks simulated
+sim_seconds 0.000028 # Number of seconds simulated
+sim_ticks 27756500 # Number of ticks simulated
system.cpu.commit.COM:branches 3359 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 39346
+system.cpu.commit.COM:committed_per_cycle.samples 42766
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 31195 7928.38%
- 1 4789 1217.15%
- 2 1729 439.43%
- 3 717 182.23%
- 4 416 105.73%
- 5 147 37.36%
- 6 198 50.32%
- 7 50 12.71%
- 8 105 26.69%
+ 0 34594 8089.14%
+ 1 4804 1123.32%
+ 2 1741 407.10%
+ 3 720 168.36%
+ 4 413 96.57%
+ 5 144 33.67%
+ 6 196 45.83%
+ 7 51 11.93%
+ 8 103 24.08%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 2226 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 3674 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2911 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 20100 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
-system.cpu.cpi 3.036058 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.036058 # CPI: Total CPI of All Threads
+system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 9408.602151 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7113.636364 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3751 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 875000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.024194 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 93 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 469500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.017170 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 9957.589286 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1218 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2230500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.155340 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 224 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 122 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 714000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 33.590604 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 9796.529968 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4969 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 3105500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.059970 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 317 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 149 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1183500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.031782 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 9796.529968 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4969 # number of overall hits
-system.cpu.dcache.overall_miss_latency 3105500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.059970 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 317 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 149 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1183500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.031782 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 4728 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 558 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 114.768529 # Cycle average of tags in use
-system.cpu.dcache.total_refs 5005 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 5414 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 52959 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 18733 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 15067 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4338 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 132 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 11601 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 7392 # Number of cache lines fetched
-system.cpu.fetch.Cycles 24155 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 764 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 59501 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.264452 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 7392 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 4364 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.356365 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched
+system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 43684
+system.cpu.fetch.rateDist.samples 47090
system.cpu.fetch.rateDist.min_value 0
- 0 26944 6167.93%
- 1 7490 1714.59%
- 2 1209 276.76%
- 3 1044 238.99%
- 4 1055 241.51%
- 5 1191 272.64%
- 6 698 159.78%
- 7 326 74.63%
- 8 3727 853.17%
+ 0 30448 6465.92%
+ 1 7532 1599.49%
+ 2 1217 258.44%
+ 3 1059 224.89%
+ 4 1060 225.10%
+ 5 1193 253.34%
+ 6 711 150.99%
+ 7 327 69.44%
+ 8 3543 752.39%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 7392 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 8917.690418 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6472.527473 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6985 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3629500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.055060 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 407 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 2356000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.049242 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 364 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 19.189560 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 7392 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 8917.690418 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6985 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3629500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.055060 # miss rate for demand accesses
-system.cpu.icache.demand_misses 407 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2356000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.049242 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 364 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
+system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses
+system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 7392 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 8917.690418 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6985 # number of overall hits
-system.cpu.icache.overall_miss_latency 3629500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.055060 # miss rate for overall accesses
-system.cpu.icache.overall_misses 407 # number of overall misses
-system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2356000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.049242 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 364 # number of overall MSHR misses
+system.cpu.icache.overall_hits 6821 # number of overall hits
+system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses
+system.cpu.icache.overall_misses 535 # number of overall misses
+system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 364 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 247.187481 # Cycle average of tags in use
-system.cpu.icache.total_refs 6985 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use
+system.cpu.icache.total_refs 6821 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 184 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4855 # Number of branches executed
-system.cpu.iew.EXEC:nop 2093 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.570211 # Inst execution rate
-system.cpu.iew.EXEC:refs 6456 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2482 # Number of stores executed
+system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 4842 # Number of branches executed
+system.cpu.iew.EXEC:nop 2091 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate
+system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2454 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 13185 # num instructions consuming a value
-system.cpu.iew.WB:count 24031 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.826773 # average fanout of values written-back
+system.cpu.iew.WB:consumers 13039 # num instructions consuming a value
+system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10901 # num instructions producing a value
-system.cpu.iew.WB:rate 0.547802 # insts written-back per cycle
-system.cpu.iew.WB:sent 24254 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3206 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4977 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 772 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3232 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 3503 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 35402 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 3974 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4417 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 25014 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 10787 # num instructions producing a value
+system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle
+system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4338 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 58 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2751 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2055 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 58 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 769 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 2437 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.329374 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.329374 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 29431 # Type of FU issued
+system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 21547 73.21% # Type of FU issued
+ IntAlu 21395 73.22% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4739 16.10% # Type of FU issued
- MemWrite 3145 10.69% # Type of FU issued
+ MemRead 4720 16.15% # Type of FU issued
+ MemWrite 3105 10.63% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.006388 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 49 26.06% # attempts to use FU when none available
+ IntAlu 40 23.12% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -296,96 +296,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 25 13.30% # attempts to use FU when none available
- MemWrite 114 60.64% # attempts to use FU when none available
+ MemRead 20 11.56% # attempts to use FU when none available
+ MemWrite 113 65.32% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 43684
+system.cpu.iq.ISSUE:issued_per_cycle.samples 47090
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 30754 7040.11%
- 1 5431 1243.25%
- 2 3052 698.65%
- 3 2131 487.82%
- 4 1026 234.87%
- 5 660 151.09%
- 6 361 82.64%
- 7 219 50.13%
- 8 50 11.45%
+ 0 34112 7244.00%
+ 1 5516 1171.37%
+ 2 3070 651.94%
+ 3 2146 455.72%
+ 4 997 211.72%
+ 5 653 138.67%
+ 6 342 72.63%
+ 7 211 44.81%
+ 8 43 9.13%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.670899 # Inst issue rate
-system.cpu.iq.iqInstsAdded 32537 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 29431 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 772 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 16058 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 297 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 12535 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate
+system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 5795.180723 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2795.180723 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 481000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 232000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 430 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 5433.098592 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2433.098592 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2314500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990698 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 426 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1036500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990698 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 5578.947368 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2578.947368 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 106000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 49000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.009828 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 5492.141454 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.992203 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 509 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1268500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.992203 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 509 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 5492.141454 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2795500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.992203 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 509 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 503 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1268500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.992203 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 509 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -398,27 +398,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 273.898723 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 43868 # number of cpu cycles simulated
+system.cpu.numCycles 55514 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 20565 # Number of cycles rename is idle
-system.cpu.rename.RENAME:RenameLookups 76206 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 43436 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 36362 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 13390 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4338 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 306 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 22530 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 5085 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 899 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 5188 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 833 # count of temporary serializing insts renamed
-system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed
+system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
index eb1796ead..320065be7 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
@@ -1,2 +1,2 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
index 502cab72d..6ac99b20a 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 16:00:51
-M5 started Wed Jul 23 16:00:53 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:21:13
+M5 started Sat Aug 2 17:29:40 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Begining test of difficult SPARC instructions...
@@ -23,4 +23,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 21933500 because target called exit()
+Exiting @ tick 27756500 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index d0972f695..1df0c476d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
index 27bd0c98d..42336245f 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 26211 # Simulator instruction rate (inst/s)
-host_mem_usage 210104 # Number of bytes of host memory used
-host_seconds 0.58 # Real time elapsed on the host
-host_tick_rate 52105150 # Simulator tick rate (ticks/s)
+host_inst_rate 494493 # Simulator instruction rate (inst/s)
+host_mem_usage 198556 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 1381087807 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
-sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 30178000 # Number of ticks simulated
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 42735000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1431000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1272000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2754000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2448000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4185000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses
system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3720000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 3513 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4185000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses
system.cpu.dcache.overall_misses 155 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3720000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 102.837167 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use
system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26907.142857 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 7534000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 6694000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26907.142857 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 7534000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6694000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26907.142857 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 14941 # number of overall hits
-system.cpu.icache.overall_miss_latency 7534000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
system.cpu.icache.overall_misses 280 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6694000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -140,37 +140,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 165.376172 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use
system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1955000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 935000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 7613000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3641000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -182,29 +182,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9568000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4576000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9568000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 416 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4576000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -221,12 +221,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 187.735043 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 60356 # number of cpu cycles simulated
+system.cpu.numCycles 85470 # number of cpu cycles simulated
system.cpu.num_insts 15175 # Number of instructions executed
system.cpu.num_refs 3684 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
index eb1796ead..320065be7 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
@@ -1,2 +1,2 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
index 2511a0e62..8c9e71e76 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 23 2008 16:00:51
-M5 started Wed Jul 23 16:03:20 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug 2 2008 17:21:13
+M5 started Sat Aug 2 17:29:41 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Begining test of difficult SPARC instructions...
@@ -23,4 +23,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 30178000 because target called exit()
+Exiting @ tick 42735000 because target called exit()
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index ecab1a9a6..e57480396 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -411,7 +411,7 @@ pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index df1b8566f..af3c5730d 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1110947 # Simulator instruction rate (inst/s)
-host_mem_usage 261416 # Number of bytes of host memory used
-host_seconds 56.81 # Real time elapsed on the host
-host_tick_rate 32921847339 # Simulator tick rate (ticks/s)
+host_inst_rate 4441196 # Simulator instruction rate (inst/s)
+host_mem_usage 289900 # Number of bytes of host memory used
+host_seconds 14.21 # Real time elapsed on the host
+host_tick_rate 131610473505 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 63114046 # Number of instructions simulated
-sim_seconds 1.870335 # Number of seconds simulated
-sim_ticks 1870335151500 # Number of ticks simulated
+sim_insts 63113507 # Number of instructions simulated
+sim_seconds 1.870336 # Number of seconds simulated
+sim_ticks 1870335522500 # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses
-system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses
-system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12664339 # number of overall hits
+system.cpu0.dcache.overall_hits 12664298 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 2057379 # number of overall misses
+system.cpu0.dcache.overall_misses 2057375 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 1978971 # number of replacements
-system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 1978967 # number of replacements
+system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 396793 # number of writebacks
system.cpu0.dtb.accesses 698037 # DTB accesses
system.cpu0.dtb.acv 251 # DTB access violations
-system.cpu0.dtb.hits 15082956 # DTB hits
+system.cpu0.dtb.hits 15082911 # DTB hits
system.cpu0.dtb.misses 7805 # DTB misses
system.cpu0.dtb.read_accesses 508987 # DTB read accesses
system.cpu0.dtb.read_acv 152 # DTB read access violations
-system.cpu0.dtb.read_hits 9148379 # DTB read hits
+system.cpu0.dtb.read_hits 9148351 # DTB read hits
system.cpu0.dtb.read_misses 7079 # DTB read misses
system.cpu0.dtb.write_accesses 189050 # DTB write accesses
system.cpu0.dtb.write_acv 99 # DTB write access violations
-system.cpu0.dtb.write_hits 5934577 # DTB write hits
+system.cpu0.dtb.write_hits 5934560 # DTB write hits
system.cpu0.dtb.write_misses 726 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses
+system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses
+system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 56305276 # number of overall hits
+system.cpu0.icache.overall_hits 56304737 # number of overall hits
system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 884863 # number of overall misses
+system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 884868 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -137,19 +137,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 884267 # number of replacements
-system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 884272 # number of replacements
+system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use
-system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
+system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
-system.cpu0.itb.accesses 3858846 # ITB accesses
+system.cpu0.itb.accesses 3858857 # ITB accesses
system.cpu0.itb.acv 127 # ITB acv
-system.cpu0.itb.hits 3855361 # ITB hits
+system.cpu0.itb.hits 3855372 # ITB hits
system.cpu0.itb.misses 3485 # ITB misses
-system.cpu0.kern.callpal 183273 # number of callpals executed
+system.cpu0.kern.callpal 183274 # number of callpals executed
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed
system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed
@@ -158,7 +158,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # nu
system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed
system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed
system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed
system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed
system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed
system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed
@@ -168,43 +168,43 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu
system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed
system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl
system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1156
-system.cpu0.kern.mode_good_user 1157
+system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1157
+system.cpu0.kern.mode_good_user 1158
system.cpu0.kern.mode_good_idle 0
system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches
system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3762 # number of times the context was actually changed
system.cpu0.kern.syscall 226 # number of syscalls executed
@@ -239,9 +239,9 @@ system.cpu0.kern.syscall_132 2 0.88% 98.23% # nu
system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed
system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed
system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
-system.cpu0.numCycles 3740670191 # number of cpu cycles simulated
-system.cpu0.num_insts 57182083 # Number of instructions executed
-system.cpu0.num_refs 15322406 # Number of memory references
+system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
+system.cpu0.num_insts 57181549 # Number of instructions executed
+system.cpu0.num_refs 15322361 # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
@@ -255,12 +255,12 @@ system.cpu1.dcache.StoreCondReq_hits 13438 # nu
system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@@ -269,10 +269,10 @@ system.cpu1.dcache.cache_copies 0 # nu
system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -284,10 +284,10 @@ system.cpu1.dcache.overall_accesses 1884270 # nu
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1812115 # number of overall hits
+system.cpu1.dcache.overall_hits 1812118 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 72155 # number of overall misses
+system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 72152 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -303,13 +303,13 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 62341 # number of replacements
-system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements 62338 # number of replacements
+system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 30850 # number of writebacks
+system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 30848 # number of writebacks
system.cpu1.dtb.accesses 323622 # DTB accesses
system.cpu1.dtb.acv 116 # DTB access violations
system.cpu1.dtb.hits 1914885 # DTB hits
@@ -322,25 +322,25 @@ system.cpu1.dtb.write_accesses 103280 # DT
system.cpu1.dtb.write_acv 58 # DTB write access violations
system.cpu1.dtb.write_hits 751446 # DTB write hits
system.cpu1.dtb.write_misses 415 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses
+system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses
+system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -348,14 +348,14 @@ system.cpu1.icache.demand_mshr_misses 0 # nu
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 5832135 # number of overall hits
+system.cpu1.icache.overall_hits 5832136 # number of overall hits
system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 103636 # number of overall misses
+system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 103630 # number of overall misses
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -371,12 +371,12 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 103097 # number of replacements
-system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 103091 # number of replacements
+system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
+system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
system.cpu1.itb.accesses 1469938 # ITB accesses
@@ -403,7 +403,7 @@ system.cpu1.kern.callpal_imb 38 0.12% 100.00% # nu
system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl
system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl
@@ -414,8 +414,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu
system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
@@ -433,9 +433,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr
system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
system.cpu1.kern.syscall 100 # number of syscalls executed
system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed
@@ -456,8 +456,8 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu
system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed
system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
-system.cpu1.numCycles 3740248139 # number of cpu cycles simulated
-system.cpu1.num_insts 5931963 # Number of instructions executed
+system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
+system.cpu1.num_insts 5931958 # Number of instructions executed
system.cpu1.num_refs 1926645 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
@@ -525,37 +525,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0
system.iocache.replacements 41695 # number of replacements
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.435434 # Cycle average of tags in use
+system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1759614 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 1759609 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 964534 # number of ReadReq misses
system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 427643 # number of Writeback hits
+system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 427641 # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.789371 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.789118 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses
+system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1759614 # number of demand (read+write) hits
+system.l2c.demand_hits 1759609 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses
-system.l2c.demand_misses 1270780 # number of demand (read+write) misses
+system.l2c.demand_misses 1270778 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses
+system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 1759614 # number of overall hits
+system.l2c.overall_hits 1759609 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses
-system.l2c.overall_misses 1270780 # number of overall misses
+system.l2c.overall_misses 1270778 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1056801 # number of replacements
-system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks.
+system.l2c.replacements 1056800 # number of replacements
+system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use
-system.l2c.total_refs 1953009 # Total number of references to valid blocks.
+system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use
+system.l2c.total_refs 1952731 # Total number of references to valid blocks.
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123879 # number of writebacks
+system.l2c.writebacks 123878 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
index 4e60f8a9d..7d514c2b6 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
@@ -1,6 +1,6 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+Listening for system connection on port 3459
+0: system.remote_gdb.listener: listening for remote gdb on port 7004
+0: system.remote_gdb.listener: listening for remote gdb on port 7008
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index a5a0972a1..601a2c3c3 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:27:21
-M5 started Mon Jul 21 20:28:09 2008
+M5 compiled Aug 2 2008 17:07:34
+M5 started Sat Aug 2 17:08:14 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1870335151500 because m5_exit instruction encountered
+Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 4ce652819..e739f3815 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -300,7 +300,7 @@ pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index 082e17724..5018c7d30 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,44 +1,44 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1474278 # Simulator instruction rate (inst/s)
-host_mem_usage 260680 # Number of bytes of host memory used
-host_seconds 40.70 # Real time elapsed on the host
-host_tick_rate 44928072322 # Simulator tick rate (ticks/s)
+host_inst_rate 3096300 # Simulator instruction rate (inst/s)
+host_mem_usage 288712 # Number of bytes of host memory used
+host_seconds 19.38 # Real time elapsed on the host
+host_tick_rate 94358252114 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 59995479 # Number of instructions simulated
-sim_seconds 1.828355 # Number of seconds simulated
-sim_ticks 1828355496000 # Number of ticks simulated
+sim_insts 59995351 # Number of instructions simulated
+sim_seconds 1.828356 # Number of seconds simulated
+sim_ticks 1828355695500 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits 7801378 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1721676 # number of ReadReq misses
+system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses
+system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.866562 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 13552150 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2121093 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 13552150 # number of overall hits
+system.cpu.dcache.overall_hits 13552138 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2121093 # number of overall misses
+system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2121104 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2042665 # number of replacements
-system.cpu.dcache.sampled_refs 2043177 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 2042676 # number of replacements
+system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14029602 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 428885 # number of writebacks
+system.cpu.dcache.writebacks 428892 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 16053818 # DTB hits
+system.cpu.dtb.hits 16053817 # DTB hits
system.cpu.dtb.misses 11471 # DTB misses
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9703850 # DTB read hits
+system.cpu.dtb.read_hits 9703849 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_hits 6349968 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits 59087262 # number of ReadReq hits
+system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 920055 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 64.229474 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 59087262 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses
-system.cpu.icache.demand_misses 920055 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses 0 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 59087262 # number of overall hits
+system.cpu.icache.overall_hits 59087131 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses
-system.cpu.icache.overall_misses 920055 # number of overall misses
+system.cpu.icache.overall_misses 920058 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 919428 # number of replacements
-system.cpu.icache.sampled_refs 919940 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 919431 # number of replacements
+system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use
-system.cpu.icache.total_refs 59087262 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use
+system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.983588 # Percentage of idle cycles
-system.cpu.itb.accesses 4979217 # ITB accesses
+system.cpu.itb.accesses 4979228 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4974211 # ITB hits
+system.cpu.itb.hits 4974222 # ITB hits
system.cpu.itb.misses 5006 # ITB misses
-system.cpu.kern.callpal 192139 # number of callpals executed
+system.cpu.kern.callpal 192140 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
@@ -157,7 +157,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu
system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed
+system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed
system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
@@ -167,40 +167,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl
+system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1828355288500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1811087557500 99.06% 99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1908
-system.cpu.kern.mode_good_user 1737
+system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1909
+system.cpu.kern.mode_good_user 1738
system.cpu.kern.mode_good_idle 171
system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1737 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1800056192000 98.45% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
@@ -234,9 +234,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles
-system.cpu.numCycles 3656710883 # number of cpu cycles simulated
-system.cpu.num_insts 59995479 # Number of instructions executed
-system.cpu.num_refs 16302129 # Number of memory references
+system.cpu.numCycles 3656711283 # number of cpu cycles simulated
+system.cpu.num_insts 59995351 # Number of instructions executed
+system.cpu.num_refs 16302128 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0
system.iocache.replacements 41686 # number of replacements
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.226223 # Cycle average of tags in use
+system.iocache.tagsinuse 1.226225 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2658874 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1696454 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.361965 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 962420 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 1696464 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 962419 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 428885 # number of Writeback hits
+system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses
+system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 428892 # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.726821 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.726803 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2963216 # number of demand (read+write) accesses
+system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1696454 # number of demand (read+write) hits
+system.l2c.demand_hits 1696464 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.427496 # miss rate for demand accesses
-system.l2c.demand_misses 1266762 # number of demand (read+write) misses
+system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses
+system.l2c.demand_misses 1266766 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2963216 # number of overall (read+write) accesses
+system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 1696454 # number of overall hits
+system.l2c.overall_hits 1696464 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.427496 # miss rate for overall accesses
-system.l2c.overall_misses 1266762 # number of overall misses
+system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses
+system.l2c.overall_misses 1266766 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1050727 # number of replacements
-system.l2c.sampled_refs 1081066 # Sample count of references to valid blocks.
+system.l2c.replacements 1050731 # number of replacements
+system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30223.986648 # Cycle average of tags in use
-system.l2c.total_refs 1866807 # Total number of references to valid blocks.
+system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use
+system.l2c.total_refs 1866797 # Total number of references to valid blocks.
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119145 # number of writebacks
+system.l2c.writebacks 119150 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
index 7e35fafed..438bf9f24 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
@@ -1,4 +1,4 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+Listening for system connection on port 3459
+0: system.remote_gdb.listener: listening for remote gdb on port 7004
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index ac8785088..8a31735d4 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:27:21
-M5 started Mon Jul 21 20:27:46 2008
+M5 compiled Aug 2 2008 17:07:34
+M5 started Sat Aug 2 17:08:29 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1828355496000 because m5_exit instruction encountered
+Exiting @ tick 1828355695500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 459187376..2985b82ee 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -405,7 +405,7 @@ pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index 85a08a7e2..3478349a5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,92 +1,92 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 647923 # Simulator instruction rate (inst/s)
-host_mem_usage 252928 # Number of bytes of host memory used
-host_seconds 97.63 # Real time elapsed on the host
-host_tick_rate 20205445341 # Simulator tick rate (ticks/s)
+host_inst_rate 1987058 # Simulator instruction rate (inst/s)
+host_mem_usage 287224 # Number of bytes of host memory used
+host_seconds 29.88 # Real time elapsed on the host
+host_tick_rate 65994111033 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 63257216 # Number of instructions simulated
-sim_seconds 1.972680 # Number of seconds simulated
-sim_ticks 1972679592000 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses 192278 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 175522 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 234006000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.087145 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 16756 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 183738000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.087145 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16756 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 9119152 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941 # average ReadReq mshr miss latency
+sim_insts 59379829 # Number of instructions simulated
+sim_seconds 1.972135 # Number of seconds simulated
+sim_ticks 1972135479000 # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits 7426037 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 35981081500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.185666 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1693115 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 30901697000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.185666 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 1693115 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 857399000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 191314 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits 162861 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 759304000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate 0.148724 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 28453 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 673945000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.148724 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 28453 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 5834436 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638 # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 5455075 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 10223632000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.065021 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 379361 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 9085549000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065021 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 379361 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1211657000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 6.692591 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14953588 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 22294.450454 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12881112 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 46204713500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.138594 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2072476 # number of demand (read+write) misses
+system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 39987246000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.138594 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 2072476 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14953588 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 22294.450454 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency
+system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12881112 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 46204713500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.138594 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 2072476 # number of overall misses
+system.cpu0.dcache.overall_hits 12909668 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 1417993 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 39987246000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.138594 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 2072476 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2069056000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 1992967 # number of replacements
-system.cpu0.dcache.sampled_refs 1993479 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 1338626 # number of replacements
+system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 503.888732 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13341539 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 66395000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 403713 # number of writebacks
-system.cpu0.dtb.accesses 719861 # DTB accesses
+system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 403562 # number of writebacks
+system.cpu0.dtb.accesses 719860 # DTB accesses
system.cpu0.dtb.acv 289 # DTB access violations
-system.cpu0.dtb.hits 15321442 # DTB hits
-system.cpu0.dtb.misses 8487 # DTB misses
-system.cpu0.dtb.read_accesses 524202 # DTB read accesses
+system.cpu0.dtb.hits 14696400 # DTB hits
+system.cpu0.dtb.misses 8485 # DTB misses
+system.cpu0.dtb.read_accesses 524201 # DTB read accesses
system.cpu0.dtb.read_acv 174 # DTB read access violations
-system.cpu0.dtb.read_hits 9294921 # DTB read hits
-system.cpu0.dtb.read_misses 7689 # DTB read misses
+system.cpu0.dtb.read_hits 8658591 # DTB read hits
+system.cpu0.dtb.read_misses 7687 # DTB read misses
system.cpu0.dtb.write_accesses 195659 # DTB write accesses
system.cpu0.dtb.write_acv 115 # DTB write access violations
-system.cpu0.dtb.write_hits 6026521 # DTB write hits
+system.cpu0.dtb.write_hits 6037809 # DTB write hits
system.cpu0.dtb.write_misses 798 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 57943269 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 14213.482115 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11212.730813 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 57028190 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 13006459000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.015793 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 915079 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 10260534500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.015793 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 915079 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 62.327526 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 57943269 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 14213.482115 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 57028190 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 13006459000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.015793 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 915079 # number of demand (read+write) misses
+system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 10260534500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.015793 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 915079 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 57943269 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 14213.482115 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency
+system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 57028190 # number of overall hits
-system.cpu0.icache.overall_miss_latency 13006459000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.015793 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 915079 # number of overall misses
+system.cpu0.icache.overall_hits 53208030 # number of overall hits
+system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 916222 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 10260534500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.015793 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 915079 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -171,76 +171,76 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 914464 # number of replacements
-system.cpu0.icache.sampled_refs 914976 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 915582 # number of replacements
+system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 507.411447 # Cycle average of tags in use
-system.cpu0.icache.total_refs 57028190 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 49269353000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use
+system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0.932800 # Percentage of idle cycles
-system.cpu0.itb.accesses 3949472 # ITB accesses
+system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles
+system.cpu0.itb.accesses 3953623 # ITB accesses
system.cpu0.itb.acv 143 # ITB acv
-system.cpu0.itb.hits 3945631 # ITB hits
+system.cpu0.itb.hits 3949782 # ITB hits
system.cpu0.itb.misses 3841 # ITB misses
-system.cpu0.kern.callpal 187580 # number of callpals executed
+system.cpu0.kern.callpal 187998 # number of callpals executed
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 94 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed
system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 3867 2.06% 2.11% # number of callpals executed
-system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed
+system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed
system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 171680 91.52% 93.66% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6661 3.55% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed
+system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed
system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed
system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed
system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed
system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_rti 4704 2.51% 99.73% # number of callpals executed
+system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed
system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed
system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 202457 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 178500 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 72488 40.61% 40.61% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1977 1.11% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 7 0.00% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 103897 58.21% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good 144346 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0 71119 49.27% 49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22 1977 1.37% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30 7 0.00% 50.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31 71112 49.26% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1972678821000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1900126420500 96.32% 96.32% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 86973000 0.00% 96.33% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 568583000 0.03% 96.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 5546500 0.00% 96.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 71891298000 3.64% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0 0.981114 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.684447 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1228
-system.cpu0.kern.mode_good_user 1229
+system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1232
+system.cpu0.kern.mode_good_user 1233
system.cpu0.kern.mode_good_idle 0
-system.cpu0.kern.mode_switch_kernel 7227 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1229 # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches
system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.169918 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1969223377000 99.82% 99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 3455442000 0.18% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3868 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3869 # number of times the context was actually changed
system.cpu0.kern.syscall 224 # number of syscalls executed
system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed
system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed
@@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu
system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed
system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed
system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction 0.067200 # Percentage of non-idle cycles
-system.cpu0.numCycles 3945359184 # number of cpu cycles simulated
-system.cpu0.num_insts 57934492 # Number of instructions executed
-system.cpu0.num_refs 15562811 # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses 12625 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9190.944882 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits 11609 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 12386000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate 0.080475 # miss rate for LoadLockedReq accesses
+system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles
+system.cpu0.numCycles 3944270958 # number of cpu cycles simulated
+system.cpu0.num_insts 54115477 # Number of instructions executed
+system.cpu0.num_refs 14937789 # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 9338000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.080475 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses 1030298 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits 994091 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 505024500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.035142 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 36207 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 396399000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035142 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 36207 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 13393500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses 12560 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits 10118 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 55860000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate 0.194427 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses 2442 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48534000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.194427 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 2442 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 657926 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865 # average WriteReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits 631072 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 708377500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.040816 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 26854 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 627815500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040816 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 26854 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 305665000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 30.077708 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 1688224 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 19241.718336 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1625163 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 1213402000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.037353 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 63061 # number of demand (read+write) misses
+system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 1024214500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.037353 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 63061 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 1688224 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 19241.718336 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency
+system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1625163 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 1213402000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.037353 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 63061 # number of overall misses
+system.cpu1.dcache.overall_hits 1608374 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 62122 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 1024214500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.037353 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 63061 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 319058500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 54390 # number of replacements
-system.cpu1.dcache.sampled_refs 54808 # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements 53749 # number of replacements
+system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 387.947804 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1648499 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1956976796000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 27227 # number of writebacks
+system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 26833 # number of writebacks
system.cpu1.dtb.accesses 302878 # DTB accesses
system.cpu1.dtb.acv 84 # DTB access violations
-system.cpu1.dtb.hits 1712100 # DTB hits
+system.cpu1.dtb.hits 1693796 # DTB hits
system.cpu1.dtb.misses 3106 # DTB misses
system.cpu1.dtb.read_accesses 205838 # DTB read accesses
system.cpu1.dtb.read_acv 36 # DTB read access violations
-system.cpu1.dtb.read_hits 1039743 # DTB read hits
+system.cpu1.dtb.read_hits 1029675 # DTB read hits
system.cpu1.dtb.read_misses 2750 # DTB read misses
system.cpu1.dtb.write_accesses 97040 # DTB write accesses
system.cpu1.dtb.write_acv 48 # DTB write access violations
-system.cpu1.dtb.write_hits 672357 # DTB write hits
+system.cpu1.dtb.write_hits 664121 # DTB write hits
system.cpu1.dtb.write_misses 356 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 5325914 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 5236056 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 1284961500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.016872 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 89858 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 1015347000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.016872 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 89858 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 58.288501 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 5325914 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14299.912084 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 5236056 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 1284961500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.016872 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 89858 # number of demand (read+write) misses
+system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 1015347000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.016872 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 89858 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 5325914 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14299.912084 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency
+system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 5236056 # number of overall hits
-system.cpu1.icache.overall_miss_latency 1284961500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.016872 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 89858 # number of overall misses
+system.cpu1.icache.overall_hits 5180112 # number of overall hits
+system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 87430 # number of overall misses
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 1015347000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.016872 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 89858 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -439,72 +439,72 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 89318 # number of replacements
-system.cpu1.icache.sampled_refs 89830 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 86890 # number of replacements
+system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 419.412997 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5236056 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1957297672000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use
+system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0.995045 # Percentage of idle cycles
-system.cpu1.itb.accesses 1398451 # ITB accesses
+system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles
+system.cpu1.itb.accesses 1397499 # ITB accesses
system.cpu1.itb.acv 41 # ITB acv
-system.cpu1.itb.hits 1397205 # ITB hits
+system.cpu1.itb.hits 1396253 # ITB hits
system.cpu1.itb.misses 1246 # ITB misses
-system.cpu1.kern.callpal 29654 # number of callpals executed
+system.cpu1.kern.callpal 29501 # number of callpals executed
system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir 7 0.02% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_swpctx 369 1.24% 1.28% # number of callpals executed
-system.cpu1.kern.callpal_tbi 10 0.03% 1.31% # number of callpals executed
-system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed
-system.cpu1.kern.callpal_swpipl 24277 81.87% 83.20% # number of callpals executed
-system.cpu1.kern.callpal_rdps 2191 7.39% 90.59% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp 1 0.00% 90.59% # number of callpals executed
-system.cpu1.kern.callpal_wrusp 3 0.01% 90.60% # number of callpals executed
-system.cpu1.kern.callpal_rdusp 2 0.01% 90.61% # number of callpals executed
-system.cpu1.kern.callpal_whami 3 0.01% 90.62% # number of callpals executed
-system.cpu1.kern.callpal_rti 2588 8.73% 99.35% # number of callpals executed
-system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed
-system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed
+system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed
+system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed
+system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed
+system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed
+system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 36198 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2401 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 28931 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 9254 31.99% 31.99% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1971 6.81% 38.80% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 94 0.32% 39.12% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 17612 60.88% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 20463 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 9246 45.18% 45.18% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1971 9.63% 54.82% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 94 0.46% 55.28% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 9152 44.72% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1972666579000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1919200833000 97.29% 97.29% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 508731500 0.03% 97.32% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 56757500 0.00% 97.32% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 52900257000 2.68% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0 0.999136 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.519646 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 533
-system.cpu1.kern.mode_good_user 515
-system.cpu1.kern.mode_good_idle 18
-system.cpu1.kern.mode_switch_kernel 882 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 515 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2077 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 1.612975 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.604308 # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 532
+system.cpu1.kern.mode_good_user 516
+system.cpu1.kern.mode_good_idle 16
+system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 516 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.008666 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 3978131000 0.20% 0.20% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 1616488000 0.08% 0.28% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1966135435000 99.72% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 370 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 366 # number of times the context was actually changed
system.cpu1.kern.syscall 102 # number of syscalls executed
system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed
system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed
@@ -527,10 +527,10 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu
system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed
system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed
system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction 0.004955 # Percentage of non-idle cycles
-system.cpu1.numCycles 3945333218 # number of cpu cycles simulated
-system.cpu1.num_insts 5322724 # Number of instructions executed
-system.cpu1.num_refs 1722033 # Number of memory references
+system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles
+system.cpu1.numCycles 3943367734 # number of cpu cycles simulated
+system.cpu1.num_insts 5264352 # Number of instructions executed
+system.cpu1.num_refs 1703685 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@@ -543,58 +543,58 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 176 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 113562.488636 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 61562.488636 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19986998 # number of ReadReq miss cycles
+system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 176 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10834998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_misses 178 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 115053.879621 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 63053.711494 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 4780718806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 2620007820 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 4173.944424 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 2771 # number of cycles access was blocked
+system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 11566000 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41728 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 115047.589245 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency
+system.iocache.demand_accesses 41730 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 4800705804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41728 # number of demand (read+write) misses
+system.iocache.demand_misses 41730 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 2630842818 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41728 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41728 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 115047.589245 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency
+system.iocache.overall_accesses 41730 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 4800705804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41728 # number of overall misses
+system.iocache.overall_misses 41730 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 2630842818 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41728 # number of overall MSHR misses
+system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -606,83 +606,83 @@ system.iocache.prefetcher.num_hwpf_issued 0 # n
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41696 # number of replacements
-system.iocache.sampled_refs 41712 # Sample count of references to valid blocks.
+system.iocache.replacements 41698 # number of replacements
+system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.554980 # Cycle average of tags in use
+system.iocache.tagsinuse 0.582076 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1766170681000 # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses 307159 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 23004.538366 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 11004.538366 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 7066051000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 307159 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 3380143000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 307159 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2746067 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 23012.790348 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1782997 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 22162928000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.350709 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 963070 # number of ReadReq misses
+system.l2c.ReadReq_hits 1782800 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 307447 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 10605988000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.350705 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 963059 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 779852500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 127459 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 22445.817871 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 11007.104245 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 2860921500 # number of UpgradeReq miss cycles
+system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 127459 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 1402954500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 127459 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1370781000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430940 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430940 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430395 # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.813929 # Average number of references to valid blocks.
+system.l2c.avg_refs 4.558799 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3053226 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 23010.794904 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency
-system.l2c.demand_hits 1782997 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 29228979000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.416028 # miss rate for demand accesses
-system.l2c.demand_misses 1270229 # number of demand (read+write) misses
+system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
+system.l2c.demand_hits 1782800 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses
+system.l2c.demand_misses 614243 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 13986131000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.416025 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 1270218 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3053226 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 23010.794904 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency
+system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1782997 # number of overall hits
-system.l2c.overall_miss_latency 29228979000 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.416028 # miss rate for overall accesses
-system.l2c.overall_misses 1270229 # number of overall misses
+system.l2c.overall_hits 1782800 # number of overall hits
+system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses
+system.l2c.overall_misses 614243 # number of overall misses
system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 13986131000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.416025 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 1270218 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2150633500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1055829 # number of replacements
-system.l2c.sampled_refs 1087019 # Sample count of references to valid blocks.
+system.l2c.replacements 399043 # number of replacements
+system.l2c.sampled_refs 430765 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30866.493853 # Cycle average of tags in use
-system.l2c.total_refs 1971775 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 7281125000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123132 # number of writebacks
+system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use
+system.l2c.total_refs 1963771 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 123178 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
index b0bbb3d67..98c38c0d8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
@@ -1,6 +1,6 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+Listening for system connection on port 3458
+0: system.remote_gdb.listener: listening for remote gdb on port 7007
+0: system.remote_gdb.listener: listening for remote gdb on port 7008
warn: Entering event queue @ 0. Starting simulation...
-warn: 478619000: Trying to launch CPU number 1!
+warn: 591544000: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 18467c41b..dff43c48d 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:27:21
-M5 started Mon Jul 21 20:27:23 2008
+M5 compiled Aug 2 2008 17:07:34
+M5 started Sat Aug 2 17:07:43 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1972679592000 because m5_exit instruction encountered
+Exiting @ tick 1972135479000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index c2aeea3f1..6974143c8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -27,6 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
+ 4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 66d96d325..05eb9b89c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -297,7 +297,7 @@ pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index fcddfbde2..7b835d1b3 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,92 +1,92 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 827411 # Simulator instruction rate (inst/s)
-host_mem_usage 316168 # Number of bytes of host memory used
-host_seconds 72.58 # Real time elapsed on the host
-host_tick_rate 26612603617 # Simulator tick rate (ticks/s)
+host_inst_rate 1555255 # Simulator instruction rate (inst/s)
+host_mem_usage 285892 # Number of bytes of host memory used
+host_seconds 36.11 # Real time elapsed on the host
+host_tick_rate 53447376481 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 60056349 # Number of instructions simulated
-sim_seconds 1.931640 # Number of seconds simulated
-sim_ticks 1931639667000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 200273 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 183016 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 243431000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.086167 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17257 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191660000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086167 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17257 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 9530772 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712 # average ReadReq mshr miss latency
+sim_insts 56165112 # Number of instructions simulated
+sim_seconds 1.930166 # Number of seconds simulated
+sim_ticks 1930165791000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits 7805869 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 36469798500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.180983 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1724903 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 31295044000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.180983 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1724903 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 837553000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses 199252 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits 169292 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 809028000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate 0.150362 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 29960 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 719148000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150362 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 29960 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6154055 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits 5753421 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10819509500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.065101 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 400634 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 9617607500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.065101 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 400634 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1174669000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.859082 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15684827 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22248.169757 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 13559290 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 47289308000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.135515 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2125537 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 40912651500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.135515 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2125537 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 15684827 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22248.169757 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 13559290 # number of overall hits
-system.cpu.dcache.overall_miss_latency 47289308000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.135515 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2125537 # number of overall misses
+system.cpu.dcache.overall_hits 13569826 # number of overall hits
+system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1471004 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 40912651500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.135515 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2125537 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2012222000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2046082 # number of replacements
-system.cpu.dcache.sampled_refs 2046594 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1391586 # number of replacements
+system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.986722 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14037756 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 66420000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430195 # number of writebacks
-system.cpu.dtb.accesses 1020787 # DTB accesses
+system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 430461 # number of writebacks
+system.cpu.dtb.accesses 1020784 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 16064922 # DTB hits
-system.cpu.dtb.misses 11471 # DTB misses
-system.cpu.dtb.read_accesses 728856 # DTB read accesses
+system.cpu.dtb.hits 15421361 # DTB hits
+system.cpu.dtb.misses 11466 # DTB misses
+system.cpu.dtb.read_accesses 728853 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9711464 # DTB read hits
-system.cpu.dtb.read_misses 10329 # DTB read misses
+system.cpu.dtb.read_hits 9063577 # DTB read hits
+system.cpu.dtb.read_misses 10324 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6353458 # DTB write hits
+system.cpu.dtb.write_hits 6357784 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses 60068188 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 929129 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency
-system.cpu.icache.demand_hits 59139059 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accesses
-system.cpu.icache.demand_misses 929129 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
+system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses
+system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 59139059 # number of overall hits
-system.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accesses
-system.cpu.icache.overall_misses 929129 # number of overall misses
+system.cpu.icache.overall_hits 55246023 # number of overall hits
+system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses
+system.cpu.icache.overall_misses 930923 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 928458 # number of replacements
-system.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 930251 # number of replacements
+system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in use
-system.cpu.icache.total_refs 59139059 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use
+system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.929252 # Percentage of idle cycles
-system.cpu.itb.accesses 4979997 # ITB accesses
+system.cpu.idle_fraction 0.929251 # Percentage of idle cycles
+system.cpu.itb.accesses 4982832 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4974991 # ITB hits
-system.cpu.itb.misses 5006 # ITB misses
-system.cpu.kern.callpal 192947 # number of callpals executed
+system.cpu.itb.hits 4977822 # ITB hits
+system.cpu.itb.misses 5010 # ITB misses
+system.cpu.kern.callpal 193204 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
-system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executed
-system.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed
+system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
-system.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 183224 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1905
-system.cpu.kern.mode_good_user 1736
-system.cpu.kern.mode_good_idle 169
-system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1736 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2093 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switches
+system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1910
+system.cpu.kern.mode_good_user 1743
+system.cpu.kern.mode_good_idle 167
+system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1743 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4175 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4172 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
@@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.not_idle_fraction 0.070748 # Percentage of non-idle cycles
-system.cpu.numCycles 3863279334 # number of cpu cycles simulated
-system.cpu.num_insts 60056349 # Number of instructions executed
-system.cpu.num_refs 16313052 # Number of memory references
+system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles
+system.cpu.numCycles 3860331582 # number of cpu cycles simulated
+system.cpu.num_insts 56165112 # Number of instructions executed
+system.cpu.num_refs 15669461 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@@ -284,55 +284,55 @@ system.disk2.dma_write_bytes 8192 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 113566.462428 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 61566.462428 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19646998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10650998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 115104.611234 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 63104.539180 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 4782826806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 2622119812 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 4196.454414 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 2764 # number of cycles access was blocked
+system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 11599000 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 115098.233769 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency
+system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 4802473804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 2632770810 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 115098.233769 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency
+system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 4802473804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 2632770810 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.333347 # Cycle average of tags in use
+system.iocache.tagsinuse 1.353410 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1766149259000 # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses 304436 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 23005.373872 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 7003664000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 304436 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 3350432000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 304436 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2671270 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 23012.722595 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1708534 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 22155176500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.360404 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 962736 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 10602344500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.360404 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 962736 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 126158 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 23005.275131 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 2902299500 # number of UpgradeReq miss cycles
+system.l2c.ReadReq_hits 1710772 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 307605 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 126158 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 1388610500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 126158 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1061281000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430195 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430195 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430461 # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.743066 # Average number of references to valid blocks.
+system.l2c.avg_refs 4.436452 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2975706 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 23010.957076 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency
-system.l2c.demand_hits 1708534 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 29158840500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.425839 # miss rate for demand accesses
-system.l2c.demand_misses 1267172 # number of demand (read+write) misses
+system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
+system.l2c.demand_hits 1710772 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses
+system.l2c.demand_misses 612230 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 13952776500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.425839 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 1267172 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2975706 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 23010.957076 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency
+system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1708534 # number of overall hits
-system.l2c.overall_miss_latency 29158840500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.425839 # miss rate for overall accesses
-system.l2c.overall_misses 1267172 # number of overall misses
+system.l2c.overall_hits 1710772 # number of overall hits
+system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses
+system.l2c.overall_misses 612230 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 13952776500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.425839 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 1267172 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1811383000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1050085 # number of replacements
-system.l2c.sampled_refs 1081030 # Sample count of references to valid blocks.
+system.l2c.replacements 394925 # number of replacements
+system.l2c.sampled_refs 425907 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30869.828292 # Cycle average of tags in use
-system.l2c.total_refs 1884307 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 5029142000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 118653 # number of writebacks
+system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use
+system.l2c.total_refs 1889516 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 119047 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 408213e67..3aab2bec2 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,4 +1,4 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for system connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb on port 7004
+Listening for system connection on port 3458
+0: system.remote_gdb.listener: listening for remote gdb on port 7007
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index a429ac712..4d30d3925 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:27:21
-M5 started Mon Jul 21 20:28:11 2008
+M5 compiled Aug 2 2008 17:07:34
+M5 started Sat Aug 2 17:08:13 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1931639667000 because m5_exit instruction encountered
+Exiting @ tick 1930165791000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index 7930e9e46..3efa225a8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -24,6 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
+ 4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index ddf7f50b2..3d8212f3f 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -163,6 +163,7 @@ type=ExeTracer
[system.cpu.workload]
type=EioProcess
chkpt=
+errout=cerr
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
@@ -182,7 +183,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index f4cb30fc4..e8282d216 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 922979 # Simulator instruction rate (inst/s)
-host_mem_usage 193036 # Number of bytes of host memory used
-host_seconds 0.54 # Real time elapsed on the host
-host_tick_rate 1305530646 # Simulator tick rate (ticks/s)
+host_inst_rate 1672362 # Simulator instruction rate (inst/s)
+host_mem_usage 196544 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
+host_tick_rate 2464131877 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
-sim_seconds 0.000708 # Number of seconds simulated
-sim_ticks 707548000 # Number of ticks simulated
+sim_seconds 0.000737 # Number of seconds simulated
+sim_ticks 737389000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 8505000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 7560000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8397000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 7464000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 16902000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 15024000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180149 # number of overall hits
-system.cpu.dcache.overall_miss_latency 16902000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
system.cpu.dcache.overall_misses 626 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 15024000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 289.353429 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 10881000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 9672000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 10881000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 9672000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499617 # number of overall hits
-system.cpu.icache.overall_miss_latency 10881000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_misses 403 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 9672000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 266.476324 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT
system.cpu.itb.hits 500020 # ITB hits
system.cpu.itb.misses 13 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 3197000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1529000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 16514000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 7898000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3956000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1892000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19711000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19711000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 857 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 373.323140 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1415096 # number of cpu cycles simulated
+system.cpu.numCycles 1474778 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 182222 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
index 9e24842c0..cc0a07c09 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
@@ -1,4 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
+0: system.remote_gdb.listener: listening for remote gdb on port 7006
warn: Entering event queue @ 0. Starting simulation...
gzip: stdout: Broken pipe
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 3f3a9bccf..46fb8222f 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:18:02 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:10:34 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
main dictionary has 1245 entries
49508 bytes wasted
->Exiting @ tick 707548000 because a thread reached the max instruction count
+>Exiting @ tick 737389000 because a thread reached the max instruction count
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 1a7e3807d..ce3301742 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -428,7 +428,7 @@ mem_side=system.toL2Bus.port[8]
[system.funcmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
@@ -484,7 +484,7 @@ port=system.l2c.mem_side system.physmem.port[0]
[system.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
index f7b90230a..c4e841ee5 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
@@ -1,70 +1,70 @@
---------- Begin Simulation Statistics ----------
-host_mem_usage 323140 # Number of bytes of host memory used
-host_seconds 197.60 # Real time elapsed on the host
-host_tick_rate 574221 # Simulator tick rate (ticks/s)
+host_mem_usage 323512 # Number of bytes of host memory used
+host_seconds 193.82 # Real time elapsed on the host
+host_tick_rate 1387453 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000113 # Number of seconds simulated
-sim_ticks 113467820 # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 16813.519915 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15809.702810 # average ReadReq mshr miss latency
+sim_seconds 0.000269 # Number of seconds simulated
+sim_ticks 268915439 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits 7364 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency 627699139 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate 0.835246 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses 37333 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 590223635 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835246 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses 37333 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 316695188 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses 24294 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 20338.524830 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19334.650285 # average WriteReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits 955 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency 474680831 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate 0.960690 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses 23339 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency 451251403 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate 0.960690 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses 23339 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 201005657 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1600.079607 # average number of cycles each access was blocked
+system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs 0.402132 # Average number of references to valid blocks.
-system.cpu0.l1c.blocked_no_mshrs 70069 # number of cycles access was blocked
+system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked
system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_mshrs 112115978 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.demand_accesses 68991 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency 18169.501088 # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency
-system.cpu0.l1c.demand_hits 8319 # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency 1102379970 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate 0.879419 # miss rate for demand accesses
-system.cpu0.l1c.demand_misses 60672 # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses
system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency 1041475038 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate 0.879419 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses 60672 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l1c.overall_accesses 68991 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 18169.501088 # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency
+system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits 8319 # number of overall hits
-system.cpu0.l1c.overall_miss_latency 1102379970 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate 0.879419 # miss rate for overall accesses
-system.cpu0.l1c.overall_misses 60672 # number of overall misses
+system.cpu0.l1c.overall_hits 8674 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 60767 # number of overall misses
system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency 1041475038 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate 0.879419 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses 60672 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency 517700845 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l1c.replacements 27892 # number of replacements
-system.cpu0.l1c.sampled_refs 28232 # Sample count of references to valid blocks.
+system.cpu0.l1c.replacements 28158 # number of replacements
+system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse 346.353469 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 11353 # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks 11056 # number of writebacks
+system.cpu0.l1c.writebacks 11054 # number of writebacks
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.num_reads 99413 # number of read accesses completed
-system.cpu0.num_writes 54273 # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses 44637 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 16885.597031 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15881.726361 # average ReadReq mshr miss latency
+system.cpu0.num_reads 99578 # number of read accesses completed
+system.cpu0.num_writes 53795 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits 7453 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency 627874040 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate 0.833031 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses 37184 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 590546113 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833031 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses 37184 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 318748024 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses 24256 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 20197.502675 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19193.799580 # average WriteReq mshr miss latency
+system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_hits 895 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency 471833860 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate 0.963102 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses 23361 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency 448386352 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.963102 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses 23361 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 199243328 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1599.721775 # average number of cycles each access was blocked
+system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs 0.408930 # Average number of references to valid blocks.
-system.cpu1.l1c.blocked_no_mshrs 69990 # number of cycles access was blocked
+system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked
system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_mshrs 111964527 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.demand_accesses 68893 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency 18163.480056 # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency
-system.cpu1.l1c.demand_hits 8348 # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency 1099707900 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate 0.878827 # miss rate for demand accesses
-system.cpu1.l1c.demand_misses 60545 # number of demand (read+write) misses
+system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
+system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses
+system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses
system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency 1038932465 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate 0.878827 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses 60545 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l1c.overall_accesses 68893 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 18163.480056 # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency
+system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits 8348 # number of overall hits
-system.cpu1.l1c.overall_miss_latency 1099707900 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate 0.878827 # miss rate for overall accesses
-system.cpu1.l1c.overall_misses 60545 # number of overall misses
+system.cpu1.l1c.overall_hits 8551 # number of overall hits
+system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses
+system.cpu1.l1c.overall_misses 60450 # number of overall misses
system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency 1038932465 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate 0.878827 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses 60545 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency 517991352 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l1c.replacements 27678 # number of replacements
-system.cpu1.l1c.sampled_refs 28017 # Sample count of references to valid blocks.
+system.cpu1.l1c.replacements 27563 # number of replacements
+system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks.
system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse 343.577416 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 11457 # Total number of references to valid blocks.
+system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks 10919 # number of writebacks
+system.cpu1.l1c.writebacks 10923 # number of writebacks
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 99570 # number of read accesses completed
-system.cpu1.num_writes 53662 # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses 44913 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 16880.348216 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15876.450165 # average ReadReq mshr miss latency
+system.cpu1.num_reads 99680 # number of read accesses completed
+system.cpu1.num_writes 54175 # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_hits 7600 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency 629856433 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate 0.830784 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses 37313 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency 592397985 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830784 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses 37313 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 314233420 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses 24350 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 20273.649648 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19269.817033 # average WriteReq mshr miss latency
+system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_hits 925 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency 474910243 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate 0.962012 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses 23425 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency 451395464 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate 0.962012 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses 23425 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 201676231 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1601.319797 # average number of cycles each access was blocked
+system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs 0.408037 # Average number of references to valid blocks.
-system.cpu2.l1c.blocked_no_mshrs 70035 # number of cycles access was blocked
+system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked
system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_mshrs 112148432 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.demand_accesses 69263 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency 18189.052587 # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency
-system.cpu2.l1c.demand_hits 8525 # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency 1104766676 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate 0.876918 # miss rate for demand accesses
-system.cpu2.l1c.demand_misses 60738 # number of demand (read+write) misses
+system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
+system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses
+system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses
system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency 1043793449 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate 0.876918 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses 60738 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.l1c.overall_accesses 69263 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 18189.052587 # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency
+system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits 8525 # number of overall hits
-system.cpu2.l1c.overall_miss_latency 1104766676 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate 0.876918 # miss rate for overall accesses
-system.cpu2.l1c.overall_misses 60738 # number of overall misses
+system.cpu2.l1c.overall_hits 8437 # number of overall hits
+system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses
+system.cpu2.l1c.overall_misses 60562 # number of overall misses
system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency 1043793449 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate 0.876918 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses 60738 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency 515909651 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.l1c.replacements 27950 # number of replacements
-system.cpu2.l1c.sampled_refs 28294 # Sample count of references to valid blocks.
+system.cpu2.l1c.replacements 27725 # number of replacements
+system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks.
system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse 344.355959 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 11545 # Total number of references to valid blocks.
+system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks 10956 # number of writebacks
+system.cpu2.l1c.writebacks 10868 # number of writebacks
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 99987 # number of read accesses completed
-system.cpu2.num_writes 53946 # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses 44879 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 16871.980218 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 15868.081622 # average ReadReq mshr miss latency
+system.cpu2.num_reads 99153 # number of read accesses completed
+system.cpu2.num_writes 52976 # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_hits 7573 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency 629426094 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate 0.831257 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses 37306 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency 591974653 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate 0.831257 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses 37306 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 315451568 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses 24230 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 20326.119616 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 19322.374206 # average WriteReq mshr miss latency
+system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_hits 922 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency 473761196 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate 0.961948 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses 23308 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency 450365898 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961948 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses 23308 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 202979355 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1601.528078 # average number of cycles each access was blocked
+system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs 0.416658 # Average number of references to valid blocks.
-system.cpu3.l1c.blocked_no_mshrs 69967 # number of cycles access was blocked
+system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked
system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_mshrs 112054115 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.demand_accesses 69109 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency 18200.206058 # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency
-system.cpu3.l1c.demand_hits 8495 # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency 1103187290 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate 0.877078 # miss rate for demand accesses
-system.cpu3.l1c.demand_misses 60614 # number of demand (read+write) misses
+system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
+system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses
+system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses
system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency 1042340551 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate 0.877078 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses 60614 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.l1c.overall_accesses 69109 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 18200.206058 # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency
+system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits 8495 # number of overall hits
-system.cpu3.l1c.overall_miss_latency 1103187290 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate 0.877078 # miss rate for overall accesses
-system.cpu3.l1c.overall_misses 60614 # number of overall misses
+system.cpu3.l1c.overall_hits 8535 # number of overall hits
+system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses
+system.cpu3.l1c.overall_misses 60533 # number of overall misses
system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency 1042340551 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate 0.877078 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses 60614 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency 518430923 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.l1c.replacements 27588 # number of replacements
+system.cpu3.l1c.replacements 27562 # number of replacements
system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks.
system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse 346.019907 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 11631 # Total number of references to valid blocks.
+system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks 10783 # number of writebacks
+system.cpu3.l1c.writebacks 10850 # number of writebacks
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99559 # number of read accesses completed
-system.cpu3.num_writes 53870 # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses 44804 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 16848.729876 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 15844.831650 # average ReadReq mshr miss latency
+system.cpu3.num_reads 99282 # number of read accesses completed
+system.cpu3.num_writes 53764 # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_hits 7584 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency 627109726 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate 0.830729 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses 37220 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency 589744634 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate 0.830729 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses 37220 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 313232793 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses 24193 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 20495.832426 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 19492.129507 # average WriteReq mshr miss latency
+system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_hits 866 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency 478106283 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate 0.964205 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses 23327 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency 454692905 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate 0.964205 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses 23327 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 192427965 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1603.347065 # average number of cycles each access was blocked
+system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs 0.413043 # Average number of references to valid blocks.
-system.cpu4.l1c.blocked_no_mshrs 69889 # number of cycles access was blocked
+system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked
system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_mshrs 112056323 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.demand_accesses 68997 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency 18253.852528 # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency
-system.cpu4.l1c.demand_hits 8450 # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency 1105216009 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate 0.877531 # miss rate for demand accesses
-system.cpu4.l1c.demand_misses 60547 # number of demand (read+write) misses
+system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
+system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses
+system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses
system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency 1044437539 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate 0.877531 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses 60547 # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.l1c.overall_accesses 68997 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 18253.852528 # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency
+system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits 8450 # number of overall hits
-system.cpu4.l1c.overall_miss_latency 1105216009 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate 0.877531 # miss rate for overall accesses
-system.cpu4.l1c.overall_misses 60547 # number of overall misses
+system.cpu4.l1c.overall_hits 8435 # number of overall hits
+system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses
+system.cpu4.l1c.overall_misses 60418 # number of overall misses
system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency 1044437539 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate 0.877531 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses 60547 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency 505660758 # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu4.l1c.replacements 27638 # number of replacements
-system.cpu4.l1c.sampled_refs 27985 # Sample count of references to valid blocks.
+system.cpu4.l1c.replacements 27721 # number of replacements
+system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks.
system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse 346.668579 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 11559 # Total number of references to valid blocks.
+system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks 10780 # number of writebacks
+system.cpu4.l1c.writebacks 10846 # number of writebacks
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 99517 # number of read accesses completed
-system.cpu4.num_writes 53554 # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses 45330 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 16742.272952 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15738.453990 # average ReadReq mshr miss latency
+system.cpu4.num_reads 99301 # number of read accesses completed
+system.cpu4.num_writes 53586 # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_hits 7653 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency 630798618 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate 0.831171 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses 37677 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency 592977731 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831171 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses 37677 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 317163872 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses 24208 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 20252.552363 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19248.677491 # average WriteReq mshr miss latency
+system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_hits 928 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency 471479419 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate 0.961666 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses 23280 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency 448109212 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961666 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses 23280 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 202581548 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1592.994331 # average number of cycles each access was blocked
+system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs 0.413221 # Average number of references to valid blocks.
-system.cpu5.l1c.blocked_no_mshrs 70383 # number of cycles access was blocked
+system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked
system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_mshrs 112119720 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.demand_accesses 69538 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency 18082.878701 # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency
-system.cpu5.l1c.demand_hits 8581 # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency 1102278037 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate 0.876600 # miss rate for demand accesses
-system.cpu5.l1c.demand_misses 60957 # number of demand (read+write) misses
+system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
+system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses
+system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses
system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency 1041086943 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate 0.876600 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses 60957 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.l1c.overall_accesses 69538 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 18082.878701 # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency
+system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits 8581 # number of overall hits
-system.cpu5.l1c.overall_miss_latency 1102278037 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate 0.876600 # miss rate for overall accesses
-system.cpu5.l1c.overall_misses 60957 # number of overall misses
+system.cpu5.l1c.overall_hits 8362 # number of overall hits
+system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses
+system.cpu5.l1c.overall_misses 60470 # number of overall misses
system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency 1041086943 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate 0.876600 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses 60957 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency 519745420 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu5.l1c.replacements 28012 # number of replacements
-system.cpu5.l1c.sampled_refs 28365 # Sample count of references to valid blocks.
+system.cpu5.l1c.replacements 27632 # number of replacements
+system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks.
system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse 347.429877 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 11721 # Total number of references to valid blocks.
+system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks 10901 # number of writebacks
+system.cpu5.l1c.writebacks 10950 # number of writebacks
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 100000 # number of read accesses completed
-system.cpu5.num_writes 53842 # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses 45124 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 16852.177623 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15848.333619 # average ReadReq mshr miss latency
+system.cpu5.num_reads 99024 # number of read accesses completed
+system.cpu5.num_writes 53903 # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_hits 7719 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency 630355704 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate 0.828938 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses 37405 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 592806919 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.828938 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 313955648 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses 24360 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 20279.291722 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19275.372628 # average WriteReq mshr miss latency
+system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_hits 913 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency 475488553 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate 0.962521 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses 23447 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency 451949662 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962521 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses 23447 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 198611435 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1598.405866 # average number of cycles each access was blocked
+system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs 0.418615 # Average number of references to valid blocks.
-system.cpu6.l1c.blocked_no_mshrs 70240 # number of cycles access was blocked
+system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked
system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_mshrs 112272028 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.demand_accesses 69484 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency 18172.685483 # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency
-system.cpu6.l1c.demand_hits 8632 # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency 1105844257 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate 0.875770 # miss rate for demand accesses
-system.cpu6.l1c.demand_misses 60852 # number of demand (read+write) misses
+system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
+system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses
+system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses
system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency 1044756581 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate 0.875770 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses 60852 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.l1c.overall_accesses 69484 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 18172.685483 # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency
+system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits 8632 # number of overall hits
-system.cpu6.l1c.overall_miss_latency 1105844257 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate 0.875770 # miss rate for overall accesses
-system.cpu6.l1c.overall_misses 60852 # number of overall misses
+system.cpu6.l1c.overall_hits 8396 # number of overall hits
+system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses
+system.cpu6.l1c.overall_misses 60973 # number of overall misses
system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency 1044756581 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate 0.875770 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses 60852 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency 512567083 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu6.l1c.replacements 27959 # number of replacements
-system.cpu6.l1c.sampled_refs 28310 # Sample count of references to valid blocks.
+system.cpu6.l1c.replacements 28139 # number of replacements
+system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks.
system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse 344.892132 # Cycle average of tags in use
-system.cpu6.l1c.total_refs 11851 # Total number of references to valid blocks.
+system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks 11044 # number of writebacks
+system.cpu6.l1c.writebacks 11130 # number of writebacks
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 99626 # number of read accesses completed
-system.cpu6.num_writes 53905 # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses 44909 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 16826.619219 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15822.802503 # average ReadReq mshr miss latency
+system.cpu6.num_reads 100000 # number of read accesses completed
+system.cpu6.num_writes 54239 # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_hits 7759 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency 625108904 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate 0.827228 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses 37150 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 587817113 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.827228 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses 37150 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 317908383 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses 24427 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 20228.908213 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 19225.075071 # average WriteReq mshr miss latency
+system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_hits 916 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency 475601861 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate 0.962501 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses 23511 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency 452000740 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962501 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses 23511 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 197920310 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1598.930420 # average number of cycles each access was blocked
+system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs 0.421584 # Average number of references to valid blocks.
-system.cpu7.l1c.blocked_no_mshrs 70034 # number of cycles access was blocked
+system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked
system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_mshrs 111979493 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.demand_accesses 69336 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency 18145.278927 # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency
-system.cpu7.l1c.demand_hits 8675 # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency 1100710765 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate 0.874885 # miss rate for demand accesses
-system.cpu7.l1c.demand_misses 60661 # number of demand (read+write) misses
+system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
+system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses
+system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses
system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency 1039817853 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate 0.874885 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses 60661 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.l1c.overall_accesses 69336 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 18145.278927 # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency
+system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits 8675 # number of overall hits
-system.cpu7.l1c.overall_miss_latency 1100710765 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate 0.874885 # miss rate for overall accesses
-system.cpu7.l1c.overall_misses 60661 # number of overall misses
+system.cpu7.l1c.overall_hits 8481 # number of overall hits
+system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses
+system.cpu7.l1c.overall_misses 60440 # number of overall misses
system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency 1039817853 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate 0.874885 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses 60661 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency 515828693 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -628,88 +628,88 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued 0 #
system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu7.l1c.replacements 27690 # number of replacements
-system.cpu7.l1c.sampled_refs 28049 # Sample count of references to valid blocks.
+system.cpu7.l1c.replacements 27627 # number of replacements
+system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks.
system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse 343.299146 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 11825 # Total number of references to valid blocks.
+system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks 10985 # number of writebacks
+system.cpu7.l1c.writebacks 10984 # number of writebacks
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99331 # number of read accesses completed
-system.cpu7.num_writes 53962 # number of write accesses completed
-system.l2c.ReadExReq_accesses 75034 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 19990.930951 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 10006.831093 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 1499999513 # number of ReadExReq miss cycles
+system.cpu7.num_reads 99634 # number of read accesses completed
+system.cpu7.num_writes 53744 # number of write accesses completed
+system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 75034 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits 354 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency 747310146 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.995282 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 74680 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 139261 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 19959.179983 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 10007.689712 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 91062 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 962012516 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.346106 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 48199 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 611 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 476245938 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.341718 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 47588 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 793404880 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 18516 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 11019.424390 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 10007.005085 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 204035662 # number of UpgradeReq miss cycles
+system.l2c.ReadReq_hits 89906 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 48016 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 18516 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_miss_latency 184989496 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 0.998380 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 18486 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 430707040 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 86799 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 86799 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs 2909.833333 # average number of cycles each access was blocked
+system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 86929 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.988478 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked
+system.l2c.avg_refs 2.005630 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 17459 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 214295 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 19978.512484 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency
-system.l2c.demand_hits 91062 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 2462012029 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.575062 # miss rate for demand accesses
-system.l2c.demand_misses 123233 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 965 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 1223556084 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.570559 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 122268 # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses 213064 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
+system.l2c.demand_hits 89906 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses
+system.l2c.demand_misses 123158 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 214295 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 19978.512484 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency
+system.l2c.overall_accesses 213064 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 91062 # number of overall hits
-system.l2c.overall_miss_latency 2462012029 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.575062 # miss rate for overall accesses
-system.l2c.overall_misses 123233 # number of overall misses
-system.l2c.overall_mshr_hits 965 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 1223556084 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.570559 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 122268 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1224111920 # number of overall MSHR uncacheable cycles
+system.l2c.overall_hits 89906 # number of overall hits
+system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses
+system.l2c.overall_misses 123158 # number of overall misses
+system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@@ -720,12 +720,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 74376 # number of replacements
-system.l2c.sampled_refs 74986 # Sample count of references to valid blocks.
+system.l2c.replacements 73303 # number of replacements
+system.l2c.sampled_refs 73894 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 633.319008 # Cycle average of tags in use
-system.l2c.total_refs 149108 # Total number of references to valid blocks.
+system.l2c.tagsinuse 633.737828 # Cycle average of tags in use
+system.l2c.total_refs 148204 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 47583 # number of writebacks
+system.l2c.writebacks 47216 # number of writebacks
---------- End Simulation Statistics ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
index f89b5d5ce..a93b081cc 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
@@ -1,74 +1,74 @@
warn: Entering event queue @ 0. Starting simulation...
-system.cpu2: completed 10000 read accesses @10889862
-system.cpu6: completed 10000 read accesses @10965571
-system.cpu0: completed 10000 read accesses @10999807
-system.cpu1: completed 10000 read accesses @11061066
-system.cpu3: completed 10000 read accesses @11070068
-system.cpu5: completed 10000 read accesses @11143240
-system.cpu7: completed 10000 read accesses @11205415
-system.cpu4: completed 10000 read accesses @11436114
-system.cpu5: completed 20000 read accesses @22318031
-system.cpu2: completed 20000 read accesses @22337080
-system.cpu0: completed 20000 read accesses @22381736
-system.cpu6: completed 20000 read accesses @22509672
-system.cpu1: completed 20000 read accesses @22762640
-system.cpu7: completed 20000 read accesses @22874302
-system.cpu3: completed 20000 read accesses @22934916
-system.cpu4: completed 20000 read accesses @22955693
-system.cpu2: completed 30000 read accesses @33671766
-system.cpu5: completed 30000 read accesses @33722420
-system.cpu0: completed 30000 read accesses @33817843
-system.cpu1: completed 30000 read accesses @34138032
-system.cpu3: completed 30000 read accesses @34173736
-system.cpu6: completed 30000 read accesses @34210820
-system.cpu7: completed 30000 read accesses @34282426
-system.cpu4: completed 30000 read accesses @34509982
-system.cpu2: completed 40000 read accesses @45029426
-system.cpu5: completed 40000 read accesses @45134036
-system.cpu0: completed 40000 read accesses @45316016
-system.cpu3: completed 40000 read accesses @45518533
-system.cpu6: completed 40000 read accesses @45639311
-system.cpu1: completed 40000 read accesses @45681507
-system.cpu7: completed 40000 read accesses @45794833
-system.cpu4: completed 40000 read accesses @46027115
-system.cpu2: completed 50000 read accesses @56302892
-system.cpu5: completed 50000 read accesses @56333031
-system.cpu3: completed 50000 read accesses @56769550
-system.cpu0: completed 50000 read accesses @56860279
-system.cpu1: completed 50000 read accesses @56989965
-system.cpu7: completed 50000 read accesses @57056302
-system.cpu6: completed 50000 read accesses @57079409
-system.cpu4: completed 50000 read accesses @57116196
-system.cpu2: completed 60000 read accesses @67583365
-system.cpu5: completed 60000 read accesses @67785565
-system.cpu3: completed 60000 read accesses @68057386
-system.cpu0: completed 60000 read accesses @68158806
-system.cpu4: completed 60000 read accesses @68296537
-system.cpu6: completed 60000 read accesses @68386914
-system.cpu7: completed 60000 read accesses @68429516
-system.cpu1: completed 60000 read accesses @68460666
-system.cpu2: completed 70000 read accesses @79111322
-system.cpu5: completed 70000 read accesses @79209430
-system.cpu4: completed 70000 read accesses @79635720
-system.cpu0: completed 70000 read accesses @79745526
-system.cpu3: completed 70000 read accesses @79788385
-system.cpu1: completed 70000 read accesses @79799686
-system.cpu7: completed 70000 read accesses @79866566
-system.cpu6: completed 70000 read accesses @79989630
-system.cpu5: completed 80000 read accesses @90523593
-system.cpu2: completed 80000 read accesses @90753657
-system.cpu4: completed 80000 read accesses @91052610
-system.cpu6: completed 80000 read accesses @91127936
-system.cpu0: completed 80000 read accesses @91167181
-system.cpu1: completed 80000 read accesses @91235432
-system.cpu3: completed 80000 read accesses @91277914
-system.cpu7: completed 80000 read accesses @91382669
-system.cpu2: completed 90000 read accesses @101882254
-system.cpu5: completed 90000 read accesses @101888287
-system.cpu1: completed 90000 read accesses @102242250
-system.cpu4: completed 90000 read accesses @102331682
-system.cpu6: completed 90000 read accesses @102446126
-system.cpu3: completed 90000 read accesses @102480895
-system.cpu0: completed 90000 read accesses @102517256
-system.cpu7: completed 90000 read accesses @102831150
-system.cpu5: completed 100000 read accesses @113467820
+system.cpu3: completed 10000 read accesses @26226880
+system.cpu6: completed 10000 read accesses @26416342
+system.cpu2: completed 10000 read accesses @26427251
+system.cpu5: completed 10000 read accesses @26798889
+system.cpu0: completed 10000 read accesses @26886521
+system.cpu7: completed 10000 read accesses @27109446
+system.cpu1: completed 10000 read accesses @27197408
+system.cpu4: completed 10000 read accesses @27318359
+system.cpu3: completed 20000 read accesses @53279230
+system.cpu6: completed 20000 read accesses @53417084
+system.cpu2: completed 20000 read accesses @53757092
+system.cpu0: completed 20000 read accesses @53888320
+system.cpu5: completed 20000 read accesses @53947132
+system.cpu4: completed 20000 read accesses @54390092
+system.cpu1: completed 20000 read accesses @54397720
+system.cpu7: completed 20000 read accesses @54632966
+system.cpu6: completed 30000 read accesses @80144176
+system.cpu3: completed 30000 read accesses @80518264
+system.cpu0: completed 30000 read accesses @80638600
+system.cpu5: completed 30000 read accesses @80869702
+system.cpu1: completed 30000 read accesses @81289158
+system.cpu2: completed 30000 read accesses @81358716
+system.cpu7: completed 30000 read accesses @81981296
+system.cpu4: completed 30000 read accesses @82043104
+system.cpu6: completed 40000 read accesses @107087547
+system.cpu0: completed 40000 read accesses @107662142
+system.cpu3: completed 40000 read accesses @107722516
+system.cpu5: completed 40000 read accesses @107884124
+system.cpu1: completed 40000 read accesses @107981413
+system.cpu7: completed 40000 read accesses @108415286
+system.cpu2: completed 40000 read accesses @108655120
+system.cpu4: completed 40000 read accesses @109427858
+system.cpu6: completed 50000 read accesses @133583246
+system.cpu0: completed 50000 read accesses @133832383
+system.cpu5: completed 50000 read accesses @134755386
+system.cpu1: completed 50000 read accesses @134792594
+system.cpu7: completed 50000 read accesses @134914312
+system.cpu3: completed 50000 read accesses @134993978
+system.cpu2: completed 50000 read accesses @135362549
+system.cpu4: completed 50000 read accesses @135394370
+system.cpu0: completed 60000 read accesses @160410176
+system.cpu6: completed 60000 read accesses @160667590
+system.cpu7: completed 60000 read accesses @161466346
+system.cpu1: completed 60000 read accesses @161592434
+system.cpu5: completed 60000 read accesses @161656374
+system.cpu4: completed 60000 read accesses @161882626
+system.cpu2: completed 60000 read accesses @162062631
+system.cpu3: completed 60000 read accesses @162154299
+system.cpu6: completed 70000 read accesses @187592265
+system.cpu1: completed 70000 read accesses @188138542
+system.cpu7: completed 70000 read accesses @188373105
+system.cpu0: completed 70000 read accesses @188690782
+system.cpu3: completed 70000 read accesses @189309687
+system.cpu2: completed 70000 read accesses @189360790
+system.cpu4: completed 70000 read accesses @189391126
+system.cpu5: completed 70000 read accesses @189902895
+system.cpu6: completed 80000 read accesses @214739574
+system.cpu1: completed 80000 read accesses @215665444
+system.cpu0: completed 80000 read accesses @216021457
+system.cpu7: completed 80000 read accesses @216394344
+system.cpu3: completed 80000 read accesses @216537382
+system.cpu4: completed 80000 read accesses @216775798
+system.cpu2: completed 80000 read accesses @216868662
+system.cpu5: completed 80000 read accesses @217401619
+system.cpu6: completed 90000 read accesses @241415090
+system.cpu1: completed 90000 read accesses @242558992
+system.cpu0: completed 90000 read accesses @242897388
+system.cpu7: completed 90000 read accesses @243372191
+system.cpu3: completed 90000 read accesses @243630762
+system.cpu5: completed 90000 read accesses @243633950
+system.cpu4: completed 90000 read accesses @243710816
+system.cpu2: completed 90000 read accesses @243974160
+system.cpu6: completed 100000 read accesses @268915439
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index d0d9bd67d..7382eca3b 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:12:56
-M5 started Mon Jul 21 20:18:03 2008
+M5 compiled Aug 2 2008 17:07:15
+M5 started Sat Aug 2 17:07:20 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 113467820 because maximum number of loads reached
+Exiting @ tick 268915439 because maximum number of loads reached
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 5ae2e325d..4a385ded6 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
-readfile=/z/binkertn/regress/m5/configs/boot/netperf-server.rcS
+readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
@@ -156,7 +156,7 @@ pio=drivesys.membus.default
[drivesys.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
@@ -698,7 +698,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
-readfile=/z/binkertn/regress/m5/configs/boot/netperf-stream-client.rcS
+readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
@@ -840,7 +840,7 @@ pio=testsys.membus.default
[testsys.physmem]
type=PhysicalMemory
file=
-latency=1
+latency=30000
latency_var=0
null=false
range=0:134217727
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
index 03c1ec15e..6315d7b3d 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
@@ -39,8 +39,8 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu
drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl
@@ -59,8 +59,8 @@ drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # f
drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
drivesys.cpu.kern.syscall 22 # number of syscalls executed
drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed
@@ -76,7 +76,7 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu
drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles
-drivesys.cpu.numCycles 199572412849 # number of cpu cycles simulated
+drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
drivesys.cpu.num_insts 1958129 # Number of instructions executed
drivesys.cpu.num_refs 626223 # Number of memory references
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@@ -139,76 +139,76 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 222632706 # Simulator instruction rate (inst/s)
-host_mem_usage 479796 # Number of bytes of host memory used
-host_seconds 1.23 # Real time elapsed on the host
-host_tick_rate 162907421274 # Simulator tick rate (ticks/s)
+host_inst_rate 162488534 # Simulator instruction rate (inst/s)
+host_mem_usage 477336 # Number of bytes of host memory used
+host_seconds 1.68 # Real time elapsed on the host
+host_tick_rate 118897556170 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 273294782 # Number of instructions simulated
+sim_insts 273294177 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
sim_ticks 200000789468 # Number of ticks simulated
testsys.cpu.dtb.accesses 335402 # DTB accesses
testsys.cpu.dtb.acv 161 # DTB access violations
-testsys.cpu.dtb.hits 1163322 # DTB hits
+testsys.cpu.dtb.hits 1163288 # DTB hits
testsys.cpu.dtb.misses 3815 # DTB misses
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
-testsys.cpu.dtb.read_hits 658456 # DTB read hits
+testsys.cpu.dtb.read_hits 658435 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
-testsys.cpu.dtb.write_hits 504866 # DTB write hits
+testsys.cpu.dtb.write_hits 504853 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles
-testsys.cpu.itb.accesses 1249851 # ITB accesses
+testsys.cpu.itb.accesses 1249822 # ITB accesses
testsys.cpu.itb.acv 69 # ITB acv
-testsys.cpu.itb.hits 1248354 # ITB hits
+testsys.cpu.itb.hits 1248325 # ITB hits
testsys.cpu.itb.misses 1497 # ITB misses
-testsys.cpu.kern.callpal 13125 # number of callpals executed
+testsys.cpu.kern.callpal 13122 # number of callpals executed
testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed
testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed
-testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed
+testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed
testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed
testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed
-testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed
+testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed
testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed
testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed
testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed
+testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed
testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed
-testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.mode_good_kernel 655
-testsys.cpu.kern.mode_good_user 650
+testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.mode_good_kernel 654
+testsys.cpu.kern.mode_good_user 649
testsys.cpu.kern.mode_good_idle 5
-testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches
-testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches
-testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches
-testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches
+testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches
+testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches
+testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.cpu.kern.syscall 83 # number of syscalls executed
testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed
@@ -233,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu
testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles
-testsys.cpu.numCycles 199570420361 # number of cpu cycles simulated
-testsys.cpu.num_insts 3560518 # Number of instructions executed
-testsys.cpu.num_refs 1173605 # Number of memory references
+testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
+testsys.cpu.num_insts 3560411 # Number of instructions executed
+testsys.cpu.num_refs 1173571 # Number of memory references
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 225676946325 # Simulator instruction rate (inst/s)
-host_mem_usage 479796 # Number of bytes of host memory used
+host_inst_rate 147646773096 # Simulator instruction rate (inst/s)
+host_mem_usage 477336 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 612132399 # Simulator tick rate (ticks/s)
+host_tick_rate 399988804 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 273294782 # Number of instructions simulated
+sim_insts 273294177 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 785978 # Number of ticks simulated
testsys.cpu.dtb.accesses 0 # DTB accesses
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
index 66e5a984c..e7a8e93ac 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
@@ -1,8 +1,8 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for testsys connection on port 3457
+Listening for testsys connection on port 3456
warn: kernel located at: /dist/m5/system/binaries/vmlinux
-Listening for drivesys connection on port 3461
-0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7006
-0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7007
+Listening for drivesys connection on port 3457
+0: testsys.remote_gdb.listener: listening for remote gdb on port 7005
+0: drivesys.remote_gdb.listener: listening for remote gdb on port 7006
warn: Entering event queue @ 0. Starting simulation...
-warn: Obsolete M5 instruction ivlb encountered.
+warn: Obsolete M5 ivlb instruction encountered.
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
index c137b03cf..d355bed12 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 21 2008 20:27:21
-M5 started Mon Jul 21 20:27:45 2008
+M5 compiled Aug 2 2008 17:07:34
+M5 started Sat Aug 2 17:07:37 2008
M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 4300235844056 because checkpoint
+Exiting @ tick 4300236804024 because checkpoint